From 800f607e38c904c10917a372fee24735a903302b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 5 Jan 2009 15:52:11 +0000 Subject: [PATCH] first full hades endpoint --- trb_net16_api_base.vhd | 5 +- trb_net16_endpoint_1_trg_2_data_1_regio.vhd | 21 +- trb_net16_endpoint_hades_full.vhd | 1024 +++++++++++++++++++ trb_net16_iobuf.vhd | 1 - trb_net16_ipudata.vhd | 139 ++- trb_net16_regIO.vhd | 6 +- trb_net16_trigger.vhd | 11 +- trb_net_std.vhd | 6 +- 8 files changed, 1164 insertions(+), 49 deletions(-) create mode 100644 trb_net16_endpoint_hades_full.vhd diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index fea00ce..8b5d64b 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -580,7 +580,8 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; process(master_counter, fifo_to_int_data_out, combined_header_F1, registered_trailer_F1, combined_trailer_F1, combined_header_F2, registered_trailer_F2, combined_trailer_F2, combined_header_F3, registered_trailer_F3, combined_trailer_F3, combined_header_F0, - registered_trailer_F0) + registered_trailer_F0,registered_header_F0, registered_header_F1, registered_header_F2, + registered_header_F3) begin case master_counter is when c_F0 => @@ -1005,7 +1006,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end if; end if; end process; - + --for simulation only diff --git a/trb_net16_endpoint_1_trg_2_data_1_regio.vhd b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd index 8aadcaa..7b5a213 100644 --- a/trb_net16_endpoint_1_trg_2_data_1_regio.vhd +++ b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd @@ -1,4 +1,4 @@ --- the full endpoint for HADES: trg, data, data, regio +-- the full endpoint for HADES: trg, data, unused, regio LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; @@ -9,19 +9,24 @@ library work; use work.trb_net_std.all; - -entity trb_net16_endpoint_1_trg_2_api_1_regio is +entity trb_net16_endpoint_hades_full is generic ( - USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); API_TYPE : channel_config_t := (c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE,c_API_PASSIVE); - IBUF_DEPTH : channel_config_t := (0,6,6,6); - FIFO_TO_INT_DEPTH : channel_config_t := (0,6,6,6); - FIFO_TO_APL_DEPTH : channel_config_t := (0,6,6,6); + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + + + SCTR_NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers SCTR_NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers --standard values for output registers @@ -891,7 +896,7 @@ begin STAT => SCTR_REGIO_STAT ); end generate; - + gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN; buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd new file mode 100644 index 0000000..57c440e --- /dev/null +++ b/trb_net16_endpoint_hades_full.vhd @@ -0,0 +1,1024 @@ +-- the full endpoint for HADES: trg, data, unused, regio + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +entity trb_net16_endpoint_hades_full is + generic ( + USE_CHANNEL : channel_config_t := (c_YES,c_YES,c_NO,c_YES); + IBUF_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_INT_DEPTH : channel_config_t := (6,6,6,6); + FIFO_TO_APL_DEPTH : channel_config_t := (6,6,6,6); + IBUF_SECURE_MODE : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_APL : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + API_SECURE_MODE_TO_INT : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH; + INIT_CAN_SEND_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + REPLY_CAN_SEND_DATA : channel_config_t := (c_YES,c_YES,c_YES,c_YES); + REPLY_CAN_RECEIVE_DATA : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + USE_CHECKSUM : channel_config_t := (c_NO,c_YES,c_YES,c_YES); + APL_WRITE_ALL_WORDS : channel_config_t := (c_NO,c_NO,c_NO,c_NO); + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"; + REGIO_NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + REGIO_NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + REGIO_INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); + --set to 0 for unused ctrl registers to save resources + REGIO_USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + REGIO_USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); + REGIO_USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + REGIO_USE_1WIRE_INTERFACE: integer := c_YES + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic; + + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + + MED_STAT_OP_IN : in std_logic_vector(15 downto 0); + MED_CTRL_OP_OUT : out std_logic_vector(15 downto 0); + + -- LVL1 trigger APL + LVL1_TRG_TYPE_OUT : out std_logic_vector(3 downto 0); + LVL1_TRG_RECEIVED_OUT : out std_logic; + LVL1_TRG_NUMBER_OUT : out std_logic_vector(15 downto 0); + LVL1_TRG_CODE_OUT : out std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_OUT : out std_logic_vector(7 downto 0); + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_TRG_RELEASE_IN : in std_logic := '0'; + + + --Data Port + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + -- Slow Control Data Port + REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); + REGIO_REGISTERS_IN : in std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0'); + REGIO_REGISTERS_OUT : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0); + --following ports only used when using internal data port + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + --IDRAM is used if no 1-wire interface, onewire used otherwise + REGIO_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); + REGIO_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + REGIO_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + REGIO_IDRAM_WR_IN : in std_logic := '0'; + REGIO_ONEWIRE_INOUT : inout std_logic; + --Additional r/w access to ctrl registers + REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); + REGIO_EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_EXT_REG_WRITE_IN : in std_logic := '0'; + REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0'); + + STAT_DEBUG_IPU : out std_logic_vector (31 downto 0); + STAT_DEBUG_1 : out std_logic_vector (31 downto 0); + STAT_DEBUG_2 : out std_logic_vector (31 downto 0); + MED_STAT_OP : out std_logic_vector (15 downto 0); + CTRL_MPLEX : in std_logic_vector (31 downto 0); + IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0); + STAT_ONEWIRE : out std_logic_vector (31 downto 0) + ); +end entity; + + + + + +architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full is + + component trb_net_onewire is + generic( + USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1; + CLK_PERIOD : integer := 10 --clk period in ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --connection to 1-wire interface + ONEWIRE : inout std_logic; + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector(2 downto 0); + WRITE_OUT: out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_regIO is + generic ( + NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers + NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers + --standard values for output registers + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '0'); + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := + (others => '1'); + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + + --Port to write Unique ID + IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); + IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); + IDRAM_WR_IN : in std_logic; + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + + --Common Register in / out + COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*c_REGIO_REG_WIDTH-1 downto 0); + COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*c_REGIO_REG_WIDTH-1 downto 0); + --Custom Register in / out + REGISTERS_IN : in std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_STAT_REGS)-1 downto 0); + REGISTERS_OUT : out std_logic_vector(c_REGIO_REG_WIDTH*2**(NUM_CTRL_REGS)-1 downto 0); + --Internal Data Port + DAT_ADDR_OUT : out std_logic_vector(c_REGIO_ADDRESS_WIDTH-1 downto 0); + DAT_READ_ENABLE_OUT : out std_logic; + DAT_WRITE_ENABLE_OUT: out std_logic; + DAT_DATA_OUT : out std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATA_IN : in std_logic_vector(c_REGIO_REG_WIDTH-1 downto 0); + DAT_DATAREADY_IN : in std_logic; + DAT_NO_MORE_DATA_IN : in std_logic; + DAT_WRITE_ACK_IN : in std_logic; + DAT_UNKNOWN_ADDR_IN : in std_logic; + DAT_TIMEOUT_OUT : out std_logic; + + --Additional write access to ctrl registers + EXT_REG_DATA_IN : in std_logic_vector(31 downto 0); + EXT_REG_DATA_OUT : out std_logic_vector(31 downto 0); + EXT_REG_WRITE_IN : in std_logic; + EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0); + STAT : out std_logic_vector(31 downto 0) + ); + end component; + + component trb_net16_iobuf is + generic ( + IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; + IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;--std_IBUF_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; -- Data word is offered by the Media(the IOBUF MUST read) + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + + -- Internal direction port + INT_INIT_DATAREADY_OUT: out std_logic; + INT_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_IN: in std_logic; + + INT_INIT_DATAREADY_IN: in std_logic; + INT_INIT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_INIT_READ_OUT: out std_logic; + + INT_REPLY_DATAREADY_OUT: out std_logic; + INT_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_IN: in std_logic; + + INT_REPLY_DATAREADY_IN: in std_logic; + INT_REPLY_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_IN :in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_REPLY_READ_OUT: out std_logic; + + -- Status and control port + STAT_GEN : out std_logic_vector (31 downto 0); + STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); + CTRL_GEN : in std_logic_vector (31 downto 0); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_api_base is + generic ( + API_TYPE : integer range 0 to 1 := c_API_PASSIVE; + FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--std_FIFO_DEPTH; + FIFO_TO_APL_DEPTH : integer range 1 to 6 := 6;--std_FIFO_DEPTH; + FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES; + SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES; + APL_WRITE_ALL_WORDS:integer range 0 to 1 := c_NO; + BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF" + ); + + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- APL Transmitter port + APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_DATAREADY_IN : in std_logic; + APL_READ_OUT : out std_logic; + APL_SHORT_TRANSFER_IN : in std_logic; + APL_DTYPE_IN : in std_logic_vector (3 downto 0); + APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + APL_SEND_IN : in std_logic; + APL_TARGET_ADDRESS_IN : in std_logic_vector (15 downto 0);-- the target (only for active APIs) + + -- Receiver port + APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + APL_TYP_OUT : out std_logic_vector (2 downto 0); + APL_DATAREADY_OUT : out std_logic; + APL_READ_IN : in std_logic; + + -- APL Control port + APL_RUN_OUT : out std_logic; + APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + APL_SEQNR_OUT : out std_logic_vector (7 downto 0); + APL_LENGTH_IN : in std_logic_vector (15 downto 0); + + -- Internal direction port + -- the ports with master or slave in their name are to be mapped by the active api + -- to the init respectivly the reply path and vice versa in the passive api. + -- lets define: the "master" path is the path that I send data on. + -- master_data_out and slave_data_in are only used in active API for termination + INT_MASTER_DATAREADY_OUT : out std_logic; + INT_MASTER_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_IN : in std_logic; + + INT_MASTER_DATAREADY_IN : in std_logic; + INT_MASTER_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_MASTER_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_MASTER_READ_OUT : out std_logic; + + INT_SLAVE_DATAREADY_OUT : out std_logic; + INT_SLAVE_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_IN : in std_logic; + + INT_SLAVE_DATAREADY_IN : in std_logic; + INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_SLAVE_READ_OUT : out std_logic; + + -- Status and control port + STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); + STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) + ); + end component; + + + + component trb_net16_io_multiplexer is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in STD_LOGIC; + + -- Internal direction port + INT_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); + INT_DATAREADY_OUT: out STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + INT_READ_IN: in STD_LOGIC_VECTOR (2**(c_MUX_WIDTH-1)-1 downto 0); + + INT_DATAREADY_IN: in STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + INT_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0); + INT_READ_OUT: out STD_LOGIC_VECTOR (2**c_MUX_WIDTH-1 downto 0); + + -- Status and control port + CTRL: in STD_LOGIC_VECTOR (31 downto 0); + STAT: out STD_LOGIC_VECTOR (31 downto 0) + ); + end component; + + component trb_net16_term_buf is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + MED_INIT_DATAREADY_OUT: out std_logic; + MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_INIT_READ_IN: in std_logic; + + MED_REPLY_DATAREADY_OUT: out std_logic; + MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_REPLY_READ_IN: in std_logic; + + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word + MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic + ); + end component; + + component trb_net16_trigger is + generic ( + USE_TRG_PORT : integer range 0 to 1 := c_YES; + --even when NO, ERROR_PACKET_IN is used for automatic replys + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE + --if secure_mode is not used, apl must provide error pattern and dtype until + --next trigger comes in. In secure mode these need to be available while relase_trg is high only + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + + -- Trigger information output + TRG_TYPE_OUT : out std_logic_vector (3 downto 0); + TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); + TRG_CODE_OUT : out std_logic_vector (7 downto 0); + TRG_INFORMATION_OUT : out std_logic_vector (7 downto 0); + TRG_RECEIVED_OUT : out std_logic; + TRG_RELEASE_IN : in std_logic; + TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) + ); + end component; + + component trb_net16_ipudata is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_LENGTH_OUT : out std_logic_vector (15 downto 0); + + --Information received with request + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe + IPU_START_READOUT_OUT: out std_logic; + --detector data, equipped with DHDR + IPU_DATA_IN : in std_logic_vector (31 downto 0); + IPU_DATAREADY_IN : in std_logic; + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN : in std_logic; + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT : out std_logic; + IPU_LENGTH_IN : in std_logic_vector (15 downto 0); + IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); + + STAT_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + +signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_INIT_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_INIT_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_INIT_READ : std_logic_vector(3 downto 0); + +signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal apl_to_buf_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal apl_to_buf_REPLY_READ : std_logic_vector(3 downto 0); + +signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0); +signal buf_to_apl_REPLY_DATA : std_logic_vector (4*c_DATA_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0); +signal buf_to_apl_REPLY_READ : std_logic_vector(3 downto 0); + +-- for the connection to the multiplexer +signal MED_IO_DATAREADY_IN : std_logic_vector(3 downto 0); +signal MED_IO_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_OUT : std_logic_vector(3 downto 0); + +signal MED_IO_DATAREADY_OUT : std_logic_vector(7 downto 0); +signal MED_IO_DATA_OUT : std_logic_vector (8*c_DATA_WIDTH-1 downto 0); +signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0); +signal MED_IO_READ_IN : std_logic_vector(7 downto 0); + +signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0); +signal buf_APL_READ_OUT : std_logic_vector(3 downto 0); +signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0); +signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0); +signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0); +signal buf_APL_SEND_IN : std_logic_vector(3 downto 0); +signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0); +signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0); +signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0); +signal buf_APL_READ_IN : std_logic_vector(3 downto 0); +signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0); +signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0); +signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0); +signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0); + +signal MY_ADDRESS : std_logic_vector(15 downto 0); + +signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0); +signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0); +signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0); +signal buf_STAT_INIT_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); +signal buf_STAT_REPLY_OBUF_DEBUG : std_logic_vector (32*4-1 downto 0); + +signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0); + +signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0); + +signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0); +signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); +signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); +signal buf_IDRAM_WR_IN : std_logic; +signal reset_internal : std_logic; + +begin + + reset_internal <= MED_STAT_OP_IN(13) or RESET; + MED_CTRL_OP_OUT(15) <= MED_STAT_OP_IN(15); + MED_CTRL_OP_OUT(14 downto 0) <= (others => '0'); + MED_STAT_OP <= MED_STAT_OP_IN; + + --Connections for data channel + genbuffers : for i in 0 to 3 generate + geniobuf: if USE_CHANNEL(i) = c_YES generate + IOBUF: trb_net16_iobuf + generic map ( + IBUF_DEPTH => IBUF_DEPTH(i), + IBUF_SECURE_MODE => IBUF_SECURE_MODE(i), + SBUF_VERSION => 0, + OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(i), + USE_CHECKSUM => USE_CHECKSUM(i), + USE_VENDOR_CORES => c_YES, + INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA(i), + REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i), + REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA(i) + ) + port map ( + -- Misc + CLK => CLK , + RESET => RESET, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + MED_ERROR_IN => MED_STAT_OP_IN(2 downto 0), + + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1), + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), + INT_INIT_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_IN => buf_to_apl_INIT_READ(i), + + INT_INIT_DATAREADY_IN => apl_to_buf_INIT_DATAREADY(i), + INT_INIT_DATA_IN => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_INIT_READ_OUT => apl_to_buf_INIT_READ(i), + + INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i), + INT_REPLY_DATA_OUT => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_IN => buf_to_apl_REPLY_READ(i), + + INT_REPLY_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), + INT_REPLY_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_REPLY_READ_OUT => apl_to_buf_REPLY_READ(i), + + -- Status and control port + STAT_GEN => buf_STAT_GEN(32*(i+1)-1 downto i*32), + STAT_IBUF_BUFFER => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32), + CTRL_GEN => buf_CTRL_GEN(32*(i+1)-1 downto i*32), + STAT_INIT_OBUF_DEBUG => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32), + STAT_REPLY_OBUF_DEBUG => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32) + ); + + gen_api : if i /= c_TRG_LVL1_CHANNEL generate + constant j : integer := i; + begin + DAT_PASSIVE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i), + FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i), + FORCE_REPLY => cfg_FORCE_REPLY(i), + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => API_SECURE_MODE_TO_APL(i), + SECURE_MODE_TO_INT => API_SECURE_MODE_TO_INT(i), + APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i), + BROADCAST_BITMASK => BROADCAST_BITMASK + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_DATAREADY_IN => buf_APL_DATAREADY_IN(j), + APL_READ_OUT => buf_APL_READ_OUT(j), + APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j), + APL_DTYPE_IN => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4), + APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32), + APL_SEND_IN => buf_APL_SEND_IN(j), + APL_TARGET_ADDRESS_IN => (others => '0'), + -- Receiver port + APL_DATA_OUT => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH), + APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH), + APL_TYP_OUT => buf_APL_TYP_OUT((j+1)*3-1 downto j*3), + APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j), + APL_READ_IN => buf_APL_READ_IN(j), + -- APL Control port + APL_RUN_OUT => buf_APL_RUN_OUT(j), + APL_MY_ADDRESS_IN => MY_ADDRESS, + APL_SEQNR_OUT => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8), + APL_LENGTH_IN => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16), + -- Internal direction port + INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_MASTER_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_IN => apl_to_buf_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_SLAVE_DATAREADY_OUT => apl_to_buf_INIT_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_INIT_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), + -- Status and control port + STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32), + STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) + ); + end generate; + + gentrgapi : if i = c_TRG_LVL1_CHANNEL generate + buf_APL_READ_OUT(i) <= '0'; + buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_APL_DATAREADY_OUT(i) <= '0'; + buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0'); + buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0'); + buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1'); + buf_APL_RUN_OUT(i) <= '0'; + buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0'); + buf_APL_READ_IN(i) <= '0'; + buf_APL_SHORT_TRANSFER_IN(i) <= '0'; + buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0'); + buf_APL_DATAREADY_IN(i) <= '0'; + buf_APL_SEND_IN(i) <= '0'; + buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + + apl_to_buf_INIT_DATAREADY(i) <= '0'; + apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16) <= (others => '0'); + apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + apl_to_buf_INIT_READ(i) <= '0'; + + buf_to_apl_REPLY_READ(i) <= '1'; + buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_REPLY_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + + buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0'); + buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0'); + + + the_trigger_apl : trb_net16_trigger + generic map( + USE_TRG_PORT => c_YES, + SECURE_MODE => std_TERM_SECURE_MODE + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_IN => apl_to_buf_REPLY_READ(i), + INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_READ_OUT => buf_to_apl_INIT_READ(i), + TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT, + TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, + TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, + TRG_CODE_OUT => LVL1_TRG_CODE_OUT, + TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, + TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + TRG_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN + ); + end generate; + + gen_ipu_apl : if i = c_DATA_CHANNEL generate + the_ipudata_apl : trb_net16_ipudata + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i), + API_READ_IN => buf_APL_READ_OUT(i), + API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i), + API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4), + API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + API_SEND_OUT => buf_APL_SEND_IN(i), + API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3), + API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i), + API_READ_OUT => buf_APL_READ_IN(i), + API_RUN_IN => buf_APL_RUN_OUT(i), + API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), + API_LENGTH_OUT => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16), + --Information received with request + IPU_NUMBER_OUT => IPU_NUMBER_OUT, + IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, + --start strobe + IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, + --detector data, equipped with DHDR + IPU_DATA_IN => IPU_DATA_IN, + IPU_DATAREADY_IN => IPU_DATAREADY_IN, + --no more data, end transfer, send TRM + IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN, + --will be low every second cycle due to 32bit -> 16bit conversion + IPU_READ_OUT => IPU_READ_OUT, + IPU_LENGTH_IN => IPU_LENGTH_IN, + IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, + STAT_DEBUG => STAT_DEBUG_IPU + ); + end generate; + + gen_regio : if i = c_SLOW_CTRL_CHANNEL generate + buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1'); + + regIO : trb_net16_regIO + generic map( + NUM_STAT_REGS => REGIO_NUM_STAT_REGS, + NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, + --standard values for output registers + INIT_CTRL_REGS => REGIO_INIT_CTRL_REGS, + --set to 0 for unused ctrl registers to save resources + USED_CTRL_REGS => REGIO_USED_CTRL_REGS, + --set to 0 for each unused bit in a register + USED_CTRL_BITMASK => REGIO_USED_CTRL_BITMASK, + --no data / address out? + USE_DAT_PORT => REGIO_USE_DAT_PORT, + INIT_ADDRESS => REGIO_INIT_ADDRESS, + INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID, + COMPILE_TIME => REGIO_COMPILE_TIME, + COMPILE_VERSION => REGIO_COMPILE_VERSION, + HARDWARE_VERSION => REGIO_HARDWARE_VERSION + ) + port map( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- Port to API + API_DATA_OUT => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + API_DATAREADY_OUT => buf_APL_DATAREADY_IN(i), + API_READ_IN => buf_APL_READ_OUT(i), + API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i), + API_DTYPE_OUT => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4), + API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32), + API_SEND_OUT => buf_APL_SEND_IN(3), + API_DATA_IN => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + API_TYP_IN => buf_APL_TYP_OUT((i+1)*3-1 downto i*3), + API_DATAREADY_IN => buf_APL_DATAREADY_OUT(i), + API_READ_OUT => buf_APL_READ_IN(i), + API_RUN_IN => buf_APL_RUN_OUT(i), + API_SEQNR_IN => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8), + --Port to write Unique ID + IDRAM_DATA_IN => buf_IDRAM_DATA_IN, + IDRAM_DATA_OUT => buf_IDRAM_DATA_OUT, + IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN, + IDRAM_WR_IN => buf_IDRAM_WR_IN, + MY_ADDRESS_OUT => MY_ADDRESS, + --Common Register in / out + COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN, + COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, + --Custom Register in / out + REGISTERS_IN => REGIO_REGISTERS_IN, + REGISTERS_OUT => REGIO_REGISTERS_OUT, + --following ports only used when no internal register is accessed + DAT_ADDR_OUT => REGIO_ADDR_OUT, + DAT_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, + DAT_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, + DAT_DATA_OUT => REGIO_DATA_OUT, + DAT_DATA_IN => REGIO_DATA_IN, + DAT_DATAREADY_IN => REGIO_DATAREADY_IN, + DAT_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, + DAT_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, + DAT_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, + DAT_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, + EXT_REG_DATA_IN => REGIO_EXT_REG_DATA_IN, + EXT_REG_DATA_OUT => REGIO_EXT_REG_DATA_OUT, + EXT_REG_WRITE_IN => REGIO_EXT_REG_WRITE_IN, + EXT_REG_ADDR_IN => REGIO_EXT_REG_ADDR_IN, + STAT => REGIO_REGIO_STAT + ); + gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = 0 generate + buf_IDRAM_DATA_IN <= REGIO_IDRAM_DATA_IN; + buf_IDRAM_ADDR_IN <= REGIO_IDRAM_ADDR_IN; + buf_IDRAM_WR_IN <= REGIO_IDRAM_WR_IN; + REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT; + REGIO_ONEWIRE_INOUT <= '0'; + buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN; + end generate; + gen_1wire : if REGIO_USE_1WIRE_INTERFACE = 1 generate + buf_COMMON_STAT_REG_IN(19 downto 0) <= REGIO_COMMON_STAT_REG_IN(19 downto 0); + buf_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32) <= + REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 32); + + REGIO_IDRAM_DATA_OUT <= (others => '0'); + + onewire_interface : trb_net_onewire + generic map( + USE_TEMPERATURE_READOUT => c_YES, + CLK_PERIOD => 10 + ) + port map( + CLK => CLK, + RESET => RESET, + --connection to 1-wire interface + ONEWIRE => REGIO_ONEWIRE_INOUT, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => buf_IDRAM_DATA_IN, + ADDR_OUT => buf_IDRAM_ADDR_IN, + WRITE_OUT=> buf_IDRAM_WR_IN, + TEMP_OUT => buf_COMMON_STAT_REG_IN(31 downto 20), + STAT => STAT_ONEWIRE + ); + end generate; + end generate; + end generate; + gentermbuf: if USE_CHANNEL(i) = c_NO generate + buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_APL_READ_OUT(i) <= '0'; + buf_APL_DATAREADY_OUT(i) <= '0'; + buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0'); + buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0'); + buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1'); + buf_APL_RUN_OUT(i) <= '0'; + buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0'); + buf_APL_READ_IN(i) <= '0'; + buf_APL_SHORT_TRANSFER_IN(i) <= '0'; + buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0'); + buf_APL_DATAREADY_IN(i) <= '0'; + buf_APL_SEND_IN(i) <= '0'; + + apl_to_buf_INIT_READ(i) <= '0'; + apl_to_buf_INIT_DATAREADY(i) <= '0'; + apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_DATAREADY(i) <= '0'; + apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + apl_to_buf_REPLY_READ(i) <= '0'; + apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + + buf_to_apl_INIT_READ(i) <= '0'; + buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + buf_to_apl_INIT_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0'); + buf_to_apl_REPLY_DATAREADY(i) <= '0'; + buf_to_apl_REPLY_READ(i) <= '0'; + buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); + + buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0'); + buf_STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0'); + buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0'); + buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0'); + buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0'); + buf_STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0'); + + termbuf: trb_net16_term_buf + port map( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_IO_DATAREADY_IN(i), + MED_DATA_IN => MED_IO_DATA_IN, + MED_PACKET_NUM_IN => MED_IO_PACKET_NUM_IN, + MED_READ_OUT => MED_IO_READ_OUT(i), + + MED_INIT_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2), + MED_INIT_DATA_OUT => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH), + MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH), + MED_INIT_READ_IN => MED_IO_READ_IN(i*2), + MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1), + MED_REPLY_DATA_OUT => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH), + MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH), + MED_REPLY_READ_IN => MED_IO_READ_IN(i*2+1) + ); + end generate; + end generate; + + + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MED_DATAREADY_IN, + MED_DATA_IN => MED_DATA_IN, + MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, + MED_READ_OUT => MED_READ_OUT, + MED_DATAREADY_OUT => MED_DATAREADY_OUT, + MED_DATA_OUT => MED_DATA_OUT, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + MED_READ_IN => MED_READ_IN, + INT_DATAREADY_OUT => MED_IO_DATAREADY_IN, + INT_DATA_OUT => MED_IO_DATA_IN, + INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN, + INT_READ_IN => MED_IO_READ_OUT, + INT_DATAREADY_IN => MED_IO_DATAREADY_OUT, + INT_DATA_IN => MED_IO_DATA_OUT, + INT_PACKET_NUM_IN => MED_IO_PACKET_NUM_OUT, + INT_READ_OUT => MED_IO_READ_IN, + CTRL => CTRL_MPLEX + ); + +buf_CTRL_GEN <= IOBUF_CTRL_GEN; + +STAT_DEBUG_1 <= (others => '0'); +STAT_DEBUG_2 <= (others => '0'); + +end architecture; + diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index e6f65f1..a9ac779 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -68,7 +68,6 @@ entity trb_net16_iobuf is STAT_GEN : out std_logic_vector (31 downto 0); STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0); STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) ); diff --git a/trb_net16_ipudata.vhd b/trb_net16_ipudata.vhd index 685aa44..9a518f7 100644 --- a/trb_net16_ipudata.vhd +++ b/trb_net16_ipudata.vhd @@ -33,9 +33,9 @@ entity trb_net16_ipudata is API_LENGTH_OUT : out std_logic_vector (15 downto 0); --Information received with request - IPU_TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_TRG_RND_CODE_OUT : out std_logic_vector (7 downto 0); - --start strobe + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + --start strobe IPU_START_READOUT_OUT: out std_logic; --detector data, equipped with DHDR IPU_DATA_IN : in std_logic_vector (31 downto 0); @@ -46,8 +46,8 @@ entity trb_net16_ipudata is IPU_READ_OUT : out std_logic; IPU_LENGTH_IN : in std_logic_vector (15 downto 0); IPU_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - - + + STAT_DEBUG : out std_logic_vector(31 downto 0) ); end entity; @@ -60,39 +60,89 @@ architecture trb_net16_ipudata_arch of trb_net16_ipudata is signal buf_API_READ_OUT : std_logic; signal buf_API_DATAREADY_OUT : std_logic; signal buf_API_DATA_OUT : std_logic_vector (c_DATA_WIDTH-1 downto 0); - signal buf_API_PACKET_NUM_OUT : std_logic_vector (c_NUM_WIDTH-1 downto 0); - type state_t is (IDLE, ); - signal state : state_t; - signal buf_API_TRG_NUMBER_OUT : std_logic_vector (15 downto 0); - signal buf_API_TRG_RND_CODE_OUT : std_logic_vector (7 downto 0); + type state_t is (START, WAITING, READING); + signal state : state_t; + signal buf_NUMBER : std_logic_vector (15 downto 0); + signal buf_RND_CODE : std_logic_vector (7 downto 0); + signal buf_INFORMATION : std_logic_vector (7 downto 0); + signal buf_TYPE : std_logic_vector (3 downto 0); + signal buf_START_READOUT : std_logic; + signal buf_IPU_READ : std_logic; + signal buf_API_SEND_OUT : std_logic; + signal waiting_word : std_logic; + signal packet_number : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal reg_IPU_DATA : std_logic_vector (15 downto 0); + signal saved_IPU_READOUT_FINISHED_IN : std_logic; + begin + IPU_NUMBER_OUT <= buf_NUMBER; + IPU_START_READOUT_OUT <= buf_START_READOUT; + IPU_READ_OUT <= buf_IPU_READ; + IPU_INFORMATION_OUT <= buf_INFORMATION; PROC_STATE_MACHINE : process(CLK) begin if rising_edge(CLK) then if RESET = '1' then - state <= IDLE; - buf_API_READ_OUT <= '0'; + state <= START; + buf_API_READ_OUT <= '0'; + buf_START_READOUT <= '0'; + update_buffers <= '0'; else - case state is - when IDLE => - if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' then + buf_API_READ_OUT <= '1'; + case state is + when START => + buf_API_SEND_OUT <= '0'; + update_buffers <= '0'; + if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' and API_TYP_IN = TYPE_TRM then case API_PACKET_NUM_IN is - when c_F0 => - when c_F1 => - when c_F2 => - when c_F3 => - when others => null + when c_F0 => null; --crc field, ignore + when c_F1 => buf_RND_CODE <= API_DATA_IN(7 downto 0); + buf_INFORMATION <= API_DATA_IN(15 downto 8); + when c_F2 => buf_NUMBER <= API_DATA_IN; + when c_F3 => buf_TYPE <= API_DATA_IN(3 downto 0); + buf_START_READOUT <= '1'; + state <= WAITING; + when others => null; end case; end if; + when WAITING => + if IPU_DATAREADY_IN = '1' then + update_buffers <= '1'; + state <= READING; + end if; + when READING => + update_buffers <= '0'; + buf_API_SEND_OUT <= '1'; + buf_API_DATAREADY_OUT <= IPU_DATAREADY_IN or waiting_word; + if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then + waiting_word <= '0'; + end if; + if IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then + buf_API_DATA_OUT <= IPU_DATA_IN(31 downto 16); + waiting_word <= '1'; + else + buf_API_DATA_OUT <= reg_IPU_DATA; + end if; + if saved_IPU_READOUT_FINISHED_IN = '1' and waiting_word = '0' and IPU_DATAREADY_IN = '0' then + buf_API_SEND_OUT <= '0'; + buf_START_READOUT <= '0'; + state <= START; + end if; + if IPU_READOUT_FINISHED_IN = '1' then + update_buffers <= '1'; + end if; when others => - state <= IDLE; + state <= START; end case; end if; end if; end process; + buf_IPU_READ <= '1' when API_READ_IN = '1' and waiting_word = '0' and state = READING else '0'; + + PROC_buffer_inputs : process(CLK) begin if rising_edge(CLK) then @@ -103,16 +153,55 @@ begin buf_IPU_LENGTH_IN <= IPU_LENGTH_IN; buf_IPU_ERROR_PATTERN_IN <= IPU_ERROR_PATTERN_IN; end if; - end if; + end if; + end process; + + PROC_store_IPU_input : process(CLK) + begin + if rising_edge(CLK) then + if IPU_DATAREADY_IN = '1' and buf_IPU_READ = '1' then + reg_IPU_DATA <= IPU_DATA_IN(15 downto 0); + end if; + end if; end process; - + + PROC_get_end_of_data : process(CLK) + begin + if rising_edge(CLK) then + if buf_START_READOUT = '0' then + saved_IPU_READOUT_FINISHED_IN <= '0'; + elsif IPU_READOUT_FINISHED_IN = '1' then + saved_IPU_READOUT_FINISHED_IN <= '1'; + end if; + end if; + end process; + + PROC_packet_num : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + packet_number <= c_F0; + elsif API_READ_IN = '1' and buf_API_DATAREADY_OUT = '1' then + packet_number <= packet_number + 1; + if packet_number = c_F3 then + packet_number <= c_F0; + end if; + end if; + end if; + end process; + API_ERROR_PATTERN_OUT <= buf_IPU_ERROR_PATTERN_IN; API_LENGTH_OUT <= buf_IPU_LENGTH_IN; API_READ_OUT <= buf_API_READ_OUT; API_DATAREADY_OUT <= buf_API_DATAREADY_OUT; API_DATA_OUT <= buf_API_DATA_OUT; - API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT; + API_PACKET_NUM_OUT <= packet_number; + API_SEND_OUT <= buf_API_SEND_OUT; + API_SHORT_TRANSFER_OUT<= '0'; + API_DTYPE_OUT <= buf_TYPE; + + + STAT_DEBUG <= (others => '0'); - end architecture; \ No newline at end of file diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index cf6f8ca..8c4219d 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -14,13 +14,11 @@ entity trb_net16_regIO is NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers --standard values for output registers - INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '0'); + INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) := (others => '0'); --set to 0 for unused ctrl registers to save resources USED_CTRL_REGS : std_logic_vector(2**(3)-1 downto 0) := "00000001"; --set to 0 for each unused bit in a register - USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := - (others => '1'); + USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; diff --git a/trb_net16_trigger.vhd b/trb_net16_trigger.vhd index e1722b4..90db12b 100644 --- a/trb_net16_trigger.vhd +++ b/trb_net16_trigger.vhd @@ -38,7 +38,7 @@ entity trb_net16_trigger is TRG_TYPE_OUT : out std_logic_vector (3 downto 0); TRG_NUMBER_OUT : out std_logic_vector (15 downto 0); TRG_CODE_OUT : out std_logic_vector (7 downto 0); - TRG_INFORMATION_OUT : out std_logic_vector (15 downto 0); + TRG_INFORMATION_OUT : out std_logic_vector (7 downto 0); TRG_RECEIVED_OUT : out std_logic; TRG_RELEASE_IN : in std_logic; TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) @@ -50,7 +50,7 @@ architecture trb_net16_trigger_arch of trb_net16_trigger is signal next_TRG_TYPE_OUT, reg_TRG_TYPE_OUT: std_logic_vector(3 downto 0); signal next_TRG_NUMBER_OUT, reg_TRG_NUMBER_OUT: std_logic_vector(15 downto 0); signal next_TRG_CODE_OUT, reg_TRG_CODE_OUT: std_logic_vector(7 downto 0); - signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(15 downto 0); + signal next_TRG_INFORMATION_OUT, reg_TRG_INFORMATION_OUT: std_logic_vector(7 downto 0); signal next_TRG_RECEIVED_OUT, reg_TRG_RECEIVED_OUT: std_logic; signal buf_TRG_ERROR_PATTERN_IN: std_logic_vector(31 downto 0); @@ -98,13 +98,12 @@ begin next_TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT; if saved_packet_type = TYPE_TRM then if INT_PACKET_NUM_IN = c_F1 then - next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 0); + next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 8); + next_TRG_CODE_OUT <= INT_DATA_IN(7 downto 0); elsif INT_PACKET_NUM_IN = c_F2 then - next_TRG_NUMBER_OUT(15 downto 8) <= INT_DATA_IN(7 downto 0); - next_TRG_CODE_OUT <= INT_DATA_IN(15 downto 8); + next_TRG_NUMBER_OUT(15 downto 0) <= INT_DATA_IN(15 downto 0); elsif INT_PACKET_NUM_IN = c_F3 then next_TRG_TYPE_OUT <= INT_DATA_IN(3 downto 0); - next_TRG_NUMBER_OUT(7 downto 0) <= INT_DATA_IN(11 downto 4); next_TRG_RECEIVED_OUT <= '1'; end if; end if; diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 5e452fa..5651a8f 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -13,13 +13,13 @@ package trb_net_std is constant c_DATA_WIDTH : integer := 16; constant c_NUM_WIDTH : integer := 3; - constant c_MUX_WIDTH : integer := 1; --!!! + constant c_MUX_WIDTH : integer := 3; --!!! --assigning channel names constant c_TRG_LVL1_CHANNEL : integer := 0; - constant c_TRG_LVL2_CHANNEL : integer := 1; - constant c_DATA_CHANNEL : integer := 2; + constant c_DATA_CHANNEL : integer := 1; + constant c_UNUSED_CHANNEL : integer := 2; constant c_SLOW_CTRL_CHANNEL : integer := 3; --api_type generic -- 2.43.0