From 8022969dc00b3d90de7ab6f4e06ec87921edc0b2 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 11 May 2017 13:30:58 +0200 Subject: [PATCH] remove large fifo option for monitoring by default. Fix registers in trigger logic --- base/code/input_statistics.vhd | 42 ++++++++++----------- base/code/input_to_trigger_logic_record.vhd | 2 +- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd index 31b0054..c6eb8c7 100644 --- a/base/code/input_statistics.vhd +++ b/base/code/input_statistics.vhd @@ -268,27 +268,27 @@ gen_small_fifo : if LARGE_FIFO = 0 generate end generate; end generate; -gen_big_fifo : if LARGE_FIFO = 1 generate - gen_all_fifo : if SINGLE_FIFO_ONLY = c_NO generate - gen_fifos : for i in 0 to INPUTS-1 generate - THE_FIFO : entity work.fifo_18x8k_oreg - port map ( - Data => std_logic_vector(cnt(i)(17 downto 0)), - Clock => CLK, - WrEn => fifo_write, - RdEn => fifo_read(i), - Reset => trigger_fifo_real, - AmFullThresh => "1000000000000", - Q => fifo_dout(i), - WCNT => fifo_count(i), - Empty => fifo_empty(i), - Full => open, - AlmostFull => open - ); - end generate; - end generate; - -end generate; +-- gen_big_fifo : if LARGE_FIFO = 1 generate +-- gen_all_fifo : if SINGLE_FIFO_ONLY = c_NO generate +-- gen_fifos : for i in 0 to INPUTS-1 generate +-- THE_FIFO : entity work.fifo_18x8k_oreg +-- port map ( +-- Data => std_logic_vector(cnt(i)(17 downto 0)), +-- Clock => CLK, +-- WrEn => fifo_write, +-- RdEn => fifo_read(i), +-- Reset => trigger_fifo_real, +-- AmFullThresh => "1000000000000", +-- Q => fifo_dout(i), +-- WCNT => fifo_count(i), +-- Empty => fifo_empty(i), +-- Full => open, +-- AlmostFull => open +-- ); +-- end generate; +-- end generate; +-- +-- end generate; status_reg(10+LARGE_FIFO*3 downto 0) <= fifo_count(0); status_reg(15) <= fifo_write; diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd index 4398a95..584d91d 100644 --- a/base/code/input_to_trigger_logic_record.vhd +++ b/base/code/input_to_trigger_logic_record.vhd @@ -173,7 +173,7 @@ begin elsif BUS_RX.addr(6 downto 0) = "0110011" then BUS_TX.data <= multiplicity_enable; elsif BUS_RX.addr(6 downto 0) = "0110100" then - BUS_TX.data <= x"00" & set_output_coin & set_output_mult & set_output_coin; + BUS_TX.data <= x"00" & set_output_coin & set_output_mult & set_output_simplecoin; else BUS_TX.nack <= '1'; BUS_TX.ack <= '0'; -- 2.43.0