From 804ade9a813059ce9b01c1bb03433d3fb30d614a Mon Sep 17 00:00:00 2001 From: HeH Date: Tue, 20 Aug 2024 14:12:46 +0200 Subject: [PATCH] HeH: Trying to remove reference channel from TDC, only coarse time needed for dogma... --- releases/tdc_v2.3/Readout.vhd | 38 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/releases/tdc_v2.3/Readout.vhd b/releases/tdc_v2.3/Readout.vhd index e4a2064..52e1632 100644 --- a/releases/tdc_v2.3/Readout.vhd +++ b/releases/tdc_v2.3/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2024-06-19 +-- Last update: 2024-08-20 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -22,7 +22,7 @@ use work.tdc_components.all; entity Readout is generic ( - CHANNEL_NUMBER : integer range 2 to 65; + CHANNEL_NUMBER : integer range 1 to 32; STATUS_REG_NR : integer range 0 to 31); port ( RESET_100 : in std_logic; @@ -30,9 +30,9 @@ entity Readout is RESET_COUNTERS : in std_logic; CLK_100 : in std_logic; CLK_200 : in std_logic; - HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1); + HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- from the channels - CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER); + CH_DATA_IN : in std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); CH_DATA_VALID_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_ALMOST_FULL_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); CH_EMPTY_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 0); @@ -99,9 +99,9 @@ architecture behavioral of Readout is signal trg_win_end_100_3r : std_logic; signal trg_win_end_100_4r : std_logic; -- channel signals - signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); - signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); - signal ch_data_3r : std_logic_vector_array_36(0 to CHANNEL_NUMBER); + signal ch_data_r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_2r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); + signal ch_data_3r : std_logic_vector_array_36(0 to CHANNEL_NUMBER-1); signal ch_data_4r : std_logic_vector(31 downto 0); signal ch_hit_time : std_logic_vector(38 downto 0); signal ch_epoch_cntr : std_logic_vector(27 downto 0); @@ -132,8 +132,8 @@ architecture behavioral of Readout is signal missing_ref_time : std_logic; signal wrong_readout_fsm : std_logic; signal wrong_readout : std_logic; - signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_rd_fsm : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr_fsm : integer range 0 to CHANNEL_NUMBER-1 := 0; signal buf_delay_fsm : integer range 0 to 63 := 0; signal buf_delay : integer range 0 to 63 := 0; -- signal isLastTriggerNoTiming : std_logic := '0'; @@ -144,11 +144,11 @@ architecture behavioral of Readout is -- fifo number type Std_Logic_8_array is array (0 to 8) of std_logic_vector(3 downto 0); signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); - signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_r : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_2r : integer range 0 to CHANNEL_NUMBER := 0; - signal fifo_nr_wr_3r : integer range 0 to CHANNEL_NUMBER := 0; + signal fifo_nr_rd : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr_r : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr_2r : integer range 0 to CHANNEL_NUMBER-1 := 0; + signal fifo_nr_wr_3r : integer range 0 to CHANNEL_NUMBER-1 := 0; -- fifo read signal rd_en : std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- data mux @@ -198,11 +198,11 @@ architecture behavioral of Readout is signal wrong_readout_up : std_logic; signal finished : std_logic; -- control - signal sync_q : std_logic_vector((CHANNEL_NUMBER-2)*3+2 downto 0); + signal sync_q : std_logic_vector((CHANNEL_NUMBER-1)*3+2 downto 0); signal isNoHit : std_logic := '1'; signal isNoHit_r : std_logic := '1'; signal isCalTrig : std_logic := '0'; - signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 1); + signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0); -- debug signal header_error_bits : std_logic_vector(15 downto 0); signal trailer_error_bits : std_logic_vector(15 downto 0); @@ -683,11 +683,11 @@ begin -- behavioral -- Control bits ------------------------------------------------------------------------------- --purpose: Hit Signal Synchroniser - HitSignalSync : for i in 0 to CHANNEL_NUMBER-2 generate - sync_q(i*3) <= HIT_IN(i+1) when rising_edge(CLK_100); + HitSignalSync : for i in 0 to CHANNEL_NUMBER-1 generate + sync_q(i*3) <= HIT_IN(i) when rising_edge(CLK_100); --sync_q(i*3+1) <= sync_q(i*3); -- when rising_edge(CLK_100); --sync_q(i*3+2) <= sync_q(i*3+1); -- when rising_edge(CLK_100); - hit_in_i(i+1) <= HIT_IN(i+1); --sync_q(i*3+2); + hit_in_i(i) <= HIT_IN(i); --sync_q(i*3+2); end generate HitSignalSync; any_hit <= or_all(hit_in_i); -- 2.43.0