From 8071add11edfbf85add8131a67e874cf2f37448f Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 21 Apr 2010 16:47:24 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/fifo/fifo_var_oreg.vhd | 2 +- pinout/shower_fpga1.lpf | 17 ----------------- 2 files changed, 1 insertion(+), 18 deletions(-) diff --git a/lattice/ecp2m/fifo/fifo_var_oreg.vhd b/lattice/ecp2m/fifo/fifo_var_oreg.vhd index 0aaebcc..729946c 100644 --- a/lattice/ecp2m/fifo/fifo_var_oreg.vhd +++ b/lattice/ecp2m/fifo/fifo_var_oreg.vhd @@ -33,7 +33,7 @@ begin assert (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 15 and FIFO_WIDTH = 36) or (FIFO_DEPTH >= 8 and FIFO_DEPTH <= 11 and FIFO_WIDTH = 18) - report "Selected data buffer size not implemented" severity error; + report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error; gen_36_256 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 8 generate THE_FIFO : fifo_36x256_oreg diff --git a/pinout/shower_fpga1.lpf b/pinout/shower_fpga1.lpf index 93c76c8..d2ddcda 100644 --- a/pinout/shower_fpga1.lpf +++ b/pinout/shower_fpga1.lpf @@ -388,21 +388,4 @@ BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; - FREQUENCY PORT CLK_100_IN 100.000000 MHz ; - FREQUENCY PORT CLK_125_IN 125.000000 MHz ; - - FREQUENCY PORT "ADCCLK_OUT_1" 20.000000 MHz ; - FREQUENCY PORT "ADCCLK_OUT_2" 20.000000 MHz ; - FREQUENCY PORT "ADCCLK_OUT_3" 20.000000 MHz ; - FREQUENCY PORT "ADCCLK_OUT_4" 20.000000 MHz ; - FREQUENCY PORT "ADCCLK_OUT_5" 20.000000 MHz ; - FREQUENCY PORT "ADCCLK_OUT_6" 20.000000 MHz ; - - FREQUENCY PORT "DCO_IN_1" 100.000000 MHz ; - FREQUENCY PORT "DCO_IN_2" 100.000000 MHz ; - FREQUENCY PORT "DCO_IN_3" 100.000000 MHz ; - FREQUENCY PORT "DCO_IN_4" 100.000000 MHz ; - FREQUENCY PORT "DCO_IN_5" 100.000000 MHz ; - FREQUENCY PORT "DCO_IN_6" 100.000000 MHz ; - -- 2.43.0