From 8085044e1b274b53a4e3b4cb67aa59716866087f Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 22 Dec 2021 09:40:47 +0100 Subject: [PATCH] TRBnet reset works again with link re-establishment --- code/clock_reset_handler.vhd | 8 ++------ cts/trb3sc_cts.vhd | 22 +++++++++++++--------- hub/par.p2t | 2 +- hub/trb3sc_hub.vhd | 5 ++--- tdctemplate/trb3sc_tdctemplate.vhd | 5 ++--- 5 files changed, 20 insertions(+), 22 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 9681112..63c141f 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -19,7 +19,6 @@ entity clock_reset_handler is NET_CLK_HALF_IN : in std_logic; -- TO BE REMOVED GLOBAL_RESET_IN : in std_logic; -- from Link Layer RESET_FROM_NET_IN : in std_logic := '0'; -- stat_op(13) - SEND_RESET_IN : in std_logic := '0'; -- stat_op(15) BUS_RX : in CTRLBUS_RX; -- NOT USED BUS_TX : out CTRLBUS_TX; -- NOT USED @@ -56,7 +55,6 @@ signal timer : unsigned(27 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i : std_logic; signal debug_reset_handler : std_logic_vector(15 downto 0); -signal send_reset_detect, trb_reset_i : std_logic := '0'; attribute syn_keep of clear_n_i : signal is true; attribute syn_preserve of clear_n_i : signal is true; @@ -223,7 +221,7 @@ clear_n_i <= timer(27-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN); --------------------------------------------------------------------------- THE_RESET_HANDLER : trb_net_reset_handler generic map( - RESET_DELAY => x"FEEE" + RESET_DELAY => x"FEEE" -- not used anymore ) port map( CLEAR_IN => GLOBAL_RESET_IN, -- reset input (high active, async) @@ -232,15 +230,13 @@ THE_RESET_HANDLER : trb_net_reset_handler SYSCLK_IN => clk_selected_half, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_int_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => trb_reset_i, -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => RESET_FROM_NET_IN, -- reset via GbE signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) DEBUG_OUT => debug_reset_handler ); RESET_OUT <= reset_i; -send_reset_detect <= SEND_RESET_IN when rising_edge(INT_CLK_IN); -trb_reset_i <= RESET_FROM_NET_IN or (send_reset_detect and not SEND_RESET_IN); --------------------------------------------------------------------------- -- Slow clock for DCDC converters diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index a0b12b0..61a1b43 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -201,13 +201,16 @@ architecture trb3sc_arch of trb3sc_cts is signal cts_ipu_status_bits : std_logic_vector(31 downto 0); signal cts_ipu_busy : std_logic; - signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + signal reset_via_gbe_long : std_logic; + signal reset_via_gbe_timer : std_logic; + signal last_reset_via_gbe_long : std_logic; + signal make_reset_by_gbe : std_logic; - signal hit_in_i : std_logic_vector(64 downto 1); - signal mbs_async_out : std_logic; + signal hit_in_i : std_logic_vector(64 downto 1); + signal mbs_async_out : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; attribute syn_keep of bussci1_rx : signal is true; attribute syn_preserve of bussci1_rx : signal is true; attribute syn_keep of bustools_rx : signal is true; @@ -264,8 +267,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => '0', NET_CLK_HALF_IN => '0', - GLOBAL_RESET_IN => '0', -- BUG - RESET_FROM_NET_IN => make_reset, + GLOBAL_RESET_IN => '0', + RESET_FROM_NET_IN => make_reset_by_gbe, BUS_RX => bustc_rx, BUS_TX => bustc_tx, RESET_OUT => reset_i, @@ -293,9 +296,10 @@ THE_CLOCK_RESET : entity work.clock_reset_handler reset_via_gbe_long <= reset_via_gbe_timer; end if; last_reset_via_gbe_long <= reset_via_gbe_long; - make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; -- pulse, 1 clock cycle + make_reset_by_gbe <= last_reset_via_gbe_long and not reset_via_gbe_long; -- pulse, 1 clock cycle end process; - +-- REMARK: this should be transfered to GbE part. + pll_calibration : entity work.pll_in125_out33 port map ( CLK => CLK_SUPPL_PCLK, diff --git a/hub/par.p2t b/hub/par.p2t index 425592e..80b7368 100644 --- a/hub/par.p2t +++ b/hub/par.p2t @@ -1,7 +1,7 @@ -w -l 5 -s 12 --t 31 # seed setting here! # 32 +-t 32 # seed setting here! # 32 -c 1 -e 2 -i 15 diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index 27b1e45..d1077ae 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -189,9 +189,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full, NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half, - GLOBAL_RESET_IN => global_reset_i, -- BUG - RESET_FROM_NET_IN => med2int(INTERFACE_NUM-1).stat_op(13), - SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15), + GLOBAL_RESET_IN => global_reset_i, + RESET_FROM_NET_IN => '0', BUS_RX => bustc_rx, BUS_TX => bustc_tx, RESET_OUT => reset_i, diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index f5ed104..a81985d 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -170,9 +170,8 @@ begin EXT_CLK_IN => CLK_EXT_PLL_LEFT, NET_CLK_FULL_IN => med2int(0).clk_full, NET_CLK_HALF_IN => med2int(0).clk_half, - GLOBAL_RESET_IN => global_reset_i, -- BUG - RESET_FROM_NET_IN => med2int(0).stat_op(13), - SEND_RESET_IN => med2int(0).stat_op(15), + GLOBAL_RESET_IN => global_reset_i, + RESET_FROM_NET_IN => '0', BUS_RX => bustc_rx, BUS_TX => bustc_tx, RESET_OUT => reset_i, -- 2.43.0