From 8093c542d46e833eae87a824461410af30557628 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 20 Jul 2023 16:28:30 +0200 Subject: [PATCH] revert change of LOL settings in ECP5 serdes --- media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd | 2 +- media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd | 2 +- media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd | 2 +- media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd | 2 +- media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd index c68011e..c8b0baa 100644 --- a/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd +++ b/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd @@ -159,7 +159,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd index 0651ba5..d769bb8 100644 --- a/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd +++ b/media_interfaces/ecp5/dual_serdes/serdes0/serdes0.vhd @@ -159,7 +159,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd index f3193c3..39c1ff9 100644 --- a/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd +++ b/media_interfaces/ecp5/dual_serdes/serdes1/serdes1.vhd @@ -127,7 +127,7 @@ begin rx_cdr_lol_s <= rx_cdr_lol_s_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd index d62e2ee..f58d702 100644 --- a/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd +++ b/media_interfaces/ecp5/dual_serdes_1/serdes0/serdes0.vhd @@ -159,7 +159,7 @@ begin pll_lol <= pll_lol_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0", CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0", diff --git a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd index 30e182a..f8a36f2 100644 --- a/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd +++ b/media_interfaces/ecp5/dual_serdes_1/serdes1/serdes1.vhd @@ -127,7 +127,7 @@ begin rx_cdr_lol_s <= rx_cdr_lol_s_c; DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", + D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", -- 2.43.0