From 809c30533951f27bb1c6b57ed1b1eb0bb2b619ad Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 13 Jul 2020 16:39:09 +0200 Subject: [PATCH] data sending from combiner; NOT as GbeEvents. Now own packaging --- combiner_cts/combiner.prj | 6 +- combiner_cts/cri/cri_data_sender3.vhd | 712 +++++++++++++ combiner_cts/cri/trb_net16_cri_interface3.vhd | 991 ++++++++++++++++++ 3 files changed, 1707 insertions(+), 2 deletions(-) create mode 100644 combiner_cts/cri/cri_data_sender3.vhd create mode 100644 combiner_cts/cri/trb_net16_cri_interface3.vhd diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj index 03d2254..7ddbf09 100644 --- a/combiner_cts/combiner.prj +++ b/combiner_cts/combiner.prj @@ -216,13 +216,15 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_rec add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" #CRI -add_file -vhdl -lib work "./cri/trb_net16_cri_interface.vhd" +add_file -vhdl -lib work "./cri/trb_net16_cri_interface3.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "./cri/trb_net16_cri_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" -add_file -vhdl -lib work "./cri/cri_data_sender.vhd" +add_file -vhdl -lib work "./cri/cri_data_sender3.vhd" +add_file -vhdl -lib work "./cri/trb_net16_cri_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" #TDC Calibration #add_file -vhdl -lib work "./code/Calibration.vhd" diff --git a/combiner_cts/cri/cri_data_sender3.vhd b/combiner_cts/cri/cri_data_sender3.vhd new file mode 100644 index 0000000..ba3fefa --- /dev/null +++ b/combiner_cts/cri/cri_data_sender3.vhd @@ -0,0 +1,712 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +--USE IEEE.std_logic_ARITH.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +USE IEEE.numeric_std.ALL; +library work; +use work.trb_net_std.all; + + +entity cri_data_sender is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + ENABLE_TRANSPORT : in std_logic; + + -- Port to API + API_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_DATAREADY_OUT : out std_logic; + API_READ_IN : in std_logic; + API_SHORT_TRANSFER_OUT : out std_logic; + API_DTYPE_OUT : out std_logic_vector (3 downto 0); + API_ERROR_PATTERN_OUT : out std_logic_vector (31 downto 0); + API_SEND_OUT : out std_logic; + -- Receiver port + API_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + API_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); + API_TYP_IN : in std_logic_vector (2 downto 0); + API_DATAREADY_IN : in std_logic; + API_READ_OUT : out std_logic; + -- APL Control port + API_RUN_IN : in std_logic; + API_SEQNR_IN : in std_logic_vector (7 downto 0); + API_LENGTH_OUT : out std_logic_vector (15 downto 0); + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + + --data from event packer + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); --not used; got it from FEE + CTS_CODE_IN : in std_logic_vector( 7 downto 0); --not used; got it from FEE + CTS_INFORMATION_IN : in std_logic_vector( 7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector( 3 downto 0); --not used; got it from FEE + CTS_START_READOUT_IN : in std_logic; + CTS_READ_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); -- 0 terminated + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); -- 0 terminated + -- Data from Frontends + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_BUSY_IN : in std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + + DEBUG_OUT : out std_logic_vector(191 downto 0) + ); +end entity; + +architecture cri_data_sender_arch of cri_data_sender is + + type save_states_t is (IDLE, WAIT_FOR_DATA, SAVE_DATA, ADD_SUBSUB1, ADD_SUBSUB2, ADD_SUBSUB3, ADD_SUBSUB4, TERMINATE, SEND_TERM_PULSE, CLOSE, CLEANUP); + signal save_current_state, save_next_state : save_states_t; + + type data_sender_states_t is (IDLE, PREPARE_SEND, LOAD, FINISH_SEND, STOP_SEND, READ_ANSWER, FINISH_ACTION, CLEANUP); + signal send_state_current, send_state_next : data_sender_states_t; + + constant loc_buff_depth : integer := 4; + type loc_buffer_t is array (0 to loc_buff_depth) of std_logic_vector(16 downto 0); + signal local_buffer : loc_buffer_t := (others => (others=> '0')); + + signal rec_state, send_state_bits : std_logic_vector(3 downto 0); + + signal df_wr_en_qq, df_wr_en_q, df_wr_en,df_rd_en : std_logic; + signal df_data : std_logic_vector(15 downto 0); + signal df_eos_q, df_eos : std_logic; + signal fifo_almFull : std_logic; + signal df_afull, df_full_real : std_logic; + signal df_empty : std_logic; + signal df_wcnt : std_logic_vector(11 downto 0); + signal df_rdy_q, df_rdy : std_logic; + signal data_out, df_q : std_logic_vector(15 downto 0); + signal load_eod : std_logic; + signal fifo_rd_en : std_logic; + signal eod_out : std_logic; + signal local_buf_empty : std_logic; + + -- saving + signal cts_rnd, cts_trg : std_logic_vector(15 downto 0); + signal length_cnt : std_logic_vector(15 downto 0) := x"0000"; + + -- sending + signal cri_apl_reading : std_logic; + signal cri_apl_data : std_logic_vector(15 downto 0); + signal cri_apl_packet_num : std_logic_vector(2 downto 0); + signal cri_apl_dataready : std_logic; + signal cri_apl_read : std_logic; + signal data_trans_finished : std_logic; + signal load_data : std_logic; + signal tmp_data : std_logic_vector( 7 downto 0); + signal cri_apl_send : std_logic; + signal received_answer : std_logic; + signal cri_apl_run : std_logic; + + signal cri_event_cnt : std_logic_vector(15 downto 0) := x"0000"; + + signal cri_apl_answer_data : std_logic_vector(15 downto 0); + signal cri_apl_answer_packet_num : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal cri_apl_answer_typ : std_logic_vector( 2 downto 0); + signal cri_apl_answer_dataready : std_logic; + signal loaded_bytes : std_logic_vector(15 downto 0) := x"0000"; + signal cri_packet_num_cnt : std_logic_vector( 1 downto 0) := "00"; + + signal data_save_cnt : std_logic_vector(15 downto 0); + signal fee_read_loc : std_logic; + + signal data_open : std_logic; -- for modelsim + + type loc_buffer_dbg_t is array (0 to 7) of std_logic_vector(15 downto 0); + signal local_buffer_dbg : loc_buffer_dbg_t := (others => (others=> '0')); +begin + + CTS_LENGTH_OUT <= (others => '0'); + CTS_ERROR_PATTERN_OUT <= (others => '0'); + + SAVE_MACHINE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + save_current_state <= IDLE; + elsif rising_edge(CLK) then + save_current_state <= save_next_state; + end if; + end process; + + SAVE_MACHINE : process(save_current_state, CTS_START_READOUT_IN, FEE_BUSY_IN, CTS_READ_IN) + begin + rec_state <= x"0"; + case (save_current_state) is + when IDLE => + rec_state <= x"1"; + if (CTS_START_READOUT_IN = '1') then + save_next_state <= WAIT_FOR_DATA; + else + save_next_state <= IDLE; + end if; + + when WAIT_FOR_DATA => + rec_state <= x"2"; + if (FEE_BUSY_IN = '1') then + save_next_state <= SAVE_DATA; + else + save_next_state <= WAIT_FOR_DATA; + end if; + + when SAVE_DATA => + rec_state <= x"3"; + if (FEE_BUSY_IN = '0') then + save_next_state <= TERMINATE; + else + save_next_state <= SAVE_DATA; + end if; + + when TERMINATE => + rec_state <= x"5"; + if (CTS_READ_IN = '1') then + save_next_state <= SEND_TERM_PULSE; --CLOSE; + else + save_next_state <= TERMINATE; + end if; + + when SEND_TERM_PULSE => + rec_state <= x"6"; + save_next_state <= CLOSE; + + when CLOSE => + rec_state <= x"6"; + save_next_state <= ADD_SUBSUB1; + + when ADD_SUBSUB1 => + rec_state <= x"7"; + save_next_state <= ADD_SUBSUB2; + + when ADD_SUBSUB2 => + rec_state <= x"8"; + save_next_state <= ADD_SUBSUB3; + + when ADD_SUBSUB3 => + rec_state <= x"9"; + save_next_state <= ADD_SUBSUB4; + + when ADD_SUBSUB4 => + rec_state <= x"a"; + save_next_state <= CLEANUP; + + when CLEANUP => + rec_state <= x"c"; + if (CTS_START_READOUT_IN = '0') then + save_next_state <= IDLE; + else + save_next_state <= CLEANUP; + end if; + + when others => save_next_state <= IDLE; + + end case; + end process; + + CTS_DATAREADY_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = SAVE_DATA and FEE_BUSY_IN = '0') then + CTS_DATAREADY_OUT <= '1'; + elsif (save_current_state = TERMINATE) then + CTS_DATAREADY_OUT <= '1'; + else + CTS_DATAREADY_OUT <= '0'; + end if; + end if; + end process; + + CTS_READOUT_FINISHED_PROC : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = CLEANUP) then + CTS_READOUT_FINISHED_OUT <= '1'; + else + CTS_READOUT_FINISHED_OUT <= '0'; + end if; + end if; + end process; + + CTS_DATA_PROC : process(CLK) + begin + if rising_edge(CLK) then + CTS_DATA_OUT <= "0001" & cts_rnd(11 downto 0) & cts_trg; + end if; + end process; + + CTS_RND_TRG_PROC : process(CLK) + begin + if rising_edge(CLK) then + if ((save_current_state = SAVE_DATA) and + (FEE_DATAREADY_IN = '1') and + (fee_read_loc = '1')) + then + if (length_cnt = x"0000") then + cts_rnd <= FEE_DATA_IN; + end if; + + if (length_cnt = x"0001") then + cts_trg <= FEE_DATA_IN; + end if; + else + cts_rnd <= cts_rnd; + cts_trg <= cts_trg; + end if; + end if; + end process; + + CTS_WORD_CNT : process(CLK) + begin + if rising_edge(CLK) then + if (save_current_state = IDLE) then + length_cnt <= (others => '0'); + elsif ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then + length_cnt <= length_cnt + 1; + else + length_cnt <= length_cnt; + end if; + end if; + end process; + + + DATA_WRITE_PROC : process begin + wait until rising_edge(CLK); + if ((save_current_state = SAVE_DATA) and (FEE_DATAREADY_IN = '1') and (fee_read_loc = '1')) then + df_wr_en <= '1'; + elsif (save_current_state = ADD_SUBSUB1 or save_current_state = ADD_SUBSUB2 or save_current_state = ADD_SUBSUB3 or save_current_state = ADD_SUBSUB4) then + df_wr_en <= '1'; + else + df_wr_en <= '0'; + end if; + end process; + +-- FEE_READ_PROC : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if (save_current_state = SAVE_DATA) then +-- if (df_afull = '0') then +-- local_read <= '1'; +-- else +-- local_read <= '0'; +-- end if; +-- else +-- local_read <= '1'; +-- end if; +-- end if; +-- end process FEE_READ_PROC; + + SF_DATA_EOD_PROC : process begin + wait until rising_edge(CLK); + case (save_current_state) is + when SAVE_DATA => + df_data <= FEE_DATA_IN; + df_eos_q <= '0'; + + when ADD_SUBSUB1 => + df_data <= x"0001"; + df_eos_q <= '0'; + + when ADD_SUBSUB2 => + df_data <= x"5555"; + df_eos_q <= '0'; + + when ADD_SUBSUB3 => + df_data <= FEE_STATUS_BITS_IN(31 downto 16); + df_eos_q <= '0'; + + when ADD_SUBSUB4 => + df_data <= FEE_STATUS_BITS_IN(15 downto 0); + df_eos_q <= '1'; + + when others => + df_data <= df_data; + df_eos_q <= '0'; + + end case; + end process; + + FEE_READ_OUT <= fee_read_loc; + fee_read_loc <= not df_afull;--local_read; + +-- DATA_FIFO : entity work.fifo_64kx9_af_cnt +-- port map( +-- Data(15 downto 0) => df_data, +-- Data(16) => df_eos_q, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => df_wr_en, +-- RdEn => df_rd_en, +-- Reset => RESET, +-- RPReset => RESET, +-- Q(15 downto 0) => df_q, +-- Q(16) => load_eod, +-- Empty => df_empty, +-- Full => df_full_real, +-- AlmostFull => df_afull, +-- WCNT => df_wcnt +-- ); + + DATA_FIFO : entity work.fifo_18x2k_oreg + port map ( + Data(15 downto 0) => df_data, + Data(16) => df_eos_q, + Data(17) => '0', + Clock => CLK, + WrEn => df_wr_en, + RdEn => df_rd_en, + Reset => RESET, + AmFullThresh => b"11111111000", + Q(15 downto 0) => data_out,--df_q, --df_q if fifo is without outreg + Q(16) => eod_out,--load_eod, --load_eod if fifo is without outreg + Q(17) => data_open, + WCNT => df_wcnt, + Empty => df_empty, + Full => df_full_real, + AlmostFull => df_afull + ); + + --READ from FIFO to TrbNet API + + df_rd_en <= load_data and not df_empty and local_buf_empty; + + load_data <= '1' when send_state_current = LOAD else '0'; + + DATA_FIFO_CONTRL_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + df_rdy_q <= '0'; + df_rdy <= '0'; + --data_out <= x"0000"; + --eod_out <= '0'; + else + df_rdy_q <= df_rd_en; + df_rdy <= df_rdy_q; -- delay from readout reg of fifo + + --data_out <= df_q; -- readout reg for fifo + --eod_out <= load_eod; + end if; + end process; + + + LOCAL_BUFF_PROC : process + variable buff_cnt : integer range 0 to loc_buff_depth := 0; + begin + wait until rising_edge(CLK); + if RESET = '1' then + buff_cnt := 0; + else + + -- Data from sub is loaded; first data from following sub is (partialy) loaded + if (send_state_current /= LOAD) and (df_rdy = '1') then + local_buffer(buff_cnt) <= eod_out & data_out; + buff_cnt := buff_cnt + 1; + end if; + + -- first word in buffer is always in 0; is loaded in sending process. + if (send_state_current = LOAD) and (local_buf_empty = '0') then + local_buffer(0) <= local_buffer(1); + local_buffer(1) <= local_buffer(2); + local_buffer(2) <= local_buffer(3); + local_buffer(3) <= local_buffer(4); + local_buffer(4) <= (others => '0'); + buff_cnt := buff_cnt - 1; + end if; + + -- has to be atthis position, to garantee that buff_cnt won't be negative + if buff_cnt = 0 then + local_buf_empty <= '1'; + else + local_buf_empty <= '0'; + end if; + + end if; + end process; + + + SEND_STATE_PROC : process(RESET, CLK) + begin + if RESET = '1' then + send_state_current <= IDLE; + else + if rising_edge(CLK) then + send_state_current <= send_state_next; + end if; + end if; + end process; + + + SEND_STATE_MACHINE : process(send_state_current, cri_apl_reading, ENABLE_TRANSPORT, eod_out, df_rdy,local_buf_empty,local_buffer(0)(8),data_trans_finished,received_answer,cri_apl_run) + begin + send_state_bits <= x"0"; + case send_state_current is + when IDLE => + send_state_bits <= x"1"; + send_state_next <= PREPARE_SEND; + + when PREPARE_SEND => + send_state_bits <= x"2"; + if cri_apl_reading = '1' and ENABLE_TRANSPORT = '1' then + send_state_next <= LOAD; + else + send_state_next <= PREPARE_SEND; + end if; + + when LOAD => + send_state_bits <= x"3"; + if (eod_out = '1' and df_rdy = '1') then--or ( local_buf_empty = '0' and local_buffer(0)(8) = '1' )) then --last word of subevent is currently in data_out + send_state_next <= FINISH_SEND; + else + send_state_next <= LOAD; + end if; + + when FINISH_SEND => + send_state_bits <= x"4"; + if data_trans_finished = '1' then + send_state_next <= STOP_SEND; + else + send_state_next <= FINISH_SEND; + end if; + + when STOP_SEND => + send_state_bits <= x"5"; + send_state_next <= READ_ANSWER; + + when READ_ANSWER => + send_state_bits <= x"6"; + if received_answer = '1' then + send_state_next <= FINISH_ACTION; + else + send_state_next <= READ_ANSWER; + end if; + + when FINISH_ACTION => + send_state_bits <= x"7"; + if cri_apl_run = '0' then + send_state_next <= PREPARE_SEND; + else + send_state_next <= FINISH_ACTION; + end if; + + when others => + send_state_bits <= x"8"; + send_state_next <= IDLE; + + end case; + end process; + + + + DATA_TRANSPORT_PROC : process + variable loc_tmp_data : std_logic_vector(15 downto 0); + variable loc_data_rdy : std_logic; + --variable pos_cnt : std_logic := '0'; + begin + wait until rising_edge(CLK); + + cri_apl_dataready <= '0'; + data_trans_finished <= '0'; + + if RESET = '1' then + loc_tmp_data := x"0000"; + loc_data_rdy := '0'; + --tmp_data <= x"00"; + --pos_cnt := '0'; + loaded_bytes <= (others => '0'); + else + --prepare data + loc_data_rdy := '0'; + if (send_state_current = LOAD) then -- load state data + -- get data from correct source + if (local_buf_empty = '0') then + loc_tmp_data := local_buffer(0)(15 downto 0); + loc_data_rdy := '1'; + else + loc_tmp_data := data_out; + loc_data_rdy := df_rdy; + end if; + end if; + + if (send_state_current = LOAD) then -- or (send_state_current = FINISH_SEND)) then + -- put data in 16 bits + if loc_data_rdy = '1' then -- only process if data is valid/rdy +-- if (pos_cnt = '1') then + cri_apl_dataready <= '1'; + cri_packet_num_cnt <= cri_packet_num_cnt + 1; + loaded_bytes <= loaded_bytes + 1; +-- pos_cnt := '0'; +-- else +-- tmp_data <= loc_tmp_data; +-- pos_cnt := '1'; +-- end if; + cri_apl_data <= loc_tmp_data;-- & tmp_data; --maybe wrong order! + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + end if; -- end data rdy + end if;-- load state + + + -- finish the send process: + -- packet if last word in LOAD was not send, send it now. + if (send_state_current = FINISH_SEND) then + -- one word was loaded, but never send out! + --if (pos_cnt = '1') then + -- cri_apl_dataready <= '1'; + -- cri_packet_num_cnt <= cri_packet_num_cnt + 1; + -- loaded_bytes <= loaded_bytes + 1; + -- cri_apl_data <= loc_tmp_data & x"00"; --maybe wrong order! + -- cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + --else + if (cri_packet_num_cnt = "00") then + data_trans_finished <= '1'; + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + else + cri_packet_num_cnt <= cri_packet_num_cnt + 1; + cri_apl_packet_num <= '0' & std_logic_vector(cri_packet_num_cnt); + cri_apl_dataready <= '1'; + cri_apl_data <= x"BBBB"; + end if; + --end if; + --pos_cnt := '0'; + end if; -- FINISH_SEND + + -- to be sure that cntr is null in next data sending process. + if (data_trans_finished = '1') then + cri_packet_num_cnt <= "00"; + loaded_bytes <= (others => '0'); + end if; + + if ((loaded_bytes > x"0000") and (loaded_bytes < x"0009") and (cri_apl_dataready = '1')) then + local_buffer_dbg(to_integer( unsigned( loaded_bytes )-1) ) <= cri_apl_data; + end if; + + end if; + end process; + + + + -- handle the data sending flag to the trbnet APL + DATA_SEND_OUT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + cri_apl_send <= '0'; + else + if ((send_state_current = PREPARE_SEND) or + (send_state_current = LOAD) or + (send_state_current = FINISH_SEND) or + (send_state_current = STOP_SEND)) + then + cri_apl_send <= '1'; + else + cri_apl_send <= '0'; + end if; + end if; + end process; + + + + -- handle the read flag to the trbnet APL + DATA_READ_OUT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + cri_apl_read <= '0'; + else + --if ((send_state_current /= IDLE) then + if (( send_state_current = READ_ANSWER ) or + ( send_state_current = STOP_SEND )) + then + cri_apl_read <= '1'; + else + cri_apl_read <= '0'; + end if; + end if; + end process; + + + + -- handle the answer from CRI over trbnet + EVENT_CNT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + received_answer <= '0'; + cri_event_cnt <= (others => '0'); + else + received_answer <= '0'; + if ((cri_apl_answer_dataready = '1') and (cri_apl_answer_typ = TYPE_TRM) and (cri_apl_answer_packet_num = c_F3)) then + --cri_data_send_cnt <= 0; + cri_event_cnt <= cri_event_cnt + 1; + received_answer <= '1'; + end if; + end if; + end process; + + +-- DEBUG_OUT + DATA_SAVE_CNT_PROC : process begin + wait until rising_edge(CLK); + if RESET = '1' then + data_save_cnt <= (others => '0'); + else + if ((save_current_state = CLEANUP) and (CTS_START_READOUT_IN = '0')) then + data_save_cnt <= data_save_cnt + 1; + end if; + end if; + end process; + + + -- Data to CRI board + API_DATA_OUT <= cri_apl_data; + API_PACKET_NUM_OUT <= cri_apl_packet_num; + API_DATAREADY_OUT <= cri_apl_dataready; + cri_apl_reading <= API_READ_IN; + + API_SHORT_TRANSFER_OUT <= '0'; + API_DTYPE_OUT <= (others => '0'); + API_ERROR_PATTERN_OUT <= (others => '0'); + API_SEND_OUT <= cri_apl_send; + + cri_apl_answer_data <= API_DATA_IN; + cri_apl_answer_packet_num <= API_PACKET_NUM_IN; + cri_apl_answer_typ <= API_TYP_IN; + cri_apl_answer_dataready <= API_DATAREADY_IN; + + API_READ_OUT <= cri_apl_read; + -- APL Control port + cri_apl_run <= API_RUN_IN; + API_LENGTH_OUT <= (others => '0'); + + DEBUG_OUT(3 downto 0) <= rec_state; + DEBUG_OUT(7 downto 4) <= send_state_bits; + DEBUG_OUT( 8) <= df_empty; + DEBUG_OUT( 9) <= df_full_real; + DEBUG_OUT(10) <= df_afull; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(14 downto 12) <= cri_apl_packet_num; + DEBUG_OUT(15) <= '0'; + DEBUG_OUT(31 downto 16) <= cri_event_cnt; + + DEBUG_OUT( 47 downto 32) <= local_buffer_dbg(0); + DEBUG_OUT( 63 downto 48) <= local_buffer_dbg(1); + DEBUG_OUT( 79 downto 64) <= local_buffer_dbg(2); + DEBUG_OUT( 95 downto 80) <= local_buffer_dbg(3); + DEBUG_OUT(111 downto 96) <= local_buffer_dbg(4); + DEBUG_OUT(127 downto 112) <= local_buffer_dbg(5); + DEBUG_OUT(143 downto 128) <= local_buffer_dbg(6); + DEBUG_OUT(159 downto 144) <= local_buffer_dbg(7); + + DEBUG_OUT(175 downto 160) <= data_save_cnt; + DEBUG_OUT(176) <= local_buf_empty; + DEBUG_OUT(177) <= local_buffer(0)(8); + DEBUG_OUT(178) <= df_rdy; + DEBUG_OUT(179) <= eod_out; + DEBUG_OUT(180) <= data_trans_finished; + DEBUG_OUT(181) <= cri_apl_run; + DEBUG_OUT(182) <= cri_apl_dataready; + DEBUG_OUT(183) <= cri_apl_send; + DEBUG_OUT(184) <= cri_apl_read; + DEBUG_OUT(191 downto 185) <= cri_apl_data( 6 downto 0); + +end architecture; diff --git a/combiner_cts/cri/trb_net16_cri_interface3.vhd b/combiner_cts/cri/trb_net16_cri_interface3.vhd new file mode 100644 index 0000000..7f43572 --- /dev/null +++ b/combiner_cts/cri/trb_net16_cri_interface3.vhd @@ -0,0 +1,991 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.trb_net_gbe_components.all; +use work.trb_net_gbe_protocols.all; +use work.med_sync_define.all; + +entity trb_net16_cri_interface is + generic( + INCLUDE_READOUT : integer range 0 to 1 := 1; + INCLUDE_SLOWCTRL : integer range 0 to 1 := 1; + READOUT_BUFFER_SIZE : integer range 1 to 4 := 1 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Media Interface + MEDIA_MED2INT : in med2int_array_t(0 to 0); + MEDIA_INT2MED : out int2med_array_t(0 to 0); + + MY_ADDRESS_IN : in std_logic_vector(15 downto 0); + + --Event information coming from CTS for CRI + CTS_NUMBER_IN : in std_logic_vector (15 downto 0); + CTS_CODE_IN : in std_logic_vector (7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); + CTS_START_READOUT_IN : in std_logic; + + --Information sent to CTS + CTS_READOUT_FINISHED_OUT : out std_logic; --no more data, end transfer, send TRM + CTS_STATUS_BITS_OUT : out std_logic_vector (31 downto 0); + + --Data from Frontends + FEE_DATA_IN : in std_logic_vector (15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; --must be high when idle, otherwise you will never get a dataready + FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + FEE_BUSY_IN : in std_logic; + + --Gbe Sctrl Input + GSC_INIT_DATAREADY_OUT : out std_logic; + GSC_INIT_DATA_OUT : out std_logic_vector(15 downto 0); + GSC_INIT_PACKET_NUM_OUT : out std_logic_vector( 2 downto 0); + GSC_INIT_READ_IN : in std_logic; + GSC_REPLY_DATAREADY_IN : in std_logic; + GSC_REPLY_DATA_IN : in std_logic_vector(15 downto 0); + GSC_REPLY_PACKET_NUM_IN : in std_logic_vector( 2 downto 0); + GSC_REPLY_READ_OUT : out std_logic; + GSC_BUSY_IN : in std_logic; + + -- Registers config + BUS_REG_RX : in CTRLBUS_RX; + BUS_REG_TX : out CTRLBUS_TX; + + BUS_DBG_RX : in CTRLBUS_RX; + BUS_DBG_TX : out CTRLBUS_TX; + + TIMER_TICKS_IN : in std_logic_vector( 1 downto 0) + ); +end entity; + +architecture arch of trb_net16_cri_interface is + + signal reset_i, reset_i_mux_io : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal io_dataready_out : std_logic_vector(7 downto 0); + signal io_data_out : std_logic_vector(127 downto 0); + signal io_packet_num_out : std_logic_vector(23 downto 0); + signal io_read_in : std_logic_vector(7 downto 0); + + signal io_dataready_in : std_logic_vector(3 downto 0); + signal io_read_out : std_logic_vector(3 downto 0); + signal io_data_in : std_logic_vector(4*16-1 downto 0); + signal io_packet_num_in : std_logic_vector(4*3-1 downto 0); + signal io_error_in : std_logic_vector(2 downto 0); + + signal cfg_gbe_enable : std_logic; + signal cfg_ipu_enable : std_logic; + signal cfg_mult_enable : std_logic; + signal cfg_subevent_id : std_logic_vector(31 downto 0); + signal cfg_subevent_dec : std_logic_vector(31 downto 0); + signal cfg_queue_dec : std_logic_vector(31 downto 0); + signal cfg_readout_ctr : std_logic_vector(23 downto 0); + signal cfg_readout_ctr_valid : std_logic; + signal cfg_insert_ttype : std_logic; + signal cfg_max_sub : std_logic_vector(15 downto 0); + signal cfg_max_queue : std_logic_vector(15 downto 0); + signal cfg_max_subs_in_queue : std_logic_vector(15 downto 0); + signal cfg_max_single_sub : std_logic_vector(15 downto 0); + signal cfg_additional_hdr : std_logic; + signal cfg_soft_rst : std_logic; + signal cfg_allow_rx : std_logic; + signal cfg_max_frame : std_logic_vector(15 downto 0); + + signal tc_rd_en : std_logic := '0'; + signal tc_data : std_logic_vector( 8 downto 0); + signal tc_size : std_logic_vector(15 downto 0); + signal resp_ready : std_logic := '0'; + signal resp_busy : std_logic := '0'; + signal cri_readout_finished_in : std_logic; + + signal cri_init_dataready_out : std_logic; + signal cri_init_data_out : std_logic_vector(15 downto 0); + signal cri_init_packet_num_out : std_logic_vector( 2 downto 0); + signal cri_init_read_in : std_logic; + + signal cri_reply_dataready_in : std_logic; + signal cri_reply_data_in : std_logic_vector(15 downto 0); + signal cri_reply_packet_num_in : std_logic_vector( 2 downto 0); + signal cri_reply_read_out : std_logic; + + --API data Transmitter to CRI + signal cri_apl_data_in : std_logic_vector(15 downto 0); + signal cri_apl_packet_num_in : std_logic_vector( 2 downto 0); + signal cri_apl_dataready_in : std_logic; + signal cri_apl_read_out : std_logic; + signal cri_apl_send_in : std_logic; + + --API data Receiver from CRI + signal cri_apl_data_out : std_logic_vector(15 downto 0); + signal cri_apl_packet_num_out : std_logic_vector( 2 downto 0); + signal cri_apl_typ_out : std_logic_vector( 2 downto 0); + signal cri_apl_dataready_out : std_logic; + signal cri_apl_read_in : std_logic; + + --API data controller + signal cri_apl_run_out : std_logic; + signal cri_packet_num_cnt : unsigned( 1 downto 0) := 0; + signal cri_data_send_cnt : unsigned(15 downto 0) := 0; + signal cri_send : std_logic; + + signal cri_event_cnt : unsigned(15 downto 0) := 0; + + --DEBUG SIGNALS: + signal debug_resp_control : std_logic_vector(63 downto 0); + signal readout_finished_cnt, readout_start_cnt : unsigned(15 downto 0); + signal last_cts_readout_finished, last_cts_readout_start : std_logic; + + signal dbg_pc_wr_en : std_logic; + signal dbg_pc_data : std_logic_vector( 7 downto 0); + signal dbg_pc_sos : std_logic; + signal dbg_pc_eos : std_logic; + signal dbg_pc_eoq : std_logic; + signal dbg_pc_sub_size : std_logic_vector(31 downto 0); + signal dbg_pc_trig_nr : std_logic_vector(31 downto 0); + signal dbg_pc_trig_type : std_logic_vector( 3 downto 0); + + signal last_dbg_pc_wr_en : std_logic; + signal last_dbg_pc_sos : std_logic; + signal last_dbg_pc_eos : std_logic; + signal last_dbg_pc_eoq : std_logic; + + signal dbg_pc_wr_en_cnt : unsigned(15 downto 0); + signal dbg_pc_sos_cnt : unsigned(15 downto 0); + signal dbg_pc_eos_cnt : unsigned(15 downto 0); + signal dbg_pc_eoq_cnt : unsigned(15 downto 0); + + signal dbg_api_fifo_to_int : std_logic_vector(31 downto 0); + signal dbg_api_fifo_to_api : std_logic_vector(31 downto 0); + + signal dbg_start_data_send : std_logic := '0'; + + signal dbg_io_dataready_cnt_2 : unsigned(15 downto 0); + signal dbg_io_dataready_cnt_3 : unsigned(15 downto 0); + signal dbg_io_dataready_cnt_6 : unsigned(15 downto 0); + signal dbg_io_dataready_cnt_7 : unsigned(15 downto 0); + + signal resp_ready_q : std_logic := '0'; + signal resp_ready_qq : std_logic := '0'; + signal resp_ready_3q : std_logic := '0'; + signal resp_ready_4q : std_logic := '0'; + signal resp_ready_5q : std_logic := '0'; + signal resp_ready_6q : std_logic := '0'; + + signal tc_data_rdy : std_logic; + + signal tmp_data, ipu_data : std_logic_vector( 7 downto 0); + + signal ipu_wr_en, ipu_wr_en_q, ipu_wr_en_qq, ipu_wr_en_qqq : std_logic; + signal ipu_sos_out_q, ipu_sos_out_qq, ipu_sos_out_qqq : std_logic; + signal ipu_eod_out_q, ipu_eod_out_qq, ipu_eod_out_qqq : std_logic; + signal ipu_data_start, ipu_data_end : std_logic; + signal ipu_sub_size : std_logic_vector(31 downto 0); + + signal ipu_ready_in : std_logic; + signal ipu_start_rdy : std_logic; + signal loaded_bytes : std_logic_vector(15 downto 0); + + signal debug_sender :std_logic_vector(191 downto 0); +begin + +--------------------------------------------------------------------- +-- Reset +--------------------------------------------------------------------- +--13: reset sequence received +--14: not connected +--15: send reset sequence + + SYNC_RESET_MUX_IO : process(CLK) + begin + if rising_edge(CLK) then + reset_i <= RESET; + reset_i_mux_io <= MEDIA_MED2INT(0).stat_op(14) or reset_i; + end if; + end process; + + + + + +--------------------------------------------------------------------- +-- I/O Buffers +--------------------------------------------------------------------- +-- iobuf of Trigger channel -> As CTS is part of Combiner, this channel is +-- not used anymore in this place + +-- channel 0 + THE_IOBUF_0 : trb_net16_term_buf + port map ( + -- Misc + CLK => CLK , + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => io_dataready_out(0), + MED_INIT_DATA_OUT => io_data_out(15 downto 0), + MED_INIT_PACKET_NUM_OUT => io_packet_num_out(2 downto 0), + MED_INIT_READ_IN => io_read_in(0), + + MED_REPLY_DATAREADY_OUT => io_dataready_out(1), + MED_REPLY_DATA_OUT => io_data_out(31 downto 16), + MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(5 downto 3), + MED_REPLY_READ_IN => io_read_in(1), + + MED_DATAREADY_IN => io_dataready_in(0), + MED_DATA_IN => io_data_in(15 downto 0), + MED_PACKET_NUM_IN => io_packet_num_in(2 downto 0), + MED_READ_OUT => io_read_out(0) + ); + +--------------------------------------------------------------------- +-- TrbNet Data Readout +--------------------------------------------------------------------- + trbnet_gen : if INCLUDE_READOUT = 1 generate + + THE_CRI_DATA_SENDER : entity work.cri_data_sender + port map( + -- Misc + CLK => CLK, + RESET => reset_i, + CLK_EN => '1', + + ENABLE_TRANSPORT => dbg_start_data_send, + + -- Port to API + API_DATA_OUT => cri_apl_data_in, + API_PACKET_NUM_OUT => cri_apl_packet_num_in, + API_DATAREADY_OUT => cri_apl_dataready_in, + API_READ_IN => cri_apl_read_out, + API_SHORT_TRANSFER_OUT => open, + API_DTYPE_OUT => open, + API_ERROR_PATTERN_OUT => open, + API_SEND_OUT => cri_apl_send_in, + -- Receiver port + API_DATA_IN => cri_apl_data_out, + API_PACKET_NUM_IN => cri_apl_packet_num_out, + API_TYP_IN => cri_apl_typ_out, + API_DATAREADY_IN => cri_apl_dataready_out, + API_READ_OUT => cri_apl_read_in, + -- APL Control port + API_RUN_IN => cri_apl_run_out, + API_SEQNR_IN => (others => '0'), + API_LENGTH_OUT => open, + MY_ADDRESS_IN => MY_ADDRESS_IN, + + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_READ_IN => '1', + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_BUSY_IN => FEE_BUSY_IN, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + + DEBUG_OUT => debug_sender + ); + +-- THE_IPU_INTERFACE : entity work.trb_net16_cri_ipu_interface +-- port map ( +-- CLK_IPU => CLK, +-- CLK_CRI => CLK, +-- RESET => reset_i, +-- -- IPU interface directed toward the CTS +-- CTS_NUMBER_IN => CTS_NUMBER_IN, +-- CTS_CODE_IN => CTS_CODE_IN, +-- CTS_INFORMATION_IN => CTS_INFORMATION_IN, +-- CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, +-- CTS_START_READOUT_IN => CTS_START_READOUT_IN, +-- CTS_READ_IN => '1', +-- CTS_DATA_OUT => open, +-- CTS_DATAREADY_OUT => open, +-- CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, +-- CTS_LENGTH_OUT => open, +-- CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, +-- -- Data from Frontends +-- FEE_DATA_IN => FEE_DATA_IN, +-- FEE_DATAREADY_IN => FEE_DATAREADY_IN, +-- FEE_READ_OUT => FEE_READ_OUT, +-- FEE_BUSY_IN => FEE_BUSY_IN, +-- FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, +-- -- slow control interface +-- DATA_IPU_ENABLE_IN => '1', +-- MULT_EVT_ENABLE_IN => '0', +-- MAX_SUBEVENT_SIZE_IN => (others => '1'), +-- MAX_QUEUE_SIZE_IN => (others => '1'), +-- MAX_SUBS_IN_QUEUE_IN => (others => '1'), +-- MAX_SINGLE_SUB_SIZE_IN => (others => '1'), +-- READOUT_CTR_IN => (others => '0'), +-- READOUT_CTR_VALID_IN => '0', +-- -- PacketConstructor interface +-- PC_WR_EN_OUT => ipu_wr_en, +-- PC_DATA_OUT => ipu_data, +-- PC_READY_IN => ipu_ready_in, +-- PC_SOS_OUT => ipu_data_start, +-- PC_EOS_OUT => open, +-- PC_EOQ_OUT => ipu_data_end, +-- PC_SUB_SIZE_OUT => ipu_sub_size, +-- PC_TRIG_NR_OUT => open, +-- PC_TRIGGER_TYPE_OUT => open, +-- +-- MONITOR_OUT => open, +-- DEBUG_OUT => open +-- ); + + + THE_CRI_DATARDY_DBG : process begin + wait until rising_edge(CLK); + if RESET = '1' then + dbg_io_dataready_cnt_2 <= 0; + dbg_io_dataready_cnt_3 <= 0; + dbg_io_dataready_cnt_6 <= 0; + dbg_io_dataready_cnt_7 <= 0; + else + if io_dataready_out(2) = '1' then + dbg_io_dataready_cnt_2 <= dbg_io_dataready_cnt_2 + 1; + end if; + + if io_dataready_out(3) = '1' then + dbg_io_dataready_cnt_3 <= dbg_io_dataready_cnt_3 + 1; + end if; + + if io_dataready_out(6) = '1' then + dbg_io_dataready_cnt_6 <= dbg_io_dataready_cnt_6 + 1; + end if; + + if io_dataready_out(7) = '1' then + dbg_io_dataready_cnt_7 <= dbg_io_dataready_cnt_7 + 1; + end if; + end if; + end process; + +--------------------------------------------------------------------- +-- active API for Data Channel +--------------------------------------------------------------------- + TRG_CHANNEL_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => 6, + FIFO_TO_APL_DEPTH => 6, + FORCE_REPLY => 1, + SBUF_VERSION => 0, + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS=> c_YES + ) + port map ( + -- Misc + CLK => CLK, + RESET => reset_i, + CLK_EN => '1', + -- APL Transmitter port + APL_DATA_IN => cri_apl_data_in, + APL_PACKET_NUM_IN => cri_apl_packet_num_in, + APL_DATAREADY_IN => cri_apl_dataready_in, -- almostfullflag ; daten in fifo von 8 auf 16 bit packen + APL_READ_OUT => cri_apl_read_out, + APL_SHORT_TRANSFER_IN => '0', + APL_DTYPE_IN => (others => '0'), + APL_ERROR_PATTERN_IN => (others => '0'), + APL_SEND_IN => cri_apl_send_in, -- 1 till end of Datastream + APL_TARGET_ADDRESS_IN => (others => '1'), + -- Receiver port + APL_DATA_OUT => cri_apl_data_out, + APL_PACKET_NUM_OUT => cri_apl_packet_num_out, + APL_TYP_OUT => cri_apl_typ_out, + APL_DATAREADY_OUT => cri_apl_dataready_out, + APL_READ_IN => cri_apl_read_in, + -- APL Control port + APL_RUN_OUT => cri_apl_run_out, + APL_MY_ADDRESS_IN => MY_ADDRESS_IN, + APL_SEQNR_OUT => open, + APL_LENGTH_IN => (others => '0'), + APL_FIFO_COUNT_OUT => open, + + -- Internal direction port + INT_MASTER_DATAREADY_OUT => cri_init_dataready_out, + INT_MASTER_DATA_OUT => cri_init_data_out, + INT_MASTER_PACKET_NUM_OUT=> cri_init_packet_num_out, + INT_MASTER_READ_IN => cri_init_read_in, + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => "000", + INT_MASTER_READ_OUT => open, + INT_SLAVE_DATAREADY_OUT => open, + INT_SLAVE_DATA_OUT => open, + INT_SLAVE_PACKET_NUM_OUT => open, + INT_SLAVE_READ_IN => '1', + INT_SLAVE_DATAREADY_IN => cri_reply_dataready_in, + INT_SLAVE_DATA_IN => cri_reply_data_in, + INT_SLAVE_PACKET_NUM_IN => cri_reply_packet_num_in, + INT_SLAVE_READ_OUT => cri_reply_read_out, + -- Status and control port + CTRL_SEQNR_RESET => '0',--common_ctrl(10), --TO BE IMPLEMENTED + STAT_FIFO_TO_INT => dbg_api_fifo_to_int, + STAT_FIFO_TO_APL => dbg_api_fifo_to_api + ); + + --iobuf on streaming api, towards CRI, data channel + THE_IOBUF_1 : trb_net16_iobuf + generic map( + IBUF_DEPTH => 6, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(1), + USE_CHECKSUM => cfg_USE_CHECKSUM(1), + INIT_CAN_SEND_DATA => c_YES, + INIT_CAN_RECEIVE_DATA => c_NO, + REPLY_CAN_SEND_DATA => c_NO, + REPLY_CAN_RECEIVE_DATA => c_YES + ) + port map( + -- Misc + CLK => CLK, + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => io_dataready_out(2), + MED_INIT_DATA_OUT => io_data_out(47 downto 32), + MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6), + MED_INIT_READ_IN => io_read_in(2), + + MED_REPLY_DATAREADY_OUT => io_dataready_out(3), + MED_REPLY_DATA_OUT => io_data_out(63 downto 48), + MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(11 downto 9), + MED_REPLY_READ_IN => io_read_in(3), + + MED_DATAREADY_IN => io_dataready_in(1), + MED_DATA_IN => io_data_in(31 downto 16), + MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3), + MED_READ_OUT => io_read_out(1), + MED_ERROR_IN => io_error_in, + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => open, + INT_INIT_DATA_OUT => open, + INT_INIT_PACKET_NUM_OUT => open, + INT_INIT_READ_IN => '1', + + INT_INIT_DATAREADY_IN => cri_init_dataready_out, + INT_INIT_DATA_IN => cri_init_data_out, -- gbe like data to CRI + INT_INIT_PACKET_NUM_IN => cri_init_packet_num_out, + INT_INIT_READ_OUT => cri_init_read_in, + + INT_REPLY_DATAREADY_OUT => cri_reply_dataready_in, + INT_REPLY_DATA_OUT => cri_reply_data_in, -- answer from CRI + INT_REPLY_PACKET_NUM_OUT => cri_reply_packet_num_in, + INT_REPLY_READ_IN => cri_reply_read_out, + + INT_REPLY_DATAREADY_IN => '0', + INT_REPLY_DATA_IN => (others => '0'), + INT_REPLY_PACKET_NUM_IN => (others => '0'), + INT_REPLY_READ_OUT => open, + + -- Status and control port + STAT_GEN => open, + STAT_IBUF_BUFFER => open, + CTRL_GEN => (others => '0'), + STAT_INIT_OBUF_DEBUG => open, + STAT_REPLY_OBUF_DEBUG => open, + TIMER_TICKS_IN => TIMER_TICKS_IN + ); + end generate trbnet_gen; + + + + + no_readout_gen : if INCLUDE_READOUT = 0 generate + -- terminate data channel if no readout + THE_IOBUF_1 : trb_net16_term_buf + port map ( + -- Misc + CLK => CLK, + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => io_dataready_out(2), + MED_INIT_DATA_OUT => io_data_out(47 downto 32), + MED_INIT_PACKET_NUM_OUT => io_packet_num_out(8 downto 6), + MED_INIT_READ_IN => io_read_in(2), + + MED_REPLY_DATAREADY_OUT => io_dataready_out(3), + MED_REPLY_DATA_OUT => io_data_out(63 downto 48), + MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(11 downto 9), + MED_REPLY_READ_IN => io_read_in(3), + + MED_DATAREADY_IN => io_dataready_in(1), + MED_DATA_IN => io_data_in(31 downto 16), + MED_PACKET_NUM_IN => io_packet_num_in(5 downto 3), + MED_READ_OUT => io_read_out(1) + ); + + --Terminate Data + THE_TrbNetData : entity work.trb_net16_gbe_ipu_interface + generic map( + DO_SIMULATION => 0 + ) + port map ( + CLK_IPU => CLK, + CLK_GBE => CLK, + RESET => reset_i_mux_io, + + CTS_NUMBER_IN => CTS_NUMBER_IN, + CTS_CODE_IN => CTS_CODE_IN, + CTS_INFORMATION_IN => CTS_INFORMATION_IN, + CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN, + CTS_START_READOUT_IN => CTS_START_READOUT_IN, + CTS_READ_IN => '1', + CTS_DATA_OUT => open, + CTS_DATAREADY_OUT => open, + CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT, + CTS_LENGTH_OUT => open, + CTS_ERROR_PATTERN_OUT => CTS_STATUS_BITS_OUT, + -- Data from Frontends + FEE_DATA_IN => FEE_DATA_IN, + FEE_DATAREADY_IN => FEE_DATAREADY_IN, + FEE_READ_OUT => FEE_READ_OUT, + FEE_BUSY_IN => FEE_BUSY_IN, + FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN, + -- slow control interface + START_CONFIG_OUT => open, + BANK_SELECT_OUT => open, + CONFIG_DONE_IN => '1', + DATA_GBE_ENABLE_IN => cfg_gbe_enable, + DATA_IPU_ENABLE_IN => cfg_ipu_enable, -- never used in code + MULT_EVT_ENABLE_IN => cfg_mult_enable, + MAX_SUBEVENT_SIZE_IN => cfg_max_sub, + MAX_QUEUE_SIZE_IN => cfg_max_queue, + MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue, + MAX_SINGLE_SUB_SIZE_IN => cfg_max_single_sub, + READOUT_CTR_IN => cfg_readout_ctr, + READOUT_CTR_VALID_IN => cfg_readout_ctr_valid, + CFG_AUTO_THROTTLE_IN => '0', + CFG_THROTTLE_PAUSE_IN => (others => '0'), + -- PacketConstructor interface + PC_WR_EN_OUT => dbg_pc_wr_en, + PC_DATA_OUT => dbg_pc_data, + PC_READY_IN => '1', + PC_SOS_OUT => dbg_pc_sos, + PC_EOS_OUT => dbg_pc_eos, + PC_EOQ_OUT => dbg_pc_eoq, + PC_SUB_SIZE_OUT => dbg_pc_sub_size, + PC_TRIG_NR_OUT => dbg_pc_trig_nr, + PC_TRIGGER_TYPE_OUT => dbg_pc_trig_type, + MONITOR_OUT => open, + DEBUG_OUT => open + ); +-- --Clean Data Output +-- CTS_READOUT_FINISHED_OUT <= '1'; +-- CTS_STATUS_BITS_OUT <= (others => '0'); +-- FEE_READ_OUT <= '0'; --maybe high if idle? + end generate no_readout_gen; + + +--who cares about an unused channel? + THE_IOBUF_2 : trb_net16_term_buf + port map ( + -- Misc + CLK => CLK , + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => io_dataready_out(4), + MED_INIT_DATA_OUT => io_data_out(79 downto 64), + MED_INIT_PACKET_NUM_OUT => io_packet_num_out(14 downto 12), + MED_INIT_READ_IN => io_read_in(4), + + MED_REPLY_DATAREADY_OUT => io_dataready_out(5), + MED_REPLY_DATA_OUT => io_data_out(95 downto 80), + MED_REPLY_PACKET_NUM_OUT=> io_packet_num_out(17 downto 15), + MED_REPLY_READ_IN => io_read_in(5), + + MED_DATAREADY_IN => io_dataready_in(2), + MED_DATA_IN => io_data_in(47 downto 32), + MED_PACKET_NUM_IN => io_packet_num_in(8 downto 6), + MED_READ_OUT => io_read_out(2) + ); + +--iobuf towards slow control channel + THE_IOBUF_3 : trb_net16_iobuf + generic map( + IBUF_DEPTH => 6, + USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(3), + USE_CHECKSUM => cfg_USE_CHECKSUM(3), + INIT_CAN_SEND_DATA => c_NO,--MII_IS_DOWNLINK(mii), + INIT_CAN_RECEIVE_DATA => c_YES,--MII_IS_UPLINK(mii), + REPLY_CAN_SEND_DATA => c_YES,--MII_IS_UPLINK(mii), + REPLY_CAN_RECEIVE_DATA => c_NO--MII_IS_DOWNLINK(mii) + ) + port map( + -- Misc + CLK => CLK, + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + -- Media direction port + MED_INIT_DATAREADY_OUT => io_dataready_out(6), + MED_INIT_DATA_OUT => io_data_out(111 downto 96), + MED_INIT_PACKET_NUM_OUT => io_packet_num_out(20 downto 18), + MED_INIT_READ_IN => io_read_in(6), + + MED_REPLY_DATAREADY_OUT => io_dataready_out(7), + MED_REPLY_DATA_OUT => io_data_out(127 downto 112), + MED_REPLY_PACKET_NUM_OUT => io_packet_num_out(23 downto 21), + MED_REPLY_READ_IN => io_read_in(7), + + MED_DATAREADY_IN => io_dataready_in(3), + MED_DATA_IN => io_data_in(63 downto 48), + MED_PACKET_NUM_IN => io_packet_num_in(11 downto 9), + MED_READ_OUT => io_read_out(3), + MED_ERROR_IN => io_error_in, + + -- Internal direction port + + INT_INIT_DATAREADY_OUT => GSC_INIT_DATAREADY_OUT, + INT_INIT_DATA_OUT => GSC_INIT_DATA_OUT, + INT_INIT_PACKET_NUM_OUT => GSC_INIT_PACKET_NUM_OUT, + INT_INIT_READ_IN => GSC_INIT_READ_IN, + + INT_INIT_DATAREADY_IN => '0', + INT_INIT_DATA_IN => (others => '0'), + INT_INIT_PACKET_NUM_IN => (others => '0'), + INT_INIT_READ_OUT => open, + + INT_REPLY_DATAREADY_OUT => open, + INT_REPLY_DATA_OUT => open, + INT_REPLY_PACKET_NUM_OUT => open, + INT_REPLY_READ_IN => '1', + + INT_REPLY_DATAREADY_IN => GSC_REPLY_DATAREADY_IN, + INT_REPLY_DATA_IN => GSC_REPLY_DATA_IN, + INT_REPLY_PACKET_NUM_IN => GSC_REPLY_PACKET_NUM_IN, + INT_REPLY_READ_OUT => GSC_REPLY_READ_OUT, + + -- Status and control port + STAT_GEN => open, + STAT_IBUF_BUFFER => open, + CTRL_GEN => (others => '0'), + STAT_INIT_OBUF_DEBUG => open, + STAT_REPLY_OBUF_DEBUG => open, + TIMER_TICKS_IN => TIMER_TICKS_IN + ); + + +--------------------------------------------------------------------- +-- Multiplexer +--------------------------------------------------------------------- + MPLEX: trb_net16_io_multiplexer + port map ( + CLK => CLK, + RESET => reset_i_mux_io, + CLK_EN => CLK_EN, + MED_DATAREADY_IN => MEDIA_MED2INT(0).dataready, + MED_DATA_IN => MEDIA_MED2INT(0).data, + MED_PACKET_NUM_IN => MEDIA_MED2INT(0).packet_num, + MED_READ_OUT => open, + MED_DATAREADY_OUT => MEDIA_INT2MED(0).dataready, + MED_DATA_OUT => MEDIA_INT2MED(0).data, + MED_PACKET_NUM_OUT => MEDIA_INT2MED(0).packet_num, + MED_READ_IN => MEDIA_MED2INT(0).tx_read, + INT_DATAREADY_OUT => io_dataready_in, + INT_DATA_OUT => io_data_in, + INT_PACKET_NUM_OUT => io_packet_num_in, + INT_READ_IN => io_read_out, + INT_DATAREADY_IN => io_dataready_out, + INT_DATA_IN => io_data_out, + INT_PACKET_NUM_IN => io_packet_num_out, + INT_READ_OUT => io_read_in, + CTRL => (others => '0'), + STAT => open + ); + io_error_in <= MEDIA_MED2INT(0).stat_op(2 downto 0); + + + SETUP : gbe_setup + port map( + CLK => CLK, + RESET => reset_i_mux_io, + + -- interface to regio bus + BUS_ADDR_IN => BUS_REG_RX.addr(7 downto 0), + BUS_DATA_IN => BUS_REG_RX.data, + BUS_DATA_OUT => BUS_REG_TX.data, + BUS_WRITE_EN_IN => BUS_REG_RX.write, + BUS_READ_EN_IN => BUS_REG_RX.read, + BUS_ACK_OUT => BUS_REG_TX.ack, + + -- output to gbe_buf + GBE_SUBEVENT_ID_OUT => cfg_subevent_id, + GBE_SUBEVENT_DEC_OUT => cfg_subevent_dec, + GBE_QUEUE_DEC_OUT => cfg_queue_dec, + GBE_MAX_FRAME_OUT => cfg_max_frame, + GBE_USE_GBE_OUT => cfg_gbe_enable, + GBE_USE_TRBNET_OUT => cfg_ipu_enable, + GBE_USE_MULTIEVENTS_OUT => cfg_mult_enable, + GBE_READOUT_CTR_OUT => cfg_readout_ctr, + GBE_READOUT_CTR_VALID_OUT => cfg_readout_ctr_valid, + GBE_ALLOW_RX_OUT => cfg_allow_rx, + GBE_ADDITIONAL_HDR_OUT => cfg_additional_hdr, + GBE_INSERT_TTYPE_OUT => cfg_insert_ttype, + GBE_SOFT_RESET_OUT => cfg_soft_rst, + GBE_MAX_REPLY_OUT => open, -- is for SLWCNTR + GBE_MAX_SUB_OUT => cfg_max_sub, + GBE_MAX_QUEUE_OUT => cfg_max_queue, + GBE_MAX_SUBS_IN_QUEUE_OUT => cfg_max_subs_in_queue, + GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub, + GBE_AUTOTHROTTLE_OUT => open, + GBE_THROTTLE_PAUSE_OUT => open, + MONITOR_RX_BYTES_IN => (others => '0'), --sum_rx_bytes, + MONITOR_RX_FRAMES_IN => (others => '0'), --sum_rx_frames, + MONITOR_TX_BYTES_IN => (others => '0'), --sum_tx_bytes, + MONITOR_TX_FRAMES_IN => (others => '0'), --sum_tx_frames, + MONITOR_TX_PACKETS_IN => (others => '0'), --sum_tx_packets, + MONITOR_DROPPED_IN => (others => '0'), --sum_dropped, + MONITOR_SELECT_REC_IN => (others => '0'), --dbg_select_rec, + MONITOR_SELECT_REC_BYTES_IN => (others => '0'), --dbg_select_rec_bytes, + MONITOR_SELECT_SENT_BYTES_IN => (others => '0'), --dbg_select_sent_bytes, + MONITOR_SELECT_SENT_IN => (others => '0'), --dbg_select_sent, + MONITOR_SELECT_DROP_IN_IN => (others => '0'), --dbg_select_drop_in, + MONITOR_SELECT_DROP_OUT_IN => (others => '0'), --dbg_select_drop_out, + MONITOR_SELECT_GEN_DBG_IN => (others => '0'), --monitor_gen_dbg, --dbg_select_gen, + + DUMMY_EVENT_SIZE_OUT => open,--dummy_event, + DUMMY_TRIGGERED_MODE_OUT => open, + DATA_HIST_IN => (others => (others => '0')), --dbg_hist, + SCTRL_HIST_IN => (others => (others => '0')) --dbg_hist2 + ); + + + debug_gen : if INCLUDE_READOUT = 0 generate + + THE_CTS_READOUT_FINISHED_CNT : process begin + wait until rising_edge(CLK); + + if RESET = '1' then + last_cts_readout_finished <= '0'; + last_cts_readout_start <= '0'; + + last_dbg_pc_wr_en <= '0'; + last_dbg_pc_sos <= '0'; + last_dbg_pc_eos <= '0'; + last_dbg_pc_eoq <= '0'; + + readout_finished_cnt <= 0; + readout_start_cnt <= 0; + + dbg_pc_wr_en_cnt <= 0; + dbg_pc_sos_cnt <= 0; + dbg_pc_eos_cnt <= 0; + dbg_pc_eoq_cnt <= 0; + else + last_cts_readout_finished <= CTS_READOUT_FINISHED_OUT; + last_cts_readout_start <= CTS_START_READOUT_IN; + if ((CTS_READOUT_FINISHED_OUT and (not last_cts_readout_finished)) = '1') then + readout_finished_cnt <= readout_finished_cnt + 1; + end if; + + if ((CTS_START_READOUT_IN and (not last_cts_readout_start)) = '1') then + readout_start_cnt <= readout_start_cnt + 1; + end if; + + ------------------- + + last_dbg_pc_wr_en <= dbg_pc_wr_en; + if ((dbg_pc_wr_en and (not last_dbg_pc_wr_en)) = '1') then + dbg_pc_wr_en_cnt <= dbg_pc_wr_en_cnt + 1; + end if; + + last_dbg_pc_sos <= dbg_pc_sos; + if ((dbg_pc_sos and (not last_dbg_pc_sos)) = '1') then + dbg_pc_sos_cnt <= dbg_pc_sos_cnt + 1; + end if; + + last_dbg_pc_eos <= dbg_pc_eos; + if ((dbg_pc_eos and (not last_dbg_pc_eos)) = '1') then + dbg_pc_eos_cnt <= dbg_pc_eos_cnt + 1; + end if; + + last_dbg_pc_eoq <= dbg_pc_eoq; + if ((dbg_pc_eoq and (not last_dbg_pc_eoq)) = '1') then + dbg_pc_eoq_cnt <= dbg_pc_eoq_cnt + 1; + end if; + + ------------------- + end if; + end process; + + + THE_CRI_READOUT_DEBUG : process begin + wait until rising_edge(CLK); + BUS_DBG_TX.ack <= '0'; + BUS_DBG_TX.nack <= '0'; + BUS_DBG_TX.unknown <= '0'; + + if BUS_DBG_RX.read = '1' then + if BUS_DBG_RX.addr(7 downto 0) = x"00" then + BUS_DBG_TX.data <= debug_resp_control(31 downto 0); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"01" then + BUS_DBG_TX.data <= debug_resp_control(63 downto 32); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"02" then + BUS_DBG_TX.data(15 downto 0) <= CTS_NUMBER_IN; + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(readout_finished_cnt); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"03" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(readout_start_cnt); + BUS_DBG_TX.data(19 downto 16) <= "000" & cfg_gbe_enable; + BUS_DBG_TX.data(23 downto 20) <= "000" & cfg_ipu_enable; + BUS_DBG_TX.data(27 downto 24) <= "000" & cfg_mult_enable; + BUS_DBG_TX.data(31 downto 28) <= "0000"; + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"04" then + BUS_DBG_TX.data(7 downto 0) <= dbg_pc_data; + BUS_DBG_TX.data(15 downto 8) <= x"00"; + BUS_DBG_TX.data(19 downto 16) <= dbg_pc_trig_type; + BUS_DBG_TX.data(23 downto 20) <= x"0"; + BUS_DBG_TX.data(24) <= dbg_pc_wr_en; + BUS_DBG_TX.data(25) <= dbg_pc_sos; + BUS_DBG_TX.data(26) <= dbg_pc_eos; + BUS_DBG_TX.data(27) <= dbg_pc_eoq; + BUS_DBG_TX.data(31 downto 28) <= x"0"; + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"05" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_wr_en_cnt); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_sos_cnt); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"06" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_pc_eos_cnt); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_pc_eoq_cnt); + BUS_DBG_TX.ack <= '1'; + end if; + + elsif BUS_DBG_RX.write = '1' then + +-- if BUS_DBG_RX.addr( 7 downto 0) = x"00" then +-- dbg_start_data_send <= BUS_DBG_RX.data(0); +-- end if; +-- +-- BUS_DBG_TX.ack <= '1'; + end if; + end process; + end generate debug_gen; + +debug_gen : if INCLUDE_READOUT = 1 generate + + + THE_CRI_READOUT_DEBUG : process begin + wait until rising_edge(CLK); + BUS_DBG_TX.ack <= '0'; + BUS_DBG_TX.nack <= '0'; + BUS_DBG_TX.unknown <= '0'; + + if BUS_DBG_RX.read = '1' then + if BUS_DBG_RX.addr(7 downto 0) = x"00" then + BUS_DBG_TX.data <= debug_sender(31 downto 0); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"01" then + BUS_DBG_TX.data(0) <= dbg_start_data_send; + BUS_DBG_tX.data(31 downto 1) <= (others => '0'); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"02" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_2); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_3); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"03" then + BUS_DBG_TX.data(15 downto 0) <= std_logic_vector(dbg_io_dataready_cnt_6); + BUS_DBG_TX.data(31 downto 16) <= std_logic_vector(dbg_io_dataready_cnt_7); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"04" then + BUS_DBG_TX.data <= debug_sender(63 downto 32); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"05" then + BUS_DBG_TX.data <= debug_sender(95 downto 64); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"06" then + BUS_DBG_TX.data <= debug_sender(127 downto 96); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"07" then + BUS_DBG_TX.data <= debug_sender(159 downto 128); + BUS_DBG_TX.ack <= '1'; + end if; + + if BUS_DBG_RX.addr(7 downto 0) = x"08" then + BUS_DBG_TX.data <= debug_sender(191 downto 160); + BUS_DBG_TX.ack <= '1'; + end if; + + elsif BUS_DBG_RX.write = '1' then + + if BUS_DBG_RX.addr( 7 downto 0) = x"01" then + dbg_start_data_send <= BUS_DBG_RX.data(0); + BUS_DBG_TX.ack <= '1'; + end if; + + + end if; + end process; + end generate debug_gen; + +end architecture; + + + -- 2.43.0