From 80f44601733cb2f4efb1347822f0b94e6acf0072 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 2 Sep 2009 15:47:36 +0000 Subject: [PATCH] added flash programming & reboot --- design/mdc_addon_daq_bus_0.vhd | 6 +- mdc_oepb.prj | 5 + mdc_oepb.vhd | 428 +++++++++++++++++++++------------ 3 files changed, 282 insertions(+), 157 deletions(-) diff --git a/design/mdc_addon_daq_bus_0.vhd b/design/mdc_addon_daq_bus_0.vhd index 5bfc6b5..d4bd996 100644 --- a/design/mdc_addon_daq_bus_0.vhd +++ b/design/mdc_addon_daq_bus_0.vhd @@ -223,7 +223,7 @@ architecture behavioral of mdc_addon_daq_bus_0 is ------------------------------------------------------------------------------- -- tdc_readout_and_trb_interface ------------------------------------------------------------------------------- - DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0); TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; REINIT_ROC1_OUT : out std_logic; @@ -366,7 +366,7 @@ begin --behavioral A_ACK => a_ack_i, A_DST => a_dst_data_i, A_DRE => open, --enable_a_add_data_i, - + TOKEN_IN => token_back_out_i, INIT_TDC_READOUT_IN => init_tdc_readout_i, @@ -435,7 +435,7 @@ begin --behavioral A_DRB_2 <= '1'; --A_RDM enable A_DRA <= '0'; --A_ACK enable - + A_GDE <= a_gde_i; A_RES <= a_res_i; A_TOK <= a_tok_i; diff --git a/mdc_oepb.prj b/mdc_oepb.prj index b391f87..d72d801 100644 --- a/mdc_oepb.prj +++ b/mdc_oepb.prj @@ -48,6 +48,11 @@ add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" + add_file -vhdl -lib work "design/common_stop_generator.vhd" add_file -vhdl -lib work "design/counter_12bit.vhd" add_file -vhdl -lib work "design/counter_4bit.vhd" diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 84689cd..6a67435 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -26,17 +26,23 @@ entity mdc_oepb is WATCHDOG : out std_logic; CLK_FF : out std_logic; DATA_FF : out std_logic; + MRES : out std_logic; --ADC ADC_SCK : out std_logic; ADC_SDI : out std_logic; ADC_SDO : in std_logic; ADC_CONVST : out std_logic; + --SPI + SPI_CLK : out std_logic; + SPI_CS : out std_logic; + SPI_DIN : in std_logic; + SPI_DOUT : out std_logic; --MB --MRES : out std_logic; --global reset TAOD : inout std_logic; --address or data TACK : in std_logic; --MB address CMS : out std_logic; --common stop - COM_STOP : in std_logic; --common stop input from transceiner + COM_STOP_P : in std_logic; --common stop input from transceiner TDST : inout std_logic; --data strobe GDE : out std_logic; --global disable RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM) @@ -55,7 +61,6 @@ architecture mdc_oepb_arch of mdc_oepb is signal CLK_100 : std_logic; signal pll_locked : std_logic; - signal test_counter : unsigned(25 downto 0); signal reset_startup : std_logic; signal reset_internal : std_logic; signal reset_counter : unsigned(23 downto 0) := x"000000"; @@ -68,7 +73,6 @@ architecture mdc_oepb_arch of mdc_oepb is signal MED_STAT_OP : std_logic_vector(16-1 downto 0); signal MED_CTRL_OP : std_logic_vector(16-1 downto 0); signal MED_STAT_DEBUG : std_logic_vector(63 downto 0); - signal MED_CTRL_DEBUG : std_logic_vector(15 downto 0); signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0); signal LVL1_TRG_RECEIVED_OUT : std_logic; @@ -87,7 +91,6 @@ architecture mdc_oepb_arch of mdc_oepb is signal IPU_READ_OUT : std_logic; signal IPU_LENGTH_IN : std_logic_vector(15 downto 0); signal IPU_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); - signal ipu_counter : unsigned(15 downto 0); signal REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0); signal REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -119,6 +122,24 @@ architecture mdc_oepb_arch of mdc_oepb is signal adc_unknown_addr : std_logic; signal adc_timeout : std_logic; signal adc_stat : std_logic_vector(31 downto 0); + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; signal global_time : std_logic_vector(31 downto 0); signal local_time : std_logic_vector(7 downto 0); @@ -147,37 +168,41 @@ architecture mdc_oepb_arch of mdc_oepb is signal a_aod_configuration_i : std_logic; signal a_dst_data_i : std_logic; signal a_aod_data_i : std_logic; - signal pulse_trdyo_i : std_logic; signal debug_trigger_distributor_i : std_logic_vector(31 downto 0); - signal last_LVL1_TRG_RECEIVED_OUT : std_logic; signal pulse_pseudo_timing_trigger : std_logic; signal cal_trigger_register_in_i : std_logic_vector(15 downto 0); signal direction_data_line_out_i : std_logic_vector(3 downto 0); signal motherboard_type_in_i : std_logic_vector(3 downto 0); signal pulse_begin_run_trigger_i : std_logic; - signal data_type_select_in_i : std_logic_vector(19 downto 0); - - signal datbus_data_out : std_logic_vector(31 downto 0); - signal datbus_addr_out : std_logic_vector(15 downto 0); - signal datbus_timeout_out : std_logic; + signal data_type_select_in_i : std_logic_vector(15 downto 0); signal test_debug_i : std_logic_vector(7 downto 0); signal counter_led : unsigned(31 downto 0); - signal reset_counter_led : std_logic; - signal counter: std_logic_vector (3 downto 0); signal test_pseudo_signal_i : std_logic; - signal flash_mem_data : std_logic_vector(31 downto 0); - signal flash_mem_data_out : std_logic_vector(31 downto 0); - signal flash_mem_write: std_logic; - signal flash_mem_read : std_logic; - signal flash_mem_addr : std_logic_vector(8 downto 0); + signal delayed_restart_fpga : std_logic; + signal restart_fpga_counter : unsigned(11 downto 0); + + signal flash_rom_read : std_logic; + signal flash_rom_write : std_logic; + signal next_flash_rom_select : std_logic; + signal flash_rom_select : std_logic; + signal flash_rom_clk : std_logic; + signal next_flash_rom_clk : std_logic; + + - signal cmd_register_in : std_logic_vector(31 downto 0); - signal ctrl_register : std_logic_vector(31 downto 0); - signal write_cmd_register_in : std_logic; - signal write_ctrl_register : std_logic; +-- signal flash_mem_data : std_logic_vector(31 downto 0); +-- signal flash_mem_data_out : std_logic_vector(31 downto 0); +-- signal flash_mem_write: std_logic; +-- signal flash_mem_read : std_logic; +-- signal flash_mem_addr : std_logic_vector(8 downto 0); + +-- signal cmd_register_in : std_logic_vector(31 downto 0); +-- signal ctrl_register : std_logic_vector(31 downto 0); +-- signal write_cmd_register_in : std_logic; +-- signal write_ctrl_register : std_logic; signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic; @@ -187,19 +212,21 @@ architecture mdc_oepb_arch of mdc_oepb is -- signal input_parity_gen : std_logic_vector(9 downto 0); - type tt is array (3000 downto 0) of std_logic_vector(3 downto 0); +-- type tt is array (3000 downto 0) of std_logic_vector(3 downto 0); -- signal data_in, data_out : tt; - + -- --signal counter_data : unsigned(35 downto 0); -- signal counter_data : std_logic_vector(35 downto 0); - signal out_shift_reg : tt; - signal out_shift_reg1 : std_logic_vector(3 downto 0); - signal temp_led0, temp_led1, temp_led2, temp_led3 : std_logic; +-- signal out_shift_reg : tt; +-- signal out_shift_reg1 : std_logic_vector(3 downto 0); +-- signal temp_led0, temp_led1, temp_led2, temp_led3 : std_logic; + + + - begin - + --------------------------------------------------------------------- -- PLL: 100 MHz --------------------------------------------------------------------- @@ -241,8 +268,45 @@ begin -- Flash FF --------------------------------------------------------------------- - CLK_FF <= '0'; - DATA_FF <= '0'; + + --force watchdog to restart fpga + MRES <= not delayed_restart_fpga; + + --delay restart command to finish trbnet transfer + process (CLK_100) + begin + if rising_edge(CLK_100) then + delayed_restart_fpga <= '0'; + if reset_internal = '1' then + restart_fpga_counter <= x"FFF"; + elsif REGIO_COMMON_CTRL_REG_OUT(15) = '1' then + restart_fpga_counter <= x"000"; + elsif restart_fpga_counter /= x"FFF" then + restart_fpga_counter <= restart_fpga_counter + 1; + if restart_fpga_counter >= x"F00" then + delayed_restart_fpga <= '1'; + end if; + end if; + end if; + end process; + + + PROC_CONTRL_FLASH_SELECT : process (CLK_100) + begin + if rising_edge(CLK_100) then + flash_rom_clk <= next_flash_rom_clk; + if flash_rom_write = '1' then + flash_rom_select <= next_flash_rom_select; + next_flash_rom_clk <= '1'; + else + next_flash_rom_clk <= '0'; + end if; + end if; + end process; + + CLK_FF <= flash_rom_clk; + DATA_FF <= flash_rom_select; + --------------------------------------------------------------------- -- trbnet endpoint @@ -250,7 +314,7 @@ begin API: trb_net16_endpoint_hades_full generic map( REGIO_NUM_STAT_REGS => 3,--4, --16 stat reg - REGIO_NUM_CTRL_REGS => 3,--3, --8 cotrol reg + REGIO_NUM_CTRL_REGS => 3,--3, --8 cotrol reg --standard values for output registers REGIO_INIT_CTRL_REGS => (others => '0'), --set to 0 for unused ctrl registers to save resources @@ -298,7 +362,7 @@ begin -- Slow Control Data Port REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN, --0x00 REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, --0x20 - REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, --start 0x80 + REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, --start 0x80 REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, --start 0xc0 --following ports only used when using internal data port @@ -319,6 +383,7 @@ begin REGIO_IDRAM_WR_IN => REGIO_IDRAM_WR_IN, REGIO_ONEWIRE_INOUT => ONEWIRE, REGIO_ONEWIRE_MONITOR_IN => '0', + REGIO_ONEWIRE_MONITOR_OUT => open, TRIGGER_MONITOR_IN => trigger_monitor, GLOBAL_TIME_OUT => global_time, @@ -336,45 +401,7 @@ begin STAT_ADDR_DEBUG => open ); ---------------------------------------------------------------------- --- LVL1 handler ---------------------------------------------------------------------- --- LVL1_ERROR_PATTERN_IN <= (others => '0'); --- LVL1_TRG_RELEASE_IN <= '1'; - ---------------------------------------------------------------------- --- IPU Data channel handler ---------------------------------------------------------------------- - --- IPU_LENGTH_IN <= x"0005"; --- IPU_ERROR_PATTERN_IN <= (others => '0'); - --- process(CLK_100) --- begin --- if rising_edge(CLK_100) then --- IPU_READOUT_FINISHED_IN <= '0'; --- ipu_counter <= ipu_counter; --- IPU_DATAREADY_IN <= '0'; --- if IPU_START_READOUT_OUT = '1' then --- IPU_DATAREADY_IN <= IPU_DATAREADY_IN; --- if IPU_DATAREADY_IN = '0' and IPU_READOUT_FINISHED_IN = '0' then --- ipu_counter <= ipu_counter + 1; --- IPU_DATAREADY_IN <= '1'; --- elsif IPU_DATAREADY_IN = '1' and IPU_READ_OUT = '1' then --- IPU_DATAREADY_IN <= '0'; --- end if; --- if ipu_counter = x"5" or IPU_READOUT_FINISHED_IN = '1' then --- ipu_counter <= (others => '0'); --- IPU_DATAREADY_IN <= '0'; --- IPU_READOUT_FINISHED_IN <= '1'; --- end if; --- else --- ipu_counter <= (others => '0'); --- end if; --- end if; --- end process; --- IPU_DATA_IN(15 downto 0) <= std_logic_vector(ipu_counter); --- IPU_DATA_IN(31 downto 16) <= std_logic_vector(0 - unsigned(ipu_counter)); + trigger_monitor <= '0'; --------------------------------------------------------------------- -- SlowControl Handler @@ -393,10 +420,9 @@ begin -- Memory map: -- full range: 8000 - FFFF --- 8000 - 80FF ADC (17) --- 9000 - 9FFF SPI --- A000 - A0FF Threshold Bytes (16) --- F000 - F00F Test readout addresses (15-0) +-- 8000 - 80FF ADC (1) +-- D000 - D13F SPI (2-3) +-- A000 - A0FF Threshold Bytes (0) THE_REG_DAT_ADDR : process(CLK_100) @@ -415,9 +441,11 @@ THE_REG_DAT_ADDR : process(CLK_100) THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"9000", others => x"0000"), - PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 8, others => 0) + PORT_NUMBER => 5, +-- PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"9000", others => x"0000"), +-- PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 8, others => 0) + PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"9000", others => x"0000"), + PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 1, 3 => 6, 4 => 0, others => 0) ) port map( CLK => CLK_100, @@ -433,11 +461,13 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_IN, DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_IN, DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_IN, - --Bus Handler input on first port (Threshold memory) + --Bus Handler (Threshold memory) BUS_READ_ENABLE_OUT(0) => thresh_mem_read, BUS_WRITE_ENABLE_OUT(0) => thresh_mem_write, BUS_DATA_OUT(0*32+15 downto 0*32) => thresh_mem_data, + BUS_DATA_OUT(0*32+31 downto 0*32+16)=> open, BUS_ADDR_OUT(0*16+8 downto 0*16) => thresh_mem_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open, BUS_TIMEOUT_OUT(0) => open, BUS_DATA_IN(0*32+15 downto 0*32) => thresh_mem_data_out, BUS_DATA_IN(0*32+31 downto 0*32+16) => x"0000", @@ -445,75 +475,166 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler BUS_WRITE_ACK_IN(0) => reg_REGIO_WRITE, BUS_NO_MORE_DATA_IN(0) => '0', BUS_UNKNOWN_ADDR_IN(0) => '0', - --Bus Handler input on second port (ADC) - BUS_READ_ENABLE_OUT(1) => adc_read, - BUS_WRITE_ENABLE_OUT(1) => adc_write, - BUS_DATA_OUT(1*32+31 downto 1*32) => adc_data_in, - BUS_ADDR_OUT(1*16+5 downto 1*16) => adc_addr, - BUS_TIMEOUT_OUT(1) => adc_timeout, - BUS_DATA_IN(1*32+31 downto 1*32) => adc_data_out, - BUS_DATAREADY_IN(1) => adc_dataready, - BUS_WRITE_ACK_IN(1) => adc_write_ack, - BUS_NO_MORE_DATA_IN(1) => adc_no_more_data, - BUS_UNKNOWN_ADDR_IN(1) => adc_unknown_addr, ---Bus Handler input on third port (SPI-FLASH) - BUS_READ_ENABLE_OUT(2) => flash_mem_read, - BUS_WRITE_ENABLE_OUT(2) => flash_mem_write, - BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data, - BUS_ADDR_OUT(2*16+8 downto 2*16) => flash_mem_addr, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(2*32+31 downto 2*32) => flash_mem_data_out, - BUS_DATAREADY_IN(2) => very_last_reg_REGIO_READ, - BUS_WRITE_ACK_IN(2) => reg_REGIO_WRITE, - BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => '0', + --Bus Handler (ADC) + BUS_READ_ENABLE_OUT(1) => adc_read, + BUS_WRITE_ENABLE_OUT(1) => adc_write, + BUS_DATA_OUT(1*32+31 downto 1*32) => adc_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => adc_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(1) => adc_timeout, + BUS_DATA_IN(1*32+31 downto 1*32) => adc_data_out, + BUS_DATAREADY_IN(1) => adc_dataready, + BUS_WRITE_ACK_IN(1) => adc_write_ack, + BUS_NO_MORE_DATA_IN(1) => adc_no_more_data, + BUS_UNKNOWN_ADDR_IN(1) => adc_unknown_addr, +-- --Bus Handler (SPI-FLASH) +-- BUS_READ_ENABLE_OUT(2) => flash_mem_read, +-- BUS_WRITE_ENABLE_OUT(2) => flash_mem_write, +-- BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data, +-- BUS_ADDR_OUT(2*16+8 downto 2*16) => flash_mem_addr, +-- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open, +-- BUS_TIMEOUT_OUT(2) => open, +-- BUS_DATA_IN(2*32+31 downto 2*32) => flash_mem_data_out, +-- BUS_DATAREADY_IN(2) => very_last_reg_REGIO_READ, +-- BUS_WRITE_ACK_IN(2) => reg_REGIO_WRITE, +-- BUS_NO_MORE_DATA_IN(2) => '0', +-- BUS_UNKNOWN_ADDR_IN(2) => '0', + --Bus Handler (SPI CTRL) + BUS_READ_ENABLE_OUT(2) => spictrl_read_en, + BUS_WRITE_ENABLE_OUT(2) => spictrl_write_en, + BUS_DATA_OUT(2*32+31 downto 2*32) => spictrl_data_in, + BUS_ADDR_OUT(2*16) => spictrl_addr, + BUS_ADDR_OUT(2*16+15 downto 2*16+1) => open, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(2*32+31 downto 2*32) => spictrl_data_out, + BUS_DATAREADY_IN(2) => spictrl_ack, + BUS_WRITE_ACK_IN(2) => spictrl_ack, + BUS_NO_MORE_DATA_IN(2) => spictrl_busy, + BUS_UNKNOWN_ADDR_IN(2) => '0', + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(3) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(3) => spimem_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => spimem_data_in, + BUS_ADDR_OUT(3*16+5 downto 3*16) => spimem_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+6) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => spimem_data_out, + BUS_DATAREADY_IN(3) => spimem_ack, + BUS_WRITE_ACK_IN(3) => spimem_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + --Flash ROM select + BUS_READ_ENABLE_OUT(4) => flash_rom_read, + BUS_WRITE_ENABLE_OUT(4) => flash_rom_write, + BUS_DATA_OUT(4*32) => next_flash_rom_select, + BUS_DATA_OUT(4*32+31 downto 4*32+1) => open, + BUS_ADDR_OUT(4*16+15 downto 4*16) => open, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(4*32) => flash_rom_select, + BUS_DATA_IN(4*32+31 downto 4*32+1) => (others => '0'), + BUS_DATAREADY_IN(4) => flash_rom_read, + BUS_WRITE_ACK_IN(4) => flash_rom_write, + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => '0', --Debugging STAT_DEBUG => open ); + + ------------------------------------------------------------------------------- -- SPI ------------------------------------------------------------------------------- - process(CLK_100) - begin - if rising_edge(CLK_100) then - flash_mem_data_out <= (others => '0'); +-- process(CLK_100) +-- begin +-- if rising_edge(CLK_100) then +-- flash_mem_data_out <= (others => '0'); +-- +-- if (flash_mem_addr(3 downto 0) = x"0") then +-- write_cmd_register_in <= flash_mem_write; +-- flash_mem_data_out <= cmd_register_in; +-- +-- elsif (flash_mem_addr(3 downto 0) = x"1") then +-- write_ctrl_register <= flash_mem_write; +-- flash_mem_data_out <= ctrl_register; +-- else +-- cmd_register_in <= cmd_register_in; +-- ctrl_register <= ctrl_register; +-- end if; +-- end if; +-- end process; +-- +-- process(CLK_100) +-- begin +-- if rising_edge(CLK_100) then +-- if (write_cmd_register_in = '1') then +-- cmd_register_in <= flash_mem_data; +-- else +-- cmd_register_in <= cmd_register_in; +-- end if; +-- end if; +-- end process; +-- +-- process(CLK_100) +-- begin +-- if rising_edge(CLK_100) then +-- if (write_ctrl_register = '1') then +-- ctrl_register <= flash_mem_data; +-- else +-- ctrl_register <= ctrl_register; +-- end if; +-- end if; +-- end process; - if (flash_mem_addr(3 downto 0) = x"0") then - write_cmd_register_in <= flash_mem_write; - flash_mem_data_out <= cmd_register_in; + THE_SPI_MASTER: spi_master + port map( + CLK_IN => CLK_100, + RESET_IN => reset_internal, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => SPI_CS, + SPI_SDI_IN => SPI_DIN, + SPI_SDO_OUT => SPI_DOUT, + SPI_SCK_OUT => SPI_CLK, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => open + ); + + -- data memory for SPI accesses + THE_SPI_MEMORY: spi_databus_memory + port map( + CLK_IN => CLK_100, + RESET_IN => reset_internal, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); - elsif (flash_mem_addr(3 downto 0) = x"1") then - write_ctrl_register <= flash_mem_write; - flash_mem_data_out <= ctrl_register; - else - cmd_register_in <= cmd_register_in; - ctrl_register <= ctrl_register; - end if; - end if; - end process; - process(CLK_100) - begin - if rising_edge(CLK_100) then - if (write_cmd_register_in = '1') then - cmd_register_in <= flash_mem_data; - else - cmd_register_in <= cmd_register_in; - end if; - end if; - end process; - process(CLK_100) - begin - if rising_edge(CLK_100) then - if (write_ctrl_register = '1') then - ctrl_register <= flash_mem_data; - else - ctrl_register <= ctrl_register; - end if; - end if; - end process; --------------------------------------------------------------------- -- ADC --------------------------------------------------------------------- @@ -574,7 +695,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler STAT_OP => MED_STAT_OP, CTRL_OP => MED_CTRL_OP, STAT_DEBUG => MED_STAT_DEBUG, - CTRL_DEBUG => MED_CTRL_DEBUG + CTRL_DEBUG => (others => '0') ); --------------------------------------------------------------------- @@ -590,12 +711,13 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler -- 0xc0 0xABC2000 -> x"ABC" test data number -- 0xc0 0x10000000 -> x"1" external cms --- 0xc0 0x00000000 -> x"0" internal generated cms +-- 0xc0 0x00000000 -> x"0" internal generated cms + ------------------------------------------------------------------------------- -- Select Internal or external common stop -------------------------------------------------------------------------------- -CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; +------------------------------------------------------------------------------- +CMS <= COM_STOP_P when (cms_select_in_i = x"1") else a_cms_i; -- 0xc0 0xABCD2000 -> x"ABCD" test data number @@ -612,10 +734,8 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; end process; --- <= REGIO_REGISTERS_OUT(32); --bit 0 of 0xc1 --- REGIO_REGISTERS_OUT(64); --bit 0 of 0xc2 multiply --- - + + PULSE_TRIGGER : edge_to_pulse port map ( CLOCK => CLK_100, @@ -790,7 +910,7 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; end if; end if; end process; - + ------------------------------------------------------------------------------- -- pin not used input for fpga ------------------------------------------------------------------------------- @@ -877,7 +997,7 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; -- generic map(width => 10) -- port map ( -- CLK => CLK_100, --- ad => input_parity_gen, +-- ad => input_parity_gen, -- oddParity => D(4) -- ); @@ -907,7 +1027,7 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; -- end generate; --counter_data_conv <= conv_std_logic_vector(counter_data); - + -- D(4) <= data_out(1)(5) and data_out(2)(15);-- and data_out(3)(16); -- process(CLK_100, reset_internal) @@ -921,7 +1041,7 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; -- counter_data <= counter_data; -- end if; -- end if; --- end process; +-- end process; -- SHIFT_TEST : for i in 1 to 2999 generate @@ -944,7 +1064,7 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; -- Output => out_shift_reg1, -- Input => cal_trigger_register_in_i(3 downto 0)); - + -- process(CLK_100) -- begin -- if rising_edge(CLK_100) then @@ -961,8 +1081,8 @@ CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i; -- D(3) <= temp_led1; -- D(2) <= temp_led2; -- D(1) <= temp_led3; - - - + + + end architecture; -- 2.43.0