From 81044114f65af230765491d6959aca42af64fcd9 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 18 Nov 2021 15:11:03 +0100 Subject: [PATCH] cleanup --- media_interfaces/sync/med_sync_control_RS.vhd | 527 +++++++++--------- media_interfaces/sync/rx_control_RS.vhd | 78 ++- media_interfaces/sync/rx_reset_fsm_RS.vhd | 265 ++++----- media_interfaces/sync/tx_control_RS.vhd | 19 +- media_interfaces/sync/tx_reset_fsm_RS.vhd | 257 ++++----- 5 files changed, 584 insertions(+), 562 deletions(-) diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index c892598..e566c98 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -51,351 +51,346 @@ entity med_sync_control_RS is RX_DLM_WORD : out std_logic_vector(7 downto 0); RX_DLM : out std_logic; - SERDES_RX_READY_IN : in std_logic := '1'; - SERDES_TX_READY_IN : in std_logic := '1'; - - STAT_TX_CONTROL : out std_logic_vector(31 downto 0); - STAT_RX_CONTROL : out std_logic_vector(31 downto 0); - DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); - DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); - STAT_RESET : out std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) + SERDES_RX_READY_IN : in std_logic; + SERDES_TX_READY_IN : in std_logic; + + STAT_TX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); + DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); + STAT_RESET : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; architecture med_sync_control_arch of med_sync_control_RS is -signal rx_fsm_state : std_logic_vector(3 downto 0); -signal tx_fsm_state : std_logic_vector(3 downto 0); -signal wa_position_rx : std_logic_vector(3 downto 0); -signal start_timer : unsigned(21 downto 0) := (others => '0'); + signal rx_fsm_state : std_logic_vector(3 downto 0); + signal tx_fsm_state : std_logic_vector(3 downto 0); + signal wa_position_rx : std_logic_vector(3 downto 0); + signal start_timer : unsigned(21 downto 0) := (others => '0'); -signal request_retr_i : std_logic; -signal start_retr_i : std_logic; -signal request_retr_position_i : std_logic_vector(7 downto 0); -signal start_retr_position_i : std_logic_vector(7 downto 0); -signal rx_dlm_i : std_logic; + signal request_retr_i : std_logic; + signal start_retr_i : std_logic; + signal request_retr_position_i : std_logic_vector(7 downto 0); + signal start_retr_position_i : std_logic_vector(7 downto 0); + signal rx_dlm_i : std_logic; -signal led_ok : std_logic; -signal led_dlm, last_led_dlm : std_logic; -signal led_rx, last_led_rx : std_logic; -signal led_tx, last_led_tx : std_logic; -signal timer : unsigned(20 downto 0); -signal sd_los_i : std_logic; + signal led_ok : std_logic; + signal led_dlm, last_led_dlm : std_logic; + signal led_rx, last_led_rx : std_logic; + signal led_tx, last_led_tx : std_logic; + signal timer : unsigned(20 downto 0); + signal sd_los_i : std_logic; -signal rx_allow : std_logic; -signal tx_allow : std_logic; -signal got_link_ready_i : std_logic; + signal rx_allow : std_logic; + signal tx_allow : std_logic; + signal got_link_ready_i : std_logic; -signal reset_i : std_logic; -signal rst_n : std_logic; -signal rst_n_tx : std_logic; -signal finished_reset_rx : std_logic; -signal finished_reset_rx_q : std_logic; -signal finished_reset_tx : std_logic; -signal finished_reset_tx_q : std_logic; + signal reset_i : std_logic; + signal rst_n : std_logic; + signal rst_n_tx : std_logic; + signal finished_reset_rx : std_logic; + signal finished_reset_rx_q : std_logic; + signal finished_reset_tx : std_logic; + signal finished_reset_tx_q : std_logic; -signal media_med2int_i : MED2INT; + signal media_med2int_i : MED2INT; -signal rx_serdes_rst_i : std_logic; -signal rx_pcs_rst_i : std_logic; + signal rx_serdes_rst_i : std_logic; + signal rx_pcs_rst_i : std_logic; -signal rx_serdes_rst_i_q : std_logic_vector(2 downto 0); -signal rx_pcs_rst_i_q : std_logic_vector(2 downto 0); + signal rx_serdes_rst_i_q : std_logic_vector(2 downto 0); + signal rx_pcs_rst_i_q : std_logic_vector(2 downto 0); -signal tx_pcs_rst_i : std_logic; -signal quad_rst_i : std_logic; + signal tx_pcs_rst_i : std_logic; + signal quad_rst_i : std_logic; -signal wap_is_zero_i : std_logic; -signal rx_reset_finished_i : std_logic; -signal tx_k_i : std_logic; + signal wap_is_zero_i : std_logic; + signal rx_reset_finished_i : std_logic; + signal tx_k_i : std_logic; -signal debug_tx_control_i : std_logic_vector(31 downto 0); ---signal debug_rx_control_i : std_logic_vector(31 downto 0); + signal debug_tx_control_i : std_logic_vector(31 downto 0); +-- signal debug_rx_control_i : std_logic_vector(31 downto 0); begin - -- synchronize SFP LOS signal -sd_los_i <= SFP_LOS when rising_edge(CLK_SYS); + sd_los_i <= SFP_LOS when rising_edge(CLK_SYS); -- TX_RESET_FSM reset ---rst_n_tx <= not (CLEAR or sd_los_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) --- else not (CLEAR or RESET); -rst_n_tx <= not (CLEAR or sd_los_i or RESET) when (IS_MODE = c_IS_SLAVE) - else not (CLEAR or RESET); + --rst_n_tx <= not (CLEAR or sd_los_i or RESET) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) + -- else not (CLEAR or RESET); + rst_n_tx <= not (CLEAR or sd_los_i or RESET) when (IS_MODE = c_IS_SLAVE) + else not (CLEAR or RESET); -- RX_RESET_FSM reset -rst_n <= not (CLEAR or sd_los_i or RESET); + rst_n <= not (CLEAR or sd_los_i or RESET); -- TX_CONTROL and RX_CONTROL reset -reset_i <= (RESET or sd_los_i); + reset_i <= (RESET or sd_los_i); -- clocks for media interface -media_med2int_i.clk_half <= CLK_RXHALF; -media_med2int_i.clk_full <= CLK_RXI; + media_med2int_i.clk_half <= CLK_RXHALF; + media_med2int_i.clk_full <= CLK_RXI; ------------------------------------------------- -- Reset RX FSM ------------------------------------------------- -THE_RX_FSM : rx_reset_fsm_RS - port map( - RST_N => rst_n, - RX_REFCLK => CLK_REF, - TX_PLL_LOL_QD_S => '0', --TX_LOL, -- we don't use this one - RX_CDR_LOL_CH_S => RX_CDR_LOL, - RX_LOS_LOW_CH_S => RX_LOS, - RX_PCS_RST_CH_C => rx_pcs_rst_i, - RX_SERDES_RST_CH_C => rx_serdes_rst_i, - WA_POSITION => wa_position_rx, - NORMAL_OPERATION_OUT => finished_reset_rx, - STATE_OUT => rx_fsm_state - ); + THE_RX_FSM : rx_reset_fsm_RS + port map( + RST_N => rst_n, + RX_REFCLK => CLK_REF, + TX_PLL_LOL_QD_S => '0', --TX_LOL, -- we don't use this one + RX_CDR_LOL_CH_S => RX_CDR_LOL, + RX_LOS_LOW_CH_S => RX_LOS, + RX_PCS_RST_CH_C => rx_pcs_rst_i, + RX_SERDES_RST_CH_C => rx_serdes_rst_i, + WA_POSITION => wa_position_rx, + NORMAL_OPERATION_OUT => finished_reset_rx, + STATE_OUT => rx_fsm_state + ); -- crossing the abbyss -THE_ABBYSS_PROC: process( CLK_RXI ) -begin - if( rising_edge(CLK_RXI) ) then - rx_serdes_rst_i_q <= rx_serdes_rst_i_q(1 downto 0) & rx_serdes_rst_i; - rx_pcs_rst_i_q <= rx_pcs_rst_i_q(1 downto 0) & rx_pcs_rst_i; - end if; -end process THE_ABBYSS_PROC; + THE_ABBYSS_PROC: process( CLK_RXI ) + begin + if( rising_edge(CLK_RXI) ) then + rx_serdes_rst_i_q <= rx_serdes_rst_i_q(1 downto 0) & rx_serdes_rst_i; + rx_pcs_rst_i_q <= rx_pcs_rst_i_q(1 downto 0) & rx_pcs_rst_i; + end if; + end process THE_ABBYSS_PROC; -- Reset signals must be syncronous to CLK_RXI -RX_SERDES_RST <= rx_serdes_rst_i_q(2); -RX_PCS_RST <= rx_pcs_rst_i_q(2); + RX_SERDES_RST <= rx_serdes_rst_i_q(2); + RX_PCS_RST <= rx_pcs_rst_i_q(2); -- sync WAP to CLK_REF, the SCI reader usually runs on CLK_SYS! -SYNC_WA_POSITION_PROC: process( CLK_REF ) -begin - if( rising_edge(CLK_REF) ) then - if IS_WAP_ZERO = 1 then - wa_position_rx <= WA_POSITION; - else - wa_position_rx <= x"0"; + SYNC_WA_POSITION_PROC: process( CLK_REF ) + begin + if( rising_edge(CLK_REF) ) then + if IS_WAP_ZERO = 1 then + wa_position_rx <= WA_POSITION; + else + wa_position_rx <= x"0"; + end if; end if; - end if; -end process SYNC_WA_POSITION_PROC; + end process SYNC_WA_POSITION_PROC; -rx_reset_finished_i <= finished_reset_rx when (IS_MODE = c_IS_SLAVE) else '1'; + rx_reset_finished_i <= finished_reset_rx when (IS_MODE = c_IS_SLAVE) else '1'; ------------------------------------------------- -- Reset TX FSM ------------------------------------------------- -THE_TX_FSM : tx_reset_fsm_RS - port map( - RST_N => rst_n_tx, - TX_REFCLK => CLK_REF, - TX_PLL_LOL_QD_S => TX_LOL, - RX_RESET_FINISHED_IN => rx_reset_finished_i, - RST_QD_C => quad_rst_i, - TX_PCS_RST_CH_C => tx_pcs_rst_i, - NORMAL_OPERATION_OUT => finished_reset_tx, - STATE_OUT => tx_fsm_state - ); + THE_TX_FSM: tx_reset_fsm_RS + port map( + RST_N => rst_n_tx, + TX_REFCLK => CLK_REF, + TX_PLL_LOL_QD_S => TX_LOL, + RX_RESET_FINISHED_IN => rx_reset_finished_i, + RST_QD_C => quad_rst_i, + TX_PCS_RST_CH_C => tx_pcs_rst_i, + NORMAL_OPERATION_OUT => finished_reset_tx, + STATE_OUT => tx_fsm_state + ); -- may also need sync? -TX_PCS_RST <= tx_pcs_rst_i; -QUAD_RST <= quad_rst_i; + TX_PCS_RST <= tx_pcs_rst_i; + QUAD_RST <= quad_rst_i; ------------------------------------------------- -- RX & TX allow ------------------------------------------------- -- Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable -PROC_ALLOW : process begin - wait until rising_edge(CLK_SYS); - if( (finished_reset_rx_q = '1') - and ((IS_MODE = c_IS_MASTER) or (start_timer(start_timer'left) = '1')) ) then - rx_allow <= '1'; - else - rx_allow <= '0'; - end if; - if( (finished_reset_tx_q = '1' and finished_reset_rx_q = '1') - and ((IS_MODE = c_IS_MASTER) or (start_timer(start_timer'left) = '1')) ) then - tx_allow <= '1'; - else - tx_allow <= '0'; - end if; -end process; - -LINK_RESET_FIN_TX: signal_sync - port map( - RESET => '0', - CLK0 => CLK_SYS, - CLK1 => CLK_SYS, - D_IN(0) => finished_reset_tx, - D_OUT(0) => finished_reset_tx_q - ); - -LINK_RESET_FIN_RX: signal_sync - port map( - RESET => '0', - CLK0 => CLK_SYS, - CLK1 => CLK_SYS, - D_IN(0) => finished_reset_rx, - D_OUT(0) => finished_reset_rx_q - ); - -START_TIMER_PROC : process( CLK_SYS ) -begin - if( rising_edge(CLK_SYS) ) then --- if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') ) then --- if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') and (got_link_ready_i = '1' or IS_SYNC_SLAVE = 1) ) then - if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') and (got_link_ready_i = '1' or IS_MODE = c_IS_SLAVE) ) then - if start_timer(start_timer'left) = '0' then - start_timer <= start_timer + 1; - end if; + PROC_ALLOW: process begin + wait until rising_edge(CLK_SYS); + if( (finished_reset_rx_q = '1') + and ((IS_MODE = c_IS_MASTER) or (start_timer(start_timer'left) = '1')) ) then + rx_allow <= '1'; + else + rx_allow <= '0'; + end if; + if( (finished_reset_tx_q = '1' and finished_reset_rx_q = '1') + and ((IS_MODE = c_IS_MASTER) or (start_timer(start_timer'left) = '1')) ) then + tx_allow <= '1'; else - start_timer <= (others => '0'); + tx_allow <= '0'; end if; - end if; -end process START_TIMER_PROC; + end process PROC_ALLOW; + + LINK_RESET_FIN_TX: signal_sync + port map( + RESET => '0', + CLK0 => CLK_SYS, + CLK1 => CLK_SYS, + D_IN(0) => finished_reset_tx, + D_OUT(0) => finished_reset_tx_q + ); + + LINK_RESET_FIN_RX: signal_sync + port map( + RESET => '0', + CLK0 => CLK_SYS, + CLK1 => CLK_SYS, + D_IN(0) => finished_reset_rx, + D_OUT(0) => finished_reset_rx_q + ); + + START_TIMER_PROC: process( CLK_SYS ) + begin + if( rising_edge(CLK_SYS) ) then +-- if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') ) then +-- if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') and (got_link_ready_i = '1' or IS_SYNC_SLAVE = 1) ) then + if( (finished_reset_tx_q = '1') and (finished_reset_rx_q = '1') and (got_link_ready_i = '1' or IS_MODE = c_IS_SLAVE) ) then + if start_timer(start_timer'left) = '0' then + start_timer <= start_timer + 1; + end if; + else + start_timer <= (others => '0'); + end if; + end if; + end process START_TIMER_PROC; ------------------------------------------------- -- TX Data -------------------------------------------------- -THE_TX : tx_control_RS - port map( - CLK_200 => CLK_TXI, - CLK_100 => CLK_SYS, - RESET_IN => reset_i, - - WORD_SYNC_IN => WORD_SYNC_IN, - - TX_DATA_IN => MEDIA_INT2MED.data, - TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, - TX_WRITE_IN => MEDIA_INT2MED.dataready, - TX_READ_OUT => media_med2int_i.tx_read, - - TX_DATA_OUT => TX_DATA, - TX_K_OUT => tx_k_i, --TX_K, - TX_CD_OUT => TX_CD, - - SEND_DLM => TX_DLM, - SEND_DLM_WORD => TX_DLM_WORD, +------------------------------------------------- + THE_TX : tx_control_RS + port map( + CLK_200 => CLK_TXI, + CLK_100 => CLK_SYS, + RESET_IN => reset_i, + + WORD_SYNC_IN => WORD_SYNC_IN, + + TX_DATA_IN => MEDIA_INT2MED.data, + TX_PACKET_NUMBER_IN => MEDIA_INT2MED.packet_num, + TX_WRITE_IN => MEDIA_INT2MED.dataready, + TX_READ_OUT => media_med2int_i.tx_read, + + TX_DATA_OUT => TX_DATA, + TX_K_OUT => tx_k_i, --TX_K, + TX_CD_OUT => TX_CD, + + SEND_DLM => TX_DLM, + SEND_DLM_WORD => TX_DLM_WORD, - TX_ALLOW_IN => tx_allow, - RX_ALLOW_IN => rx_allow, + TX_ALLOW_IN => tx_allow, + RX_ALLOW_IN => rx_allow, - DEBUG_OUT => debug_tx_control_i, --DEBUG_TX_CONTROL, - STAT_REG_OUT => STAT_TX_CONTROL - ); + DEBUG_OUT => debug_tx_control_i, --DEBUG_TX_CONTROL, + STAT_REG_OUT => STAT_TX_CONTROL + ); -TX_K <= tx_k_i; + TX_K <= tx_k_i; ------------------------------------------------- -- RX Data ------------------------------------------------- -THE_RX_CONTROL : rx_control_RS - port map( - CLK_200 => CLK_RXI, - CLK_100 => CLK_SYS, - RESET_IN => reset_i, + THE_RX_CONTROL : rx_control_RS + port map( + CLK_200 => CLK_RXI, + CLK_100 => CLK_SYS, + RESET_IN => reset_i, - WORD_SYNC_OUT => WORD_SYNC_OUT, + WORD_SYNC_OUT => WORD_SYNC_OUT, - RX_DATA_OUT => media_med2int_i.data, - RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, - RX_WRITE_OUT => media_med2int_i.dataready, + RX_DATA_OUT => media_med2int_i.data, + RX_PACKET_NUMBER_OUT => media_med2int_i.packet_num, + RX_WRITE_OUT => media_med2int_i.dataready, - RX_DATA_IN => RX_DATA, - RX_K_IN => RX_K, + RX_DATA_IN => RX_DATA, + RX_K_IN => RX_K, - RX_DLM => rx_dlm_i, - RX_DLM_WORD => RX_DLM_WORD, + RX_DLM => rx_dlm_i, + RX_DLM_WORD => RX_DLM_WORD, - RX_ALLOW_IN => rx_allow, - RX_RESET_FINISHED => finished_reset_rx, - GOT_LINK_READY => got_link_ready_i, + RX_ALLOW_IN => rx_allow, + RX_RESET_FINISHED => finished_reset_rx, + GOT_LINK_READY => got_link_ready_i, - DEBUG_OUT => DEBUG_RX_CONTROL, - STAT_REG_OUT => STAT_RX_CONTROL - ); + DEBUG_OUT => DEBUG_RX_CONTROL, + STAT_REG_OUT => STAT_RX_CONTROL + ); -RX_DLM <= rx_dlm_i; -MEDIA_MED2INT <= media_med2int_i; + RX_DLM <= rx_dlm_i; + MEDIA_MED2INT <= media_med2int_i; ------------------------------------------------- -- Generate LED signals ------------------------------------------------- -led_ok <= rx_allow and tx_allow when rising_edge(CLK_SYS); -led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); -led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS); -led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS); - -ROC_TIMER_PROC: process( CLK_SYS ) -begin - if( rising_edge(CLK_SYS) ) then - timer <= timer + 1 ; - if timer(20) = '1' then - timer <= (others => '0'); - last_led_rx <= led_rx ; - last_led_tx <= led_tx; - last_led_dlm <= led_dlm; + led_ok <= rx_allow and tx_allow when rising_edge(CLK_SYS); + led_rx <= (media_med2int_i.dataready or led_rx) and not timer(20) when rising_edge(CLK_SYS); + led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i) and not timer(20) when rising_edge(CLK_SYS); + led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS); + + ROC_TIMER_PROC: process( CLK_SYS ) + begin + if( rising_edge(CLK_SYS) ) then + timer <= timer + 1 ; + if timer(20) = '1' then + timer <= (others => '0'); + last_led_rx <= led_rx ; + last_led_tx <= led_tx; + last_led_dlm <= led_dlm; + end if; end if; - end if; -end process ROC_TIMER_PROC; + end process ROC_TIMER_PROC; ------------------------------------------------- -- Status signals ------------------------------------------------- - -STAT_RESET(3 downto 0) <= rx_fsm_state; -STAT_RESET(7 downto 4) <= tx_fsm_state; -STAT_RESET(8) <= tx_allow; -STAT_RESET(9) <= rx_allow; -STAT_RESET(15 downto 10) <= (others => '0'); -STAT_RESET(16) <= RX_CDR_LOL; -STAT_RESET(17) <= RX_LOS; -STAT_RESET(18) <= '0'; -STAT_RESET(19) <= '0'; -STAT_RESET(20) <= TX_LOL; -STAT_RESET(21) <= rst_n; -STAT_RESET(22) <= rst_n_tx; -STAT_RESET(30 downto 23) <= (others => '0'); -STAT_RESET(31) <= start_timer(start_timer'left); - -media_med2int_i.stat_op(15) <= '0'; -media_med2int_i.stat_op(14) <= '0'; -media_med2int_i.stat_op(13) <= '0'; --make trbnet reset -media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm; -media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx; -media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -media_med2int_i.stat_op(9) <= tx_allow; --led_ok -media_med2int_i.stat_op(8 downto 5) <= (others => '0'); -media_med2int_i.stat_op(4) <= rx_allow; -media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7"; - -wap_is_zero_i <= '1' when WA_POSITION = x"0" else '0'; + STAT_RESET(3 downto 0) <= rx_fsm_state; + STAT_RESET(7 downto 4) <= tx_fsm_state; + STAT_RESET(8) <= tx_allow; + STAT_RESET(9) <= rx_allow; + STAT_RESET(15 downto 10) <= (others => '0'); + STAT_RESET(16) <= RX_CDR_LOL; + STAT_RESET(17) <= RX_LOS; + STAT_RESET(18) <= '0'; + STAT_RESET(19) <= '0'; + STAT_RESET(20) <= TX_LOL; + STAT_RESET(21) <= rst_n; + STAT_RESET(22) <= rst_n_tx; + STAT_RESET(30 downto 23) <= (others => '0'); + STAT_RESET(31) <= start_timer(start_timer'left); + + media_med2int_i.stat_op(15) <= '0'; + media_med2int_i.stat_op(14) <= '0'; + media_med2int_i.stat_op(13) <= '0'; --make trbnet reset + media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm; + media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx; + media_med2int_i.stat_op(10) <= led_rx or last_led_rx; + media_med2int_i.stat_op(9) <= tx_allow; --led_ok + media_med2int_i.stat_op(8 downto 5) <= (others => '0'); + media_med2int_i.stat_op(4) <= rx_allow; + media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7"; + + wap_is_zero_i <= '1' when WA_POSITION = x"0" else '0'; -- TEST_LINE signals -DEBUG_OUT(0) <= TX_LOL; -DEBUG_OUT(1) <= RX_CDR_LOL; -DEBUG_OUT(2) <= RX_LOS; -DEBUG_OUT(3) <= rst_n; -DEBUG_OUT(4) <= rst_n_tx; -DEBUG_OUT(5) <= quad_rst_i; -DEBUG_OUT(6) <= rx_pcs_rst_i; -DEBUG_OUT(7) <= tx_pcs_rst_i; -DEBUG_OUT(8) <= rx_serdes_rst_i; -DEBUG_OUT(9) <= finished_reset_rx; -DEBUG_OUT(10) <= finished_reset_tx; -DEBUG_OUT(11) <= '0'; -DEBUG_OUT(12) <= '0'; -DEBUG_OUT(13) <= got_link_ready_i; -DEBUG_OUT(14) <= rx_allow; -DEBUG_OUT(15) <= tx_allow; --- not used - -DEBUG_OUT(25 downto 16) <= (others => '0'); - -DEBUG_OUT(26) <= wap_is_zero_i; -DEBUG_OUT(27) <= rx_dlm_i; -DEBUG_OUT(28) <= debug_tx_control_i(29); -- send_reset -DEBUG_OUT(29) <= got_link_ready_i; --tx_k_i; -DEBUG_OUT(30) <= debug_tx_control_i(30); -- send_dlm_i -DEBUG_OUT(31) <= debug_tx_control_i(31); -- sending_dlm - -DEBUG_TX_CONTROL <= debug_tx_control_i; + DEBUG_OUT(0) <= TX_LOL; + DEBUG_OUT(1) <= RX_CDR_LOL; + DEBUG_OUT(2) <= RX_LOS; + DEBUG_OUT(3) <= rst_n; + DEBUG_OUT(4) <= rst_n_tx; + DEBUG_OUT(5) <= quad_rst_i; + DEBUG_OUT(6) <= rx_pcs_rst_i; + DEBUG_OUT(7) <= tx_pcs_rst_i; + DEBUG_OUT(8) <= rx_serdes_rst_i; + DEBUG_OUT(9) <= finished_reset_rx; + DEBUG_OUT(10) <= finished_reset_tx; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(12) <= '0'; + DEBUG_OUT(13) <= got_link_ready_i; + DEBUG_OUT(14) <= rx_allow; + DEBUG_OUT(15) <= tx_allow; + DEBUG_OUT(25 downto 16) <= (others => '0'); + DEBUG_OUT(26) <= wap_is_zero_i; + DEBUG_OUT(27) <= rx_dlm_i; + DEBUG_OUT(28) <= debug_tx_control_i(29); -- send_reset + DEBUG_OUT(29) <= got_link_ready_i; --tx_k_i; + DEBUG_OUT(30) <= debug_tx_control_i(30); -- send_dlm_i + DEBUG_OUT(31) <= debug_tx_control_i(31); -- sending_dlm + + DEBUG_TX_CONTROL <= debug_tx_control_i; end architecture; diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 065ea6b..29ebaca 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -13,35 +13,38 @@ entity rx_control_RS is CLK_100 : in std_logic; RESET_IN : in std_logic; - WORD_SYNC_OUT : out std_logic; - ---clk_sys signals + -- CLK_100 signals RX_DATA_OUT : out std_logic_vector(15 downto 0); RX_PACKET_NUMBER_OUT : out std_logic_vector(2 downto 0); RX_WRITE_OUT : out std_logic; --- clk_rx signals - RX_DATA_IN : in std_logic_vector( 7 downto 0); + -- CLK_200 signals + RX_DATA_IN : in std_logic_vector(7 downto 0); RX_K_IN : in std_logic; ---send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM + WORD_SYNC_OUT : out std_logic; + RX_DLM_OUT : out std_logic := '0'; - RX_DLM_WORD_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); + RX_DLM_WORD_OUT : out std_logic_vector(7 downto 0); + + RX_RST_OUT : out std_logic := '0'; + RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); ---other signals - RX_ALLOW_IN : in std_logic := '0'; --clk_sys - RX_RESET_DONE_IN : in std_logic := '0'; --clk_rx - GOT_LINK_READY_OUT : out std_logic := '0'; --clk_rx + -- unknown + RX_ALLOW_IN : in std_logic := '0'; + RX_RESET_DONE_IN : in std_logic := '0'; + GOT_LINK_READY_OUT : out std_logic := '0'; + -- unknown clock DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) - ); + ); end entity; - architecture rx_control_arch of rx_control_RS is -type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM); +type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST); + signal rx_state : rx_state_t; signal rx_state_bits : std_logic_vector(3 downto 0); signal rx_packet_num : std_logic_vector(2 downto 0); @@ -60,9 +63,13 @@ signal last_ct_fifo_read : std_logic; signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; signal got_link_ready_i : std_logic := '0'; + signal rx_dlm_i : std_logic; signal rx_dlm_word_i : std_logic_vector(7 downto 0); +signal rx_rst_i : std_logic; +signal rx_rst_word_i : std_logic_vector(7 downto 0); + signal next_sop : std_logic; signal reg_rx_data_in : std_logic_vector(7 downto 0); @@ -76,11 +83,10 @@ begin -- Data to Endpoint ---------------------------------------------------------------------- -ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; -buf_rx_write_out <= (last_ct_fifo_read and not last_ct_fifo_empty) when rising_edge(CLK_100); +buf_rx_write_out <= (last_ct_fifo_read and not last_ct_fifo_empty) when rising_edge(CLK_100); -RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; RX_WRITE_OUT <= buf_rx_write_out; +RX_DATA_OUT <= ct_fifo_data_out(15 downto 0) ; RX_PACKET_NUMBER_OUT <= rx_packet_num; last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_100); @@ -88,7 +94,7 @@ last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_100); process begin wait until rising_edge(CLK_100); - if RX_ALLOW_IN = '0' then + if RX_ALLOW_IN = '0' then -- DANGEROUS!!!! rx_packet_num <= "100"; elsif buf_rx_write_out = '1' then if rx_packet_num = "100" then @@ -117,6 +123,8 @@ THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg AlmostFull => ct_fifo_afull ); +ct_fifo_read <= not ct_fifo_reset and not ct_fifo_empty; + ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); ---------------------------------------------------------------------- @@ -124,11 +132,12 @@ ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); ---------------------------------------------------------------------- PROC_RX_FSM : process begin wait until rising_edge(CLK_200); - ct_fifo_write <= '0'; - rx_dlm_i <= '0'; + ct_fifo_write <= '0'; + rx_dlm_i <= '0'; + rx_rst_i <= '0'; idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); - idle_hist_i(0) <= got_link_ready_i; - sync_k_i <= '0'; + idle_hist_i(0) <= got_link_ready_i; + sync_k_i <= '0'; case rx_state is when SLEEP => @@ -153,6 +162,8 @@ PROC_RX_FSM : process begin rx_state <= GET_IDLE; when K_DLM => rx_state <= GET_DLM; + when K_RST => + rx_state <= GET_RST; when others => null; end case; else @@ -189,26 +200,36 @@ PROC_RX_FSM : process begin rx_dlm_i <= '1'; rx_dlm_word_i <= reg_rx_data_in; rx_state <= FIRST; + + when GET_RST => + rx_state_bits <= x"6"; + rx_rst_i <= '1'; + rx_rst_word_i <= reg_rx_data_in; + rx_state <= FIRST; end case; if RESET_IN = '1' or RX_RESET_DONE_IN = '0' then - rx_state <= SLEEP; + rx_state <= SLEEP; + rx_dlm_word_i <= x"00"; + rx_rst_word_i <= x"00"; end if; end process; +-- we store incoming data in a register reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_200); reg_rx_k_in <= RX_K_IN when rising_edge(CLK_200); -WORD_SYNC_OUT <= sync_k_i; --reg_rx_k_in; - ---------------------------------------------------------------------- -- Signals out ---------------------------------------------------------------------- GOT_LINK_READY_OUT <= got_link_ready_i; +WORD_SYNC_OUT <= sync_k_i; -RX_DLM_OUT <= rx_dlm_i when rising_edge(CLK_200); -RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_200); +RX_DLM_OUT <= rx_dlm_i when rising_edge(CLK_200); +RX_DLM_WORD_OUT <= rx_dlm_word_i when rising_edge(CLK_200); +RX_RST_OUT <= rx_rst_i when rising_edge(CLK_200); +RX_RST_WORD_OUT <= rx_rst_word_i when rising_edge(CLK_200); ---------------------------------------------------------------------- -- Debug and Status @@ -218,12 +239,11 @@ STAT_REG_OUT(4) <= got_link_ready_i; STAT_REG_OUT(5) <= ct_fifo_afull; STAT_REG_OUT(6) <= ct_fifo_empty; STAT_REG_OUT(7) <= ct_fifo_write; -STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0); +STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(clk_100); STAT_REG_OUT(16) <= rx_data(16); STAT_REG_OUT(17) <= '0'; STAT_REG_OUT(31 downto 18) <= (others => '0'); - DEBUG_OUT(3 downto 0) <= rx_state_bits; DEBUG_OUT(4) <= got_link_ready_i; DEBUG_OUT(5) <= ct_fifo_afull; diff --git a/media_interfaces/sync/rx_reset_fsm_RS.vhd b/media_interfaces/sync/rx_reset_fsm_RS.vhd index a1fcfb5..e852df4 100644 --- a/media_interfaces/sync/rx_reset_fsm_RS.vhd +++ b/media_interfaces/sync/rx_reset_fsm_RS.vhd @@ -21,171 +21,172 @@ end entity ; architecture rx_reset_fsm_arch of rx_reset_fsm_RS is -constant count_index : integer := 19; -type statetype is ( WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, CHECK_WAP, NORMAL ); + constant count_index : integer := 19; + + type statetype is ( WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, CHECK_WAP, NORMAL ); -signal cs : statetype; -- current state of lsm -signal ns : statetype; -- next state of lsm + signal cs : statetype; -- current state of lsm + signal ns : statetype; -- next state of lsm -signal tx_pll_lol_qd_q : std_logic; -signal rx_cdr_lol_ch_q : std_logic; -signal rx_los_low_ch_q : std_logic; -signal rx_lol_los : std_logic; -signal rx_lol_los_int : std_logic; -signal rx_lol_los_del : std_logic; -signal rx_pcs_rst_ch_c_int : std_logic; -signal rx_serdes_rst_ch_c_int : std_logic; + signal tx_pll_lol_qd_q : std_logic; + signal rx_cdr_lol_ch_q : std_logic; + signal rx_los_low_ch_q : std_logic; + signal rx_lol_los : std_logic; + signal rx_lol_los_int : std_logic; + signal rx_lol_los_del : std_logic; + signal rx_pcs_rst_ch_c_int : std_logic; + signal rx_serdes_rst_ch_c_int : std_logic; -signal reset_timer2 : std_logic; -signal counter2 : unsigned(19 downto 0); -signal timer2 : std_logic; + signal reset_timer2 : std_logic; + signal counter2 : unsigned(19 downto 0); + signal timer2 : std_logic; begin -rx_lol_los <= rx_cdr_lol_ch_q or rx_los_low_ch_q ; + rx_lol_los <= rx_cdr_lol_ch_q or rx_los_low_ch_q ; -sync_sfp_sigs : entity work.signal_sync - generic map( - WIDTH => 3 - ) - port map( - RESET => '0', - CLK0 => RX_REFCLK, - CLK1 => RX_REFCLK, - D_IN(0) => TX_PLL_LOL_QD_S, - D_IN(1) => RX_CDR_LOL_CH_S, - D_IN(2) => RX_LOS_LOW_CH_S, - D_OUT(0) => tx_pll_lol_qd_q, - D_OUT(1) => rx_cdr_lol_ch_q, - D_OUT(2) => rx_los_low_ch_q - ); + SYNC_SFP_SIGS : entity work.signal_sync + generic map( + WIDTH => 3 + ) + port map( + RESET => '0', + CLK0 => RX_REFCLK, + CLK1 => RX_REFCLK, + D_IN(0) => TX_PLL_LOL_QD_S, + D_IN(1) => RX_CDR_LOL_CH_S, + D_IN(2) => RX_LOS_LOW_CH_S, + D_OUT(0) => tx_pll_lol_qd_q, + D_OUT(1) => rx_cdr_lol_ch_q, + D_OUT(2) => rx_los_low_ch_q + ); --timer2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles --An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set timer2 = bit[18] -THE_TIMER2_PROC: process( RX_REFCLK ) -begin - if( rising_edge(RX_REFCLK) ) then - if reset_timer2 = '1' then - counter2 <= (others => '0'); - timer2 <= '0'; - else - if counter2(count_index) = '1' then - timer2 <= '1'; - else + THE_TIMER2_PROC: process( RX_REFCLK ) + begin + if( rising_edge(RX_REFCLK) ) then + if reset_timer2 = '1' then + counter2 <= (others => '0'); timer2 <= '0'; - counter2 <= counter2 + 1 ; + else + if counter2(count_index) = '1' then + timer2 <= '1'; + else + timer2 <= '0'; + counter2 <= counter2 + 1 ; + end if; end if; end if; - end if; -end process THE_TIMER2_PROC; + end process THE_TIMER2_PROC; --- State machine clocked process -THE_FSM_PROC: process( RX_REFCLK ) -begin - if rising_edge(RX_REFCLK) then - if RST_N = '0' then - cs <= WAIT_FOR_PLOL; - rx_lol_los_int <= '1'; - rx_lol_los_del <= '1'; - RX_PCS_RST_CH_C <= '1'; - RX_SERDES_RST_CH_C <= '0'; - else - cs <= ns; - rx_lol_los_del <= rx_lol_los; - rx_lol_los_int <= rx_lol_los_del; - RX_PCS_RST_CH_C <= rx_pcs_rst_ch_c_int; - RX_SERDES_RST_CH_C <= rx_serdes_rst_ch_c_int; + -- State machine clocked process + THE_FSM_PROC: process( RX_REFCLK ) + begin + if rising_edge(RX_REFCLK) then + if RST_N = '0' then + cs <= WAIT_FOR_PLOL; + rx_lol_los_int <= '1'; + rx_lol_los_del <= '1'; + RX_PCS_RST_CH_C <= '1'; + RX_SERDES_RST_CH_C <= '0'; + else + cs <= ns; + rx_lol_los_del <= rx_lol_los; + rx_lol_los_int <= rx_lol_los_del; + RX_PCS_RST_CH_C <= rx_pcs_rst_ch_c_int; + RX_SERDES_RST_CH_C <= rx_serdes_rst_ch_c_int; + end if; end if; - end if; -end process; + end process THE_FSM_PROC; -THE_FSM_DECODE_PROC: process( cs, tx_pll_lol_qd_q, rx_los_low_ch_q, rx_lol_los_int, timer2, wa_position, rx_lol_los_del ) -begin - reset_timer2 <= '0'; - STATE_OUT <= x"F"; - NORMAL_OPERATION_OUT <= '0'; + THE_FSM_DECODE_PROC: process( cs, tx_pll_lol_qd_q, rx_los_low_ch_q, rx_lol_los_int, timer2, wa_position, rx_lol_los_del ) + begin + reset_timer2 <= '0'; + STATE_OUT <= x"F"; + NORMAL_OPERATION_OUT <= '0'; - case cs is - when WAIT_FOR_PLOL => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if( (tx_pll_lol_qd_q = '1') or (rx_los_low_ch_q = '1') ) then -- also make sure a Signal - ns <= WAIT_FOR_PLOL; -- is present prior to moving to the next - else - ns <= RX_SERDES_RESET; - end if; - STATE_OUT <= x"1"; + case cs is + when WAIT_FOR_PLOL => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + if( (tx_pll_lol_qd_q = '1') or (rx_los_low_ch_q = '1') ) then -- also make sure a Signal + ns <= WAIT_FOR_PLOL; -- is present prior to moving to the next + else + ns <= RX_SERDES_RESET; + end if; + STATE_OUT <= x"1"; - when RX_SERDES_RESET => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - ns <= WAIT_FOR_TIMER1; - STATE_OUT <= x"2"; + when RX_SERDES_RESET => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '1'; + ns <= WAIT_FOR_TIMER1; + STATE_OUT <= x"2"; - when WAIT_FOR_TIMER1 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '1'; - ns <= CHECK_LOL_LOS; - STATE_OUT <= x"3"; + when WAIT_FOR_TIMER1 => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '1'; + ns <= CHECK_LOL_LOS; + STATE_OUT <= x"3"; - when CHECK_LOL_LOS => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; - STATE_OUT <= x"4"; + when CHECK_LOL_LOS => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; + STATE_OUT <= x"4"; - when WAIT_FOR_TIMER2 => - rx_pcs_rst_ch_c_int <= '1'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES - if timer2 = '1' then - if rx_lol_los_int = '1' then - ns <= WAIT_FOR_PLOL; + when WAIT_FOR_TIMER2 => + rx_pcs_rst_ch_c_int <= '1'; + rx_serdes_rst_ch_c_int <= '0'; + if rx_lol_los_int = rx_lol_los_del then --NO RISING OR FALLING EDGES + if timer2 = '1' then + if rx_lol_los_int = '1' then + ns <= WAIT_FOR_PLOL; + else + ns <= CHECK_WAP; + reset_timer2 <= '1'; + end if; else - ns <= CHECK_WAP; - reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; end if; else - ns <= WAIT_FOR_TIMER2; + ns <= CHECK_LOL_LOS; --RESET timer2 end if; - else - ns <= CHECK_LOL_LOS; --RESET timer2 - end if; - STATE_OUT <= x"5"; + STATE_OUT <= x"5"; + + when CHECK_WAP => + rx_pcs_rst_ch_c_int <= '0'; + rx_serdes_rst_ch_c_int <= '0'; +-- if timer2 = '1' then + if std_logic(counter2(16)) = '1' then -- may be too long + if WA_POSITION /= x"0" then + ns <= WAIT_FOR_PLOL; + else + ns <= NORMAL; + end if; + else + ns <= CHECK_WAP; + end if; + STATE_OUT <= x"7"; - when CHECK_WAP => - rx_pcs_rst_ch_c_int <= '0'; - rx_serdes_rst_ch_c_int <= '0'; --- if timer2 = '1' then - if std_logic(counter2(16)) = '1' then -- may be too long - if WA_POSITION /= x"0" then + when NORMAL => + rx_pcs_rst_ch_c_int <= '0'; + rx_serdes_rst_ch_c_int <= '0'; + if rx_lol_los_int = '1' or WA_POSITION /= x"0" then ns <= WAIT_FOR_PLOL; else + NORMAL_OPERATION_OUT <= '1'; ns <= NORMAL; end if; - else - ns <= CHECK_WAP; - end if; - STATE_OUT <= x"7"; - - when NORMAL => - rx_pcs_rst_ch_c_int <= '0'; - rx_serdes_rst_ch_c_int <= '0'; - if rx_lol_los_int = '1' or WA_POSITION /= x"0" then - ns <= WAIT_FOR_PLOL; - else - NORMAL_OPERATION_OUT <= '1'; - ns <= NORMAL; - end if; - STATE_OUT <= x"6"; + STATE_OUT <= x"6"; - when others => - ns <= WAIT_FOR_PLOL; + when others => + ns <= WAIT_FOR_PLOL; - end case; + end case; -end process THE_FSM_DECODE_PROC; + end process THE_FSM_DECODE_PROC; end architecture; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 74a0493..58002a2 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -13,26 +13,30 @@ entity tx_control_RS is CLK_100 : in std_logic; RESET_IN : in std_logic; - WORD_SYNC_IN : in std_logic; - + -- CLK_100 signals TX_DATA_IN : in std_logic_vector(15 downto 0); TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0); TX_WRITE_IN : in std_logic; TX_READ_OUT : out std_logic; - TX_DATA_OUT : out std_logic_vector( 7 downto 0); + -- CLK_200 signals + TX_DATA_OUT : out std_logic_vector(7 downto 0); TX_K_OUT : out std_logic; TX_CD_OUT : out std_logic; + + WORD_SYNC_IN : in std_logic; - SEND_DLM_IN : in std_logic := '0'; - SEND_DLM_WORD_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + SEND_DLM_IN : in std_logic; + SEND_DLM_WORD_IN : in std_logic_vector(7 downto 0); - SEND_RST_IN : in std_logic := '0'; - SEND_RST_WORD_IN : in std_logic_vector( 7 downto 0) := (others => '0'); + SEND_RST_IN : in std_logic; + SEND_RST_WORD_IN : in std_logic_vector(7 downto 0); + -- internally synced TX_ALLOW_IN : in std_logic := '0'; RX_ALLOW_IN : in std_logic := '0'; + -- unknown clock DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) ); @@ -249,6 +253,7 @@ begin TX_DATA_OUT <= K_RST; TX_K_OUT <= '1'; current_state <= SEND_RST_H; + debug_sending_rst <= '1'; when SEND_RST_H => TX_DATA_OUT <= send_rst_word_i; diff --git a/media_interfaces/sync/tx_reset_fsm_RS.vhd b/media_interfaces/sync/tx_reset_fsm_RS.vhd index 40d6fa8..2f5c09f 100644 --- a/media_interfaces/sync/tx_reset_fsm_RS.vhd +++ b/media_interfaces/sync/tx_reset_fsm_RS.vhd @@ -5,72 +5,72 @@ USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.all; entity tx_reset_fsm_RS is -port ( - RST_N : in std_logic; - TX_REFCLK : in std_logic; - TX_PLL_LOL_QD_S : in std_logic; - RX_RESET_FINISHED_IN : in std_logic; - RST_QD_C : out std_logic; - TX_PCS_RST_CH_C : out std_logic; - NORMAL_OPERATION_OUT : out std_logic; - STATE_OUT : out std_logic_vector(3 downto 0) + port( + RST_N : in std_logic; + TX_REFCLK : in std_logic; + TX_PLL_LOL_QD_S : in std_logic; + RX_RESET_FINISHED_IN : in std_logic; + RST_QD_C : out std_logic; + TX_PCS_RST_CH_C : out std_logic; + NORMAL_OPERATION_OUT : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) ); end entity; architecture tx_reset_fsm_arch of tx_reset_fsm_RS is -constant count_index : integer := 19; -- end of timer2 + constant count_index : integer := 19; -- end of timer2 -type statetype is ( QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL, WAIT_FOR_RX ); + type statetype is ( QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL, WAIT_FOR_RX ); -signal cs : statetype; -- current state of lsm -signal ns : statetype; -- next state of lsm + signal cs : statetype; -- current state of lsm + signal ns : statetype; -- next state of lsm -signal tx_pll_lol_qd_s_int : std_logic; -signal tx_pcs_rst_ch_c_int : std_logic; -signal rst_qd_c_int : std_logic; + signal tx_pll_lol_qd_s_int : std_logic; + signal tx_pcs_rst_ch_c_int : std_logic; + signal rst_qd_c_int : std_logic; -signal reset_timer1 : std_logic; -signal reset_timer2 : std_logic; + signal reset_timer1 : std_logic; + signal reset_timer2 : std_logic; -signal counter1 : unsigned(2 downto 0); -signal timer1 : std_logic; + signal counter1 : unsigned(2 downto 0); + signal timer1 : std_logic; -signal counter2 : unsigned(19 downto 0); -signal timer2 : std_logic; + signal counter2 : unsigned(19 downto 0); + signal timer2 : std_logic; begin - -SYNC_SFP_SIGS : entity work.signal_sync - port map( - RESET => '0', - CLK0 => TX_REFCLK, - CLK1 => TX_REFCLK, - D_IN(0) => TX_PLL_LOL_QD_S, - D_OUT(0) => tx_pll_lol_qd_s_int - ); + + SYNC_SFP_SIGS : entity work.signal_sync + port map( + RESET => '0', + CLK0 => TX_REFCLK, + CLK1 => TX_REFCLK, + D_IN(0) => TX_PLL_LOL_QD_S, + D_OUT(0) => tx_pll_lol_qd_s_int + ); --TIMER1 = 20ns; --Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles -- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] -- Timer 1 -THE_TIMER1_PROC: process( TX_REFCLK ) -begin - if rising_edge(TX_REFCLK) then - if reset_timer1 = '1' then - counter1 <= (others => '0'); - timer1 <= '0'; - else - if counter1(2) = '1' then - timer1 <= '1'; + THE_TIMER1_PROC: process( TX_REFCLK ) + begin + if rising_edge(TX_REFCLK) then + if reset_timer1 = '1' then + counter1 <= (others => '0'); + timer1 <= '0'; else - timer1 <='0'; - counter1 <= counter1 + 1 ; + if counter1(2) = '1' then + timer1 <= '1'; + else + timer1 <='0'; + counter1 <= counter1 + 1 ; + end if; end if; end if; - end if; -end process THE_TIMER1_PROC; + end process THE_TIMER1_PROC; --TIMER2 = 1,400,000 UI; --WORST CASE CYCLES is with smallest multipier factor. @@ -79,107 +79,108 @@ end process THE_TIMER1_PROC; -- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES -- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18] -THE_TIMER2_PROC: process( TX_REFCLK ) -begin - if rising_edge(TX_REFCLK) then - if reset_timer2 = '1' then - counter2 <= (others => '0'); - timer2 <= '0'; - else - if counter2(count_index) = '1' then - timer2 <='1'; + THE_TIMER2_PROC: process( TX_REFCLK ) + begin + if rising_edge(TX_REFCLK) then + if reset_timer2 = '1' then + counter2 <= (others => '0'); + timer2 <= '0'; else - timer2 <='0'; - counter2 <= counter2 + 1 ; + if counter2(count_index) = '1' then + timer2 <='1'; + else + timer2 <='0'; + counter2 <= counter2 + 1 ; + end if; end if; end if; - end if; -end process THE_TIMER2_PROC; + end process THE_TIMER2_PROC; -- State machine clocked process -THE_FSM_PROC: process( TX_REFCLK, RST_N ) -begin - if RST_N = '0' then - cs <= QUAD_RESET; - TX_PCS_RST_CH_C <= '1'; - RST_QD_C <= '1'; - else - if rising_edge(TX_REFCLK) then - cs <= ns; - TX_PCS_RST_CH_C <= tx_pcs_rst_ch_c_int; - RST_QD_C <= rst_qd_c_int; + THE_FSM_PROC: process( TX_REFCLK, RST_N ) + begin + if RST_N = '0' then + cs <= QUAD_RESET; + TX_PCS_RST_CH_C <= '1'; + RST_QD_C <= '1'; + else + if rising_edge(TX_REFCLK) then + cs <= ns; + TX_PCS_RST_CH_C <= tx_pcs_rst_ch_c_int; + RST_QD_C <= rst_qd_c_int; + end if; end if; - end if; -end process THE_FSM_PROC; + end process THE_FSM_PROC; -THE_FSM_DECODE_PROC: process( cs, timer1, timer2, tx_pll_lol_qd_s_int, RX_RESET_FINISHED_IN ) -begin - reset_timer1 <= '0'; - reset_timer2 <= '0'; - rst_qd_c_int <= '0'; - tx_pcs_rst_ch_c_int <= '0'; - STATE_OUT <= x"F"; - NORMAL_OPERATION_OUT <= '0'; + THE_FSM_DECODE_PROC: process( cs, timer1, timer2, tx_pll_lol_qd_s_int, RX_RESET_FINISHED_IN ) + begin + reset_timer1 <= '0'; + reset_timer2 <= '0'; + rst_qd_c_int <= '0'; + tx_pcs_rst_ch_c_int <= '0'; + STATE_OUT <= x"F"; + NORMAL_OPERATION_OUT <= '0'; - case cs is + case cs is - when QUAD_RESET => - STATE_OUT <= x"1"; - tx_pcs_rst_ch_c_int <= '1'; - rst_qd_c_int <= '1'; - reset_timer1 <= '1'; - ns <= WAIT_FOR_TIMER1; - - when WAIT_FOR_TIMER1 => - STATE_OUT <= x"2"; - tx_pcs_rst_ch_c_int <= '1'; - rst_qd_c_int <= '1'; - if timer1 = '1' then - ns <= CHECK_PLOL; - else + when QUAD_RESET => + STATE_OUT <= x"1"; + tx_pcs_rst_ch_c_int <= '1'; + rst_qd_c_int <= '1'; + reset_timer1 <= '1'; ns <= WAIT_FOR_TIMER1; - end if; - when CHECK_PLOL => - STATE_OUT <= x"3"; - tx_pcs_rst_ch_c_int <= '1'; - reset_timer2 <= '1'; - ns <= WAIT_FOR_TIMER2; + when WAIT_FOR_TIMER1 => + STATE_OUT <= x"2"; + tx_pcs_rst_ch_c_int <= '1'; + rst_qd_c_int <= '1'; + if timer1 = '1' then + ns <= CHECK_PLOL; + else + ns <= WAIT_FOR_TIMER1; + end if; + + when CHECK_PLOL => + STATE_OUT <= x"3"; + tx_pcs_rst_ch_c_int <= '1'; + reset_timer2 <= '1'; + ns <= WAIT_FOR_TIMER2; - when WAIT_FOR_TIMER2 => - STATE_OUT <= x"4"; - tx_pcs_rst_ch_c_int <= '1'; - if timer2 = '1' then + when WAIT_FOR_TIMER2 => + STATE_OUT <= x"4"; + tx_pcs_rst_ch_c_int <= '1'; + if timer2 = '1' then + if tx_pll_lol_qd_s_int = '1' then + ns <= QUAD_RESET; + else + ns <= WAIT_FOR_RX; + end if; + else + ns <= WAIT_FOR_TIMER2; + end if; + + when WAIT_FOR_RX => + if RX_RESET_FINISHED_IN = '1' then + ns <= NORMAL; + else + ns <= WAIT_FOR_RX; + end if; + + when NORMAL => + STATE_OUT <= x"5"; + tx_pcs_rst_ch_c_int <= '0'; if tx_pll_lol_qd_s_int = '1' then ns <= QUAD_RESET; else - ns <= WAIT_FOR_RX; + NORMAL_OPERATION_OUT <= '1'; + ns <= NORMAL; end if; - else - ns <= WAIT_FOR_TIMER2; - end if; - - when WAIT_FOR_RX => - if RX_RESET_FINISHED_IN = '1' then - ns <= NORMAL; - else - ns <= WAIT_FOR_RX; - end if; - - when NORMAL => - STATE_OUT <= x"5"; - tx_pcs_rst_ch_c_int <= '0'; - if tx_pll_lol_qd_s_int = '1' then - ns <= QUAD_RESET; - else - NORMAL_OPERATION_OUT <= '1'; - ns <= NORMAL; - end if; - when others => - ns <= QUAD_RESET; + when others => + ns <= QUAD_RESET; - end case; -end process THE_FSM_DECODE_PROC; + end case; + + end process THE_FSM_DECODE_PROC; end architecture; -- 2.43.0