From 8136c15ed01396d4641aa27944efacd072d88ecd Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 5 Jul 2022 17:47:30 +0200 Subject: [PATCH] raw SCTRL endpoint works --- gbe_hub/trb3sc_gbe_hub.lpf | 3 +- gbe_hub/trb3sc_gbe_hub.prj | 1 + gbe_hub/trb3sc_gbe_hub.vhd | 212 ++++++++++++++++++++++++++++++++----- 3 files changed, 189 insertions(+), 27 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.lpf b/gbe_hub/trb3sc_gbe_hub.lpf index e820fc0..9b2ad66 100644 --- a/gbe_hub/trb3sc_gbe_hub.lpf +++ b/gbe_hub/trb3sc_gbe_hub.lpf @@ -2,8 +2,9 @@ LOCATE COMP "GBE/physical/gbe_serdes/PCSD_INST" SITE "PCSD"; -LOCATE COMP "THE_GBE_MED_RAW_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; LOCATE COMP "THE_GBE_MED_RAW_PCSB/gbe_serdes/PCSD_INST" SITE "PCSB"; +LOCATE COMP "THE_GBE_MED_RAW_PCSC/gbe_serdes/PCSD_INST" SITE "PCSC"; +LOCATE COMP "THE_GBE_MED_RAW_PCSD/gbe_serdes/PCSD_INST" SITE "PCSD"; # main frequencies diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index 5f76730..5ab8b32 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -197,6 +197,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" #add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_interface_single.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_single.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 5993454..e8ebcef 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -121,15 +121,36 @@ architecture trb3sc_arch of trb3sc_gbe_hub is ---------------------------------------------------------------- signal tx_pll_lol_i : std_logic; + signal tx_pll_lol_b_i : std_logic; signal tx_pll_lol_c_i : std_logic; signal tx_pll_lol_d_i : std_logic; signal tx_clk_avail_i : std_logic; signal tx_pcs_rst_i : std_logic; --- signal sync_tx_quad_i : std_logic; signal link_tx_ready_i : std_logic; --- signal link_rx_ready_i : std_logic_vector(3 downto 0); signal status_raw : std_logic_vector(4 * 32 - 1 downto 0); + ---------------------------------------------------------------- + signal mac_ready_conf : std_logic; + signal mac_reconf : std_logic; + signal mac_an_ready : std_logic; + signal mac_fifoavail : std_logic; + signal mac_fifoeof : std_logic; + signal mac_fifoempty : std_logic; + signal mac_rx_fifofull : std_logic; + signal mac_tx_data : std_logic_vector(7 downto 0); + signal mac_tx_read : std_logic; + signal mac_tx_discrfrm : std_logic; + signal mac_tx_stat_en : std_logic; + signal mac_tx_stats : std_logic_vector(30 downto 0); + signal mac_tx_done : std_logic; + signal mac_rx_fifo_err : std_logic; + signal mac_rx_stats : std_logic_vector(31 downto 0); + signal mac_rx_data : std_logic_vector(7 downto 0); + signal mac_rx_write : std_logic; + signal mac_rx_stat_en : std_logic; + signal mac_rx_eof : std_logic; + signal mac_rx_err : std_logic; + begin --------------------------------------------------------------------------- @@ -176,9 +197,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 --------------------------------------------------------------------------- --- PCSD as test point (SFP2) +-- GbE wrapper without med interface --------------------------------------------------------------------------- - GBE : entity work.gbe_wrapper_single + GBE : entity work.gbe_wrapper_raw generic map( DO_SIMULATION => 0, INCLUDE_DEBUG => 0, @@ -193,15 +214,12 @@ THE_CLOCK_RESET : entity work.clock_reset_handler UP_DOWN_LIMIT => 100, FIXED_DELAY => 100, - NUMBER_OF_GBE_LINKS => 4, - LINKS_ACTIVE => "0001", - - LINK_HAS_READOUT => "0000", - LINK_HAS_SLOWCTRL => "0001", - LINK_HAS_DHCP => "0001", - LINK_HAS_ARP => "0001", - LINK_HAS_PING => "0001", - LINK_HAS_FWD => "0000" + LINK_HAS_READOUT => '0', + LINK_HAS_SLOWCTRL => '1', + LINK_HAS_DHCP => '1', + LINK_HAS_ARP => '1', + LINK_HAS_PING => '1', + LINK_HAS_FWD => '0' ) port map( CLK_SYS_IN => clk_sys, @@ -210,10 +228,27 @@ THE_CLOCK_RESET : entity work.clock_reset_handler GSR_N => GSR_N, -- Trigger TRIGGER_IN => '0', - -- SFP - SD_PRSNT_N_IN(0) => SFP_MOD0(0), - SD_LOS_IN(0) => SFP_LOS(0), - SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + -- MAC + MAC_READY_CONF_IN => mac_ready_conf, -- in std_logic; + MAC_RECONF_OUT => mac_reconf, -- out std_logic; + MAC_AN_READY_IN => mac_an_ready, -- in std_logic; + MAC_FIFOAVAIL_OUT => mac_fifoavail, -- out std_logic; + MAC_FIFOEOF_OUT => mac_fifoeof, -- out std_logic; + MAC_FIFOEMPTY_OUT => mac_fifoempty, -- out std_logic; + MAC_RX_FIFOFULL_OUT => mac_rx_fifofull, -- out std_logic; + MAC_TX_DATA_OUT => mac_tx_data, -- out std_logic_vector(7 downto 0); + MAC_TX_READ_IN => mac_tx_read, -- in std_logic; + MAC_TX_DISCRFRM_IN => mac_tx_discrfrm, -- in std_logic; + MAC_TX_STAT_EN_IN => mac_tx_stat_en, -- in std_logic; + MAC_TX_STATS_IN => mac_tx_stats, -- in std_logic_vector(30 downto 0); + MAC_TX_DONE_IN => mac_tx_done, -- in std_logic; + MAC_RX_FIFO_ERR_IN => mac_rx_fifo_err, -- in std_logic; + MAC_RX_STATS_IN => mac_rx_stats, -- in std_logic_vector(31 downto 0); + MAC_RX_DATA_IN => mac_rx_data, -- in std_logic_vector(7 downto 0); + MAC_RX_WRITE_IN => mac_rx_write, -- in std_logic; + MAC_RX_STAT_EN_IN => mac_rx_stat_en, -- in std_logic; + MAC_RX_EOF_IN => mac_rx_eof, -- in std_logic; + MAC_RX_ERROR_IN => mac_rx_err, -- in std_logic; -- unique adresses MC_UNIQUE_ID_IN => timer.uid, MY_TRBNET_ADDRESS_IN => timer.network_address, @@ -240,9 +275,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler STATUS_OUT => status, DEBUG_OUT => open ); - - SFP_TX_DIS(1) <= '1'; - + ------------------------------------------------------------------------------- -- SCTRL endpoint for GbE standalone ------------------------------------------------------------------------------- @@ -408,11 +441,11 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_HUB_TX(8) <= not '0'; LED_HUB_RX(8) <= not '0'; - LED_SFP_GREEN(0) <= not '0'; -- D0 - LED_SFP_RED(0) <= not '0'; + LED_SFP_GREEN(0) <= not status_raw(12 * 8 + 2); --'0'; -- D0 + LED_SFP_RED(0) <= not status_raw(12 * 8 + 5); --'0'; - LED_SFP_GREEN(1) <= not '0'; -- D1 - LED_SFP_RED(1) <= not '0'; + LED_SFP_GREEN(1) <= not status_raw(13 * 8 + 2); --'0'; -- D1 + LED_SFP_RED(1) <= not status_raw(13 * 8 + 5); --'0'; LED_WHITE(1) <= not additional_reg(31); --'0'; LED_WHITE(0) <= not status(8); --'0'; @@ -529,7 +562,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler SD_TXDIS_OUT(2) => open, --HUB_TXDIS(7), SD_TXDIS_OUT(3) => open, --HUB_TXDIS(8), -- SerDes control - TX_PLOL_LOL_OUT => tx_pll_lol_d_i, + TX_PLOL_LOL_OUT => tx_pll_lol_b_i, TX_PCS_RST_IN => tx_pcs_rst_i, RX_LINK_READY_OUT => open, TX_LINK_READY_IN => open, @@ -538,6 +571,66 @@ THE_CLOCK_RESET : entity work.clock_reset_handler DEBUG_OUT => open ); +--------------------------------------------------------------------------- +-- PCSD is on uplink / one downlink (no backplane) or two downlinks (backplane) +--------------------------------------------------------------------------- + THE_GBE_MED_RAW_PCSD: entity gbe_med_raw + generic map( + LINKS_ACTIVE => "0011" + ) + port map( + RESET => reset_i, + GSR_N => GSR_N, + CLK_SYS => clk_sys, + CLK_125 => CLK_SUPPL_PCLK, + CLK_125_RX => open, + -- MAC status and config + MAC_READY_CONF_OUT(0) => mac_ready_conf, -- open, + MAC_RECONF_IN(0) => mac_reconf, -- (others => '0'), + MAC_AN_READY_OUT(0) => mac_an_ready, -- open, + -- MAC data interface + MAC_FIFOAVAIL_IN(0) => mac_fifoavail, -- (others => '0'), + MAC_FIFOEOF_IN(0) => mac_fifoeof, -- (others => '0'), + MAC_FIFOEMPTY_IN(0) => mac_fifoempty, -- (others => '0'), + MAC_RX_FIFOFULL_IN(0) => mac_rx_fifofull, -- (others => '0'), + -- MAC TX interface + MAC_TX_DATA_IN(7 downto 0) => mac_tx_data, -- (others => '0'), + MAC_TX_READ_OUT(0) => mac_tx_read, -- open, + MAC_TX_DISCRFRM_OUT(0) => mac_tx_discrfrm, -- open, + MAC_TX_STAT_EN_OUT(0) => mac_tx_stat_en, -- open, + MAC_TX_STATS_OUT(30 downto 0) => mac_tx_stats, -- open, + MAC_TX_DONE_OUT(0) => mac_tx_done, -- open, + -- MAC RX interface + MAC_RX_FIFO_ERR_OUT(0) => mac_rx_fifo_err, -- open, + MAC_RX_STATS_OUT(31 downto 0) => mac_rx_stats, -- open, + MAC_RX_DATA_OUT(7 downto 0) => mac_rx_data, -- open, + MAC_RX_WRITE_OUT(0) => mac_rx_write, -- open, + MAC_RX_STAT_EN_OUT(0) => mac_rx_stat_en, -- open, + MAC_RX_EOF_OUT(0) => mac_rx_eof, -- open, + MAC_RX_ERROR_OUT(0) => mac_rx_err, -- open, + -- SFP Connection + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(1) => SFP_MOD0(1), + SD_PRSNT_N_IN(2) => '1', + SD_PRSNT_N_IN(3) => '1', + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(1) => SFP_LOS(1), + SD_LOS_IN(2) => '1', + SD_LOS_IN(3) => '1', + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + SD_TXDIS_OUT(1) => SFP_TX_DIS(1), + SD_TXDIS_OUT(2) => open, + SD_TXDIS_OUT(3) => open, + -- SerDes control + TX_PLOL_LOL_OUT => tx_pll_lol_d_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + RX_LINK_READY_OUT => open, + TX_LINK_READY_IN => open, + -- Debug + STATUS_OUT => status_raw(4 * 32 - 1 downto 3 * 32), + DEBUG_OUT => open + ); + --------------------------------------------------------------------------- -- RSL for TX of SerDes, based on extRSL logic --------------------------------------------------------------------------- @@ -553,6 +646,73 @@ THE_CLOCK_RESET : entity work.clock_reset_handler STATE_OUT => open ); - tx_pll_lol_i <= tx_pll_lol_c_i or tx_pll_lol_d_i; + tx_pll_lol_i <= tx_pll_lol_b_i or tx_pll_lol_c_i or tx_pll_lol_d_i; + + + +-- GBE : entity work.gbe_wrapper_single +-- generic map( +-- DO_SIMULATION => 0, +-- INCLUDE_DEBUG => 0, +-- USE_INTERNAL_TRBNET_DUMMY => 0, +-- USE_EXTERNAL_TRBNET_DUMMY => 0, +-- RX_PATH_ENABLE => 1, +-- FIXED_SIZE_MODE => 1, +-- INCREMENTAL_MODE => 1, +-- FIXED_SIZE => 100, +-- FIXED_DELAY_MODE => 1, +-- UP_DOWN_MODE => 0, +-- UP_DOWN_LIMIT => 100, +-- FIXED_DELAY => 100, +-- +-- NUMBER_OF_GBE_LINKS => 4, +-- LINKS_ACTIVE => "0001", +-- +-- LINK_HAS_READOUT => "0000", +-- LINK_HAS_SLOWCTRL => "0001", +-- LINK_HAS_DHCP => "0001", +-- LINK_HAS_ARP => "0001", +-- LINK_HAS_PING => "0001", +-- LINK_HAS_FWD => "0000" +-- ) +-- port map( +-- CLK_SYS_IN => clk_sys, +-- CLK_125_IN => CLK_SUPPL_PCLK, +-- RESET => reset_i, +-- GSR_N => GSR_N, +-- -- Trigger +-- TRIGGER_IN => '0', +-- -- SFP +-- SD_PRSNT_N_IN(0) => SFP_MOD0(0), +-- SD_LOS_IN(0) => SFP_LOS(0), +-- SD_TXDIS_OUT(0) => SFP_TX_DIS(0), +-- -- unique adresses +-- MC_UNIQUE_ID_IN => timer.uid, +-- MY_TRBNET_ADDRESS_IN => timer.network_address, +-- ISSUE_REBOOT_OUT => reboot_from_gbe, +-- -- slow control by GbE +-- GSC_CLK_IN => clk_sys, +-- GSC_INIT_DATAREADY_OUT => gsc_init_dataready, +-- GSC_INIT_DATA_OUT => gsc_init_data, +-- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, +-- GSC_INIT_READ_IN => gsc_init_read, +-- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, +-- GSC_REPLY_DATA_IN => gsc_reply_data, +-- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, +-- GSC_REPLY_READ_OUT => gsc_reply_read, +-- GSC_BUSY_IN => gsc_busy, +-- -- readout +-- BUS_IP_RX => busgbeip_rx, +-- BUS_IP_TX => busgbeip_tx, +-- BUS_REG_RX => busgbereg_rx, +-- BUS_REG_TX => busgbereg_tx, +-- -- reset +-- MAKE_RESET_OUT => reset_via_gbe, +-- -- debug +-- STATUS_OUT => status, +-- DEBUG_OUT => open +-- ); +-- +-- SFP_TX_DIS(1) <= '1'; end architecture; -- 2.43.0