From 815fe0c4d557da1d7cb2073eb004bc9cf7557141 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Thu, 6 Nov 2014 09:09:40 +0100 Subject: [PATCH] CTS: JTTL(15) functions as reboot input (provide 1.28us high-pulse) --- base/trb3_central_cts.lpf | 3 ++- cts/trb3_central.vhd | 25 ++++++++++++++++++++++--- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/base/trb3_central_cts.lpf b/base/trb3_central_cts.lpf index f91381f..5a6136b 100644 --- a/base/trb3_central_cts.lpf +++ b/base/trb3_central_cts.lpf @@ -382,8 +382,9 @@ LOCATE COMP "JTTL_12" SITE "A8"; LOCATE COMP "JTTL_13" SITE "A9"; LOCATE COMP "JTTL_14" SITE "K11"; LOCATE COMP "JTTL_15" SITE "J11"; -DEFINE PORT GROUP "JTTL_group" "JTTL*" ; +DEFINE PORT GROUP "JTTL_group" "JTTL_{0:14}" ; IOBUF GROUP "JTTL_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=8; +IOBUF PORT "JTTL_15" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; LOCATE COMP "LED_BANK_0" SITE "E13"; LOCATE COMP "LED_BANK_1" SITE "F13"; diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index d101326..253b096 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -546,7 +546,8 @@ architecture trb3_central_arch of trb3_central is signal led_time_ref_i : std_logic; - signal do_reboot_i : std_logic; + signal do_reboot_i : std_logic; + signal killswitch_reboot_i : std_logic; -- cbmnet signal cbm_clk_i : std_logic; @@ -1571,7 +1572,25 @@ begin PROGRAMN => PROGRAMN ); - do_reboot_i <= common_ctrl_regs(15); + do_reboot_i <= common_ctrl_regs(15) or killswitch_reboot_i; + + -- if jttl(15) is stabily high for 1.28us: issue reboot + THE_KILLSWITCH_PROC: process + variable stab_counter : unsigned(7 downto 0); + variable inp, inp_delay : std_logic := '0'; + begin + wait until rising_edge(clk_100_i); + + if inp_delay = inp then + stab_counter := stab_counter + 1; + else + stab_counter := 0; + end if; + + inp_delay := inp; + inp := JTTL(15); + killswitch_reboot_i <= stab_counter(stab_counter'high) and inp; + end process; ------------------------------------------------------------------------------- -- TDC @@ -1668,7 +1687,7 @@ begin tdc_inputs(2) <= cbm_sync_pulser_i; tdc_inputs(3) <= cbm_sync_timing_trigger_i; tdc_inputs(4) <= JINLVDS(0); --NIM_IN(0); - JTTL(0 downto 15) <= (others => '0'); + --JTTL(0 downto 15) <= (others => '0'); PROC_TDC_CTRL_REG : process -- 2.43.0