From 816c181c4d752f120d97039fe0e26c11c20613ab Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 15 Sep 2014 18:58:08 +0200 Subject: [PATCH] changed reset behavior of external clock selection. Now static. --- trb3_gbe/config_default.vhd | 7 +++++-- trb3_gbe/trb3_central.vhd | 9 ++------- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/trb3_gbe/config_default.vhd b/trb3_gbe/config_default.vhd index c9a9ebe..bb654bf 100644 --- a/trb3_gbe/config_default.vhd +++ b/trb3_gbe/config_default.vhd @@ -29,7 +29,7 @@ package config is constant USE_RXCLOCK : integer := c_NO; --Run external 200 MHz clock source - constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO; + constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO; --Address settings constant INIT_ENDPOINT_ID : std_logic_vector := x"0005"; @@ -113,7 +113,7 @@ function generateIncludedFeatures return std_logic_vector; constant MEDIA_FREQUENCY : integer; constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); - + constant USE_EXTERNAL_CLOCK_std : std_logic; end; package body config is @@ -149,4 +149,7 @@ package body config is constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); constant INCLUDED_FEATURES : std_logic_vector := generateIncludedFeatures; + + constant USE_EXTERNAL_CLOCK_std : std_logic := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1))(0); + end package body; \ No newline at end of file diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index 218c01c..b9833e2 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -254,7 +254,7 @@ signal gbe_stp_reg_read : std_logic; signal gbe_stp_reg_write : std_logic; signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); -signal select_tc : std_logic_vector(31 downto 0); +signal select_tc : std_logic_vector(31 downto 0) := (8 => USE_EXTERNAL_CLOCK_std, others => '0'); signal select_tc_data_in : std_logic_vector(31 downto 0); signal select_tc_write : std_logic; signal select_tc_read : std_logic; @@ -1034,12 +1034,7 @@ end generate; process begin wait until rising_edge(clk_sys_i); - if reset_i = '1' then - select_tc <= x"00000000"; --always external trigger source, external clock - if USE_EXTERNAL_CLOCK = c_YES then - select_tc(8) <= '1'; - end if; - elsif select_tc_write = '1' then + if select_tc_write = '1' then select_tc <= select_tc_data_in; end if; select_tc_ack <= select_tc_read or select_tc_write; -- 2.43.0