From 821335824d952a0a2f496d0db9b7946ec531dd32 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 17 Oct 2011 13:52:24 +0000 Subject: [PATCH] trb3_gbe --- trb3_gbe_test/ipcores/serdes.ipx | 11 ++ trb3_gbe_test/ipcores/serdes.lpc | 258 +++++++++++++++++++++++++++++++ 2 files changed, 269 insertions(+) create mode 100644 trb3_gbe_test/ipcores/serdes.ipx create mode 100644 trb3_gbe_test/ipcores/serdes.lpc diff --git a/trb3_gbe_test/ipcores/serdes.ipx b/trb3_gbe_test/ipcores/serdes.ipx new file mode 100644 index 0000000..49a0157 --- /dev/null +++ b/trb3_gbe_test/ipcores/serdes.ipx @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/trb3_gbe_test/ipcores/serdes.lpc b/trb3_gbe_test/ipcores/serdes.lpc new file mode 100644 index 0000000..0abc5fa --- /dev/null +++ b/trb3_gbe_test/ipcores/serdes.lpc @@ -0,0 +1,258 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=8.1 +ModuleName=serdes +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/14/2011 +Time=13:51:31 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +_mode0=RXTX +_mode1=RXTX +_mode2=DISABLED +_mode3=DISABLED +_protocol0=GIGE +_protocol1=GIGE +_protocol2=G8B10B +_protocol3=G8B10B +_ldr0=DISABLED +_ldr1=DISABLED +_ldr2=DISABLED +_ldr3=DISABLED +_datarange=1.25 +_pll_txsrc=INTERNAL +_refclk_mult=10X +_refclk_rate=125.0 +_tx_protocol0=GIGE +_tx_protocol1=GIGE +_tx_protocol2=DISABLED +_tx_protocol3=DISABLED +_tx_data_rate0=FULL +_tx_data_rate1=FULL +_tx_data_rate2=FULL +_tx_data_rate3=FULL +_tx_data_width0=8 +_tx_data_width1=8 +_tx_data_width2=8 +_tx_data_width3=8 +_tx_fifo0=ENABLED +_tx_fifo1=ENABLED +_tx_fifo2=ENABLED +_tx_fifo3=ENABLED +_tx_ficlk_rate0=125.0 +_tx_ficlk_rate1=125.0 +_tx_ficlk_rate2=125.0 +_tx_ficlk_rate3=125.0 +_pll_rxsrc0=INTERNAL +_pll_rxsrc1=INTERNAL +_pll_rxsrc2=EXTERNAL +_pll_rxsrc3=EXTERNAL +Multiplier0= +Multiplier1= +Multiplier2= +Multiplier3= +_rx_datarange0=1.25 +_rx_datarange1=1.25 +_rx_datarange2=2.5 +_rx_datarange3=2.5 +_rx_protocol0=GIGE +_rx_protocol1=GIGE +_rx_protocol2=DISABLED +_rx_protocol3=DISABLED +_rx_data_rate0=FULL +_rx_data_rate1=FULL +_rx_data_rate2=FULL +_rx_data_rate3=FULL +_rxrefclk_rate0=125.0 +_rxrefclk_rate1=125.0 +_rxrefclk_rate2=250.0 +_rxrefclk_rate3=250.0 +_rx_data_width0=8 +_rx_data_width1=8 +_rx_data_width2=8 +_rx_data_width3=8 +_rx_fifo0=ENABLED +_rx_fifo1=ENABLED +_rx_fifo2=ENABLED +_rx_fifo3=ENABLED +_rx_ficlk_rate0=125.0 +_rx_ficlk_rate1=125.0 +_rx_ficlk_rate2=250.0 +_rx_ficlk_rate3=250.0 +_tdrv_ch0=0 +_tdrv_ch1=0 +_tdrv_ch2=0 +_tdrv_ch3=0 +_tx_pre0=DISABLED +_tx_pre1=DISABLED +_tx_pre2=DISABLED +_tx_pre3=DISABLED +_rterm_tx0=50 +_rterm_tx1=50 +_rterm_tx2=50 +_rterm_tx3=50 +_rx_eq0=DISABLED +_rx_eq1=DISABLED +_rx_eq2=DISABLED +_rx_eq3=DISABLED +_rterm_rx0=50 +_rterm_rx1=50 +_rterm_rx2=50 +_rterm_rx3=50 +_rx_dcc0=AC +_rx_dcc1=AC +_rx_dcc2=AC +_rx_dcc3=AC +_los_threshold_mode0=LOS_E +_los_threshold_mode1=LOS_E +_los_threshold_mode2=LOS_E +_los_threshold_mode3=LOS_E +_los_threshold_lo0=2 +_los_threshold_lo1=2 +_los_threshold_lo2=2 +_los_threshold_lo3=2 +_los_threshold_hi0=7 +_los_threshold_hi1=7 +_los_threshold_hi2=7 +_los_threshold_hi3=7 +_pll_term=50 +_pll_dcc=AC +_pll_lol_set=0 +_tx_sb0=DISABLED +_tx_sb1=DISABLED +_tx_sb2=DISABLED +_tx_sb3=DISABLED +_tx_8b10b0=ENABLED +_tx_8b10b1=ENABLED +_tx_8b10b2=ENABLED +_tx_8b10b3=ENABLED +_rx_sb0=DISABLED +_rx_sb1=DISABLED +_rx_sb2=DISABLED +_rx_sb3=DISABLED +_ird0=DISABLED +_ird1=DISABLED +_ird2=DISABLED +_ird3=DISABLED +_rx_8b10b0=ENABLED +_rx_8b10b1=ENABLED +_rx_8b10b2=ENABLED +_rx_8b10b3=ENABLED +_rxwa0=ENABLED +_rxwa1=ENABLED +_rxwa2=ENABLED +_rxwa3=ENABLED +_ilsm0=ENABLED +_ilsm1=ENABLED +_ilsm2=ENABLED +_ilsm3=ENABLED +_scomma0=K28P5 +_scomma1=K28P5 +_scomma2=K28P157 +_scomma3=K28P157 +_comma_a0=1100000101 +_comma_a1=1100000101 +_comma_a2=1100000101 +_comma_a3=1100000101 +_comma_b0=0011111010 +_comma_b1=0011111010 +_comma_b2=0011111010 +_comma_b3=0011111010 +_comma_m0=1111111111 +_comma_m1=1111111111 +_comma_m2=1111111100 +_comma_m3=1111111100 +_ctc0=DISABLED +_ctc1=DISABLED +_ctc2=DISABLED +_ctc3=DISABLED +_cc_match_mode0=2 +_cc_match_mode1=2 +_cc_match_mode2=1 +_cc_match_mode3=1 +_k00=01 +_k01=01 +_k02=00 +_k03=00 +_k10=00 +_k11=00 +_k12=00 +_k13=00 +_k20=01 +_k21=01 +_k22=01 +_k23=01 +_k30=00 +_k31=00 +_k32=01 +_k33=01 +_byten00=10111100 +_byten01=10111100 +_byten02=00000000 +_byten03=00000000 +_byten10=01010000 +_byten11=01010000 +_byten12=00000000 +_byten13=00000000 +_byten20=10111100 +_byten21=10111100 +_byten22=00011100 +_byten23=00011100 +_byten30=01010000 +_byten31=01010000 +_byten32=00011100 +_byten33=00011100 +_cc_min_ipg0=3 +_cc_min_ipg1=3 +_cc_min_ipg2=3 +_cc_min_ipg3=3 +_cchmark=9 +_cclmark=7 +_loopback=DISABLED +_lbtype0=DISABLED +_lbtype1=DISABLED +_lbtype2=DISABLED +_lbtype3=DISABLED +_teidle_ch0=DISABLED +_teidle_ch1=DISABLED +_teidle_ch2=DISABLED +_teidle_ch3=DISABLED +_rst_gen=DISABLED +_rx_los_port0=Internal +_rx_los_port1=Internal +_rx_los_port2=Internal +_rx_los_port3=Internal +_sci_ports=DISABLED +_sci_int_port=DISABLED +_refck2core=DISABLED +Regen=auto +PAR1=0 +PARTrace1=0 +PAR3=0 +PARTrace3=0 + +[FilesGenerated] +serdes.pp=pp +serdes.tft=tft +serdes.txt=pcs_module +serdes.sym=sym -- 2.43.0