From 8317d27391df74feeed36679b452d0891fe7567a Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 8 Dec 2021 10:02:28 +0100 Subject: [PATCH] ping works now, TRB3sc CTS need recompilation --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 30 +++++----- media_interfaces/sync/med_sync_control_RS.vhd | 7 ++- media_interfaces/sync/med_sync_define_RS.vhd | 2 +- media_interfaces/sync/tx_control_RS.vhd | 56 +++++++++---------- 4 files changed, 48 insertions(+), 47 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index e621236..1fac808 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -121,8 +121,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal powerup_ch : std_logic_vector(3 downto 0); signal tx_ref_clk_i : std_logic; - signal tx_dlm_word_i : std_logic_vector(7 downto 0); - signal tx_rst_word_i : std_logic_vector(4*8-1 downto 0); signal tx_rst_i : std_logic_vector(3 downto 0); @@ -144,7 +142,7 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is begin -- constants used as reminder --- unused = 0, master = 1, slave = 8 +-- unused = 0, master = 1, slave = 8 ------------------------------------------------- -- check settings of media interface @@ -189,11 +187,11 @@ begin MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else - clk_tx_full(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else -- just for testing - clk_tx_full(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else -- just for testing - clk_tx_full(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else -- just for testing - clk_tx_full(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else -- just for testing + clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE + clk_tx_full(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else + clk_tx_full(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else + clk_tx_full(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else + clk_tx_full(3) when ((quad_mode = 1) and (IS_MODE(3) = c_IS_MASTER)) else '0'; ------------------------------------------------- @@ -203,7 +201,7 @@ begin GLOBAL_RESET_OUT <= global_reset_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else global_reset_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else global_reset_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + global_reset_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE GLOBAL_RESET_IN; ------------------------------------------------- @@ -212,7 +210,7 @@ begin tx_clk_avail_sel <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else link_rx_ready_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else link_rx_ready_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE '1'; TX_CLK_AVAIL_OUT <= tx_clk_avail_sel; @@ -223,7 +221,7 @@ begin word_sync_sel <= word_sync_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else word_sync_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else word_sync_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + word_sync_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE word_sync_i(0) when ((quad_mode = 1) and (IS_MODE(0) = c_IS_MASTER)) else word_sync_i(1) when ((quad_mode = 1) and (IS_MODE(1) = c_IS_MASTER)) else word_sync_i(2) when ((quad_mode = 1) and (IS_MODE(2) = c_IS_MASTER)) else @@ -239,13 +237,13 @@ begin RX_RST_OUT <= rx_rst_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else rx_rst_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else rx_rst_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - rx_rst_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + rx_rst_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE '0'; RX_RST_WORD_OUT <= rx_rst_word_i(0*8+7 downto 0*8) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else rx_rst_word_i(1*8+7 downto 1*8) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else rx_rst_word_i(2*8+7 downto 2*8) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else - rx_rst_word_i(3*8+7 downto 3*8) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else + rx_rst_word_i(3*8+7 downto 3*8) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else -- HEREWEARE x"00"; ------------------------------------------------- @@ -452,7 +450,7 @@ gen_control : for i in 0 to 3 generate LINK_RX_READY_OUT => link_rx_ready_i(i), -- komma operation TX_DLM_IN => TX_DLM_IN, - TX_DLM_WORD_IN => tx_dlm_word_i, + TX_DLM_WORD_IN => TX_DLM_WORD_IN, TX_RST_IN => tx_rst_i(i), TX_RST_WORD_IN => tx_rst_word_i(i*8+7 downto i*8), RX_DLM_OUT => RX_DLM_OUT(i), @@ -515,7 +513,9 @@ end generate; cv_cnt_sys <= cv_cnt when rising_edge(SYSCLK); - STAT_DEBUG(63 downto 0) <= (others => '0'); + STAT_DEBUG(3 downto 0) <= clk_rx_full(3 downto 0); + STAT_DEBUG(7 downto 4) <= clk_tx_full(3 downto 0); + STAT_DEBUG(63 downto 8) <= (others => '0'); -- DEBUG_OUT <= debug_i(3*32+31 downto 3*32); DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32); diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 4569313..c738793 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -220,7 +220,7 @@ begin IS_MODE => IS_MODE ) port map( - CLK_TX => CLK_TXI, + CLK_TXI => CLK_TXI, CLK_SYS => CLK_SYS, RESET => reset_i, -- Media Interface @@ -313,8 +313,9 @@ begin DEBUG_OUT(14) <= '0'; DEBUG_OUT(15) <= '0'; -- 16 pin debug connector ends here - DEBUG_OUT(21 downto 16) <= debug_tx_control_i(5 downto 0); - DEBUG_OUT(31 downto 22) <= (others => '0'); + DEBUG_OUT(16) <= word_sync_rx_i; + DEBUG_OUT(17) <= word_sync_tx_i; + DEBUG_OUT(31 downto 18) <= (others => '0'); -- DEBUG_OUT <= (others => '0'); -- Some remarks on the SerDes issue: diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index ca7a759..cabf0ec 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -144,7 +144,7 @@ component tx_control_RS is IS_MODE : integer := c_IS_UNUSED ); port( - CLK_TX : in std_logic; + CLK_TXI : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; -- async/sync reset -- Media Interface diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 77b259c..00ecc2d 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -15,7 +15,7 @@ entity tx_control_RS is IS_MODE : integer := c_IS_UNUSED ); port( - CLK_TX : in std_logic; + CLK_TXI : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; -- async/sync reset -- Media Interface @@ -110,8 +110,8 @@ begin ) port map( RESET => '0', - CLK0 => CLK_TX, - CLK1 => CLK_TX, + CLK0 => CLK_TXI, + CLK1 => CLK_TXI, D_IN(0) => LINK_TX_READY_IN, D_IN(1) => LINK_RX_READY_IN, D_IN(2) => LINK_HALF_DONE_IN, @@ -126,7 +126,7 @@ begin link_active_int <= link_tx_ready_qtx and link_rx_ready_qtx and link_half_done_qtx and link_full_done_qtx; - link_active_qtx <= link_active_int when rising_edge(CLK_TX); + link_active_qtx <= link_active_int when rising_edge(CLK_TXI); -- if not set, send toggling idles send_steady_idle_int <= link_tx_ready_qtx and link_rx_ready_qtx and @@ -157,7 +157,7 @@ begin Data(16) => save_sop, Data(17) => save_eop, WrClock => CLK_SYS, - RdClock => CLK_TX, + RdClock => CLK_TXI, WrEn => ct_fifo_write, RdEn => ct_fifo_read, Reset => ct_fifo_reset, @@ -181,8 +181,8 @@ begin ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN; ct_fifo_read <= link_active_qtx and not ram_afull and not ct_fifo_empty; - last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_TX); - last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_TX); + last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_TXI); + last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_TXI); save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0'; save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0'; @@ -190,17 +190,17 @@ begin ---------------------------------------------------------------------- -- RAM ---------------------------------------------------------------------- - THE_RAM_WR_PROC : process(CLK_TX) + THE_RAM_WR_PROC : process(CLK_TXI) begin - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then ram_write <= last_ct_fifo_read and not last_ct_fifo_empty; end if; end process; --RAM - THE_RAM_PROC : process(CLK_TX) + THE_RAM_PROC : process(CLK_TXI) begin - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then if( ram_write = '1' ) then ram((to_integer(ram_write_addr))) <= tx_data_200; end if; @@ -210,9 +210,9 @@ begin end process; --RAM read pointer - THE_READ_CNT : process(CLK_TX) + THE_READ_CNT : process(CLK_TXI) begin - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then if( link_active_qtx = '0' ) then ram_read_addr <= (others => '0'); elsif( ram_read = '1' ) then @@ -222,9 +222,9 @@ begin end process; --RAM write pointer - THE_WRITE_CNT : process(CLK_TX) + THE_WRITE_CNT : process(CLK_TXI) begin - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then if( link_active_qtx = '0' ) then ram_write_addr <= (others => '0'); elsif( ram_write = '1' ) then @@ -234,9 +234,9 @@ begin end process; --RAM fill level counter - THE_FILL_CNT : process(CLK_TX) + THE_FILL_CNT : process(CLK_TXI) begin - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then if( link_active_qtx = '0' ) then ram_fill_level <= (others => '0'); else @@ -249,13 +249,13 @@ begin ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET = '1' else '0'; ram_afull <= '1' when ram_fill_level >= 4 else '0'; - last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TX); + last_ram_write_addr <= ram_write_addr when rising_edge(CLK_TXI); ---------------------------------------------------------------------- -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(CLK_TX, LINK_TX_READY_IN, RESET) + THE_DATA_CONTROL_FSM : process(CLK_TXI, LINK_TX_READY_IN, RESET) begin if( (LINK_TX_READY_IN = '0') or (RESET = '1') ) then current_state <= IDLE; @@ -263,7 +263,7 @@ begin TX_DATA_OUT <= K_NULL; WORD_SYNC_OUT <= '0'; else - if( rising_edge(CLK_TX) ) then + if( rising_edge(CLK_TXI) ) then TX_K_OUT <= '0'; WORD_SYNC_OUT <= '0'; debug_sending_dlm <= '0'; @@ -364,16 +364,16 @@ begin -- ---------------------------------------------------------------------- -send_dlm_i <= SEND_DLM_IN; -send_dlm_word_i <= SEND_DLM_WORD_IN; +send_dlm_i <= SEND_DLM_IN when rising_edge(CLK_TXI); +send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); --Send DLM message --- THE_STORE_DLM_PROC: process( CLK_TX, RESET ) +-- THE_STORE_DLM_PROC: process( CLK_TXI, RESET ) -- begin -- if( RESET = '1' ) then -- send_dlm_i <= '0'; -- send_dlm_word_i <= (others => '0'); --- elsif( rising_edge(CLK_TX) ) then +-- elsif( rising_edge(CLK_TXI) ) then -- if ( link_active_qtx = '0' ) then -- send_dlm_i <= '0'; -- send_dlm_word_i <= (others => '0'); @@ -390,12 +390,12 @@ send_dlm_word_i <= SEND_DLM_WORD_IN; -- Send RST message -- UNTESTED - THE_STORE_RST_PROC: process( CLK_TX, RESET ) + THE_STORE_RST_PROC: process( CLK_TXI, RESET ) begin if( RESET = '1' ) then send_rst_i <= '0'; send_rst_word_i <= (others => '0'); - elsif( rising_edge(CLK_TX) ) then + elsif( rising_edge(CLK_TXI) ) then if ( link_active_qtx = '0' ) then send_rst_i <= '0'; send_rst_word_i <= (others => '0'); @@ -413,9 +413,9 @@ send_dlm_word_i <= SEND_DLM_WORD_IN; ---------------------------------------------------------------------- -- Debug ---------------------------------------------------------------------- - DEBUG_OUT(31) <= debug_sending_dlm when rising_edge(CLK_TX); + DEBUG_OUT(31) <= debug_sending_dlm when rising_edge(CLK_TXI); DEBUG_OUT(30) <= send_dlm_i; - DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TX); + DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI); DEBUG_OUT(28 downto 6) <= (others => '0'); DEBUG_OUT(5) <= send_steady_idle_int; DEBUG_OUT(4) <= toggle_idle; -- 2.43.0