From 839217681364d23eb18e185781fb3f52868d78c3 Mon Sep 17 00:00:00 2001 From: hadaq Date: Wed, 23 Jun 2010 08:34:00 +0000 Subject: [PATCH] *** empty log message *** --- trb_net_sbuf5.vhd | 62 ++++++++++++++++++++++------------------------- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd index 805f3b3..b5eb11f 100644 --- a/trb_net_sbuf5.vhd +++ b/trb_net_sbuf5.vhd @@ -23,8 +23,9 @@ port( SYN_DATA_OUT : out std_logic_vector(18 downto 0); -- Data word SYN_READ_IN : in std_logic; -- Status and control port - DEBUG : out std_logic_vector(15 downto 0); - DEBUG_DATA : out std_logic_vector(18 downto 0); + DEBUG : out std_logic_vector(7 downto 0); + DEBUG_BSM : out std_logic_vector(3 downto 0); + DEBUG_WCNT : out std_logic_vector(4 downto 0); STAT_BUFFER : out std_logic ); end entity; @@ -51,6 +52,7 @@ end component fifo_19x16_obuf; type STATES is (IDLE, RD1, RD2, RD3, RD4, RD5, WT5, WR5, WD5, DEL); signal CURRENT_STATE, NEXT_STATE: STATES; signal bsm_x : std_logic_vector(3 downto 0); +signal bsm : std_logic_vector(3 downto 0); signal syn_dataready_x : std_logic; signal syn_dataready : std_logic; @@ -71,7 +73,7 @@ signal fifo_wcnt : std_logic_vector(4 downto 0); signal fifo_full : std_logic; signal fifo_almostfull : std_logic; -signal debug_x : std_logic_vector(15 downto 0); +signal debug_x : std_logic_vector(7 downto 0); attribute syn_preserve : boolean; attribute syn_keep : boolean; @@ -79,8 +81,6 @@ attribute syn_preserve of syn_data : signal is true; attribute syn_keep of syn_data : signal is true; attribute syn_preserve of syn_dataready : signal is true; attribute syn_keep of syn_dataready : signal is true; -attribute syn_preserve of syn_dataready_x : signal is true; -attribute syn_keep of syn_dataready_x : signal is true; attribute syn_preserve of fifo_wcnt : signal is true; attribute syn_keep of fifo_wcnt : signal is true; @@ -101,7 +101,8 @@ fifo_reset <= RESET; COMB_next_READ_OUT <= not fifo_almostfull; DEBUG <= debug_x; -DEBUG_DATA <= fifo_data_o; +DEBUG_BSM <= bsm; +DEBUG_WCNT <= fifo_wcnt; STAT_BUFFER <= fifo_full; SYN_DATA_OUT <= syn_data; @@ -153,7 +154,7 @@ begin end process STATE_MEM; -- state transitions -STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready ) +STATE_TRANSFORM: process( CURRENT_STATE, p_wait_x, p_avail_x, SYN_READ_IN, syn_dataready, COMB_DATAREADY_IN ) begin NEXT_STATE <= IDLE; -- avoid latches fifo_rd_en_x <= '0'; @@ -182,33 +183,30 @@ begin syn_dataready_x <= '1'; else NEXT_STATE <= RD2; - syn_dataready_x <= p_avail_x; + syn_dataready_x <= p_avail_x; --?!? end if; - when DEL => if( SYN_READ_IN = '1' ) then + when DEL => syn_dataready_x <= '1'; + if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD3; fifo_rd_en_x <= '1'; - syn_dataready_x <= '1'; else NEXT_STATE <= DEL; - syn_dataready_x <= '1'; end if; - when RD3 => if( SYN_READ_IN = '1' ) then + when RD3 => syn_dataready_x <= '1'; + if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD4; - syn_dataready_x <= '1'; fifo_rd_en_x <= '1'; else NEXT_STATE <= RD3; - syn_dataready_x <= '1'; end if; - when RD4 => if( SYN_READ_IN = '1' ) then + when RD4 => syn_dataready_x <= '1'; + if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD5; - syn_dataready_x <= '1'; fifo_rd_en_x <= '1'; else NEXT_STATE <= RD4; - syn_dataready_x <= '1'; end if; - when RD5 => syn_dataready_x <= '1'; + when RD5 => syn_dataready_x <= '1'; if ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then NEXT_STATE <= WR5; fifo_rd_en_x <= '1'; @@ -217,19 +215,20 @@ begin else NEXT_STATE <= RD5; end if; - when WT5 => if( SYN_READ_IN = '1' ) then - NEXT_STATE <= IDLE; - else - NEXT_STATE <= WT5; - syn_dataready_x <= '1'; - end if; when WR5 => if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then NEXT_STATE <= RD2; fifo_rd_en_x <= '1'; - syn_dataready_x <= '1'; + --syn_dataready_x <= '1'; + syn_dataready_x <= COMB_DATAREADY_IN; else NEXT_STATE <= WR5; end if; + when WT5 => if( SYN_READ_IN = '1' ) then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= WT5; + syn_dataready_x <= '1'; + end if; when others => NEXT_STATE <= IDLE; end case; end process STATE_TRANSFORM; @@ -254,7 +253,6 @@ end process THE_DECODE_PROC; THE_SYNC_PROC: process( CLK ) begin if( rising_edge(CLK) ) then --- if( ((syn_dataready_x = '1') and (syn_read_in = '1')) or (update = '1') ) then if( ((syn_dataready = '1') and (syn_read_in = '1')) or (update = '1') ) then syn_data <= fifo_data_o; end if; @@ -264,12 +262,10 @@ end process THE_SYNC_PROC; --------------------------------------------------------------------- -- DEBUG --------------------------------------------------------------------- -debug_x(15 downto 12) <= bsm_x; -debug_x(11) <= '0'; -debug_x(10) <= fifo_rd_en_x; -debug_x(9) <= p_avail_x; -debug_x(8) <= p_wait_x; -debug_x(7 downto 5) <= (others => '0'); -debug_x(4 downto 0) <= fifo_wcnt; +debug_x(7 downto 4) <= x"0"; +debug_x(3) <= '0'; +debug_x(2) <= fifo_rd_en_x; +debug_x(1) <= p_avail_x; +debug_x(0) <= p_wait_x; end architecture; \ No newline at end of file -- 2.43.0