From 844fe86f558b9b6c5e4f019e68d5478710c42852 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 1 Jul 2022 13:22:13 +0200 Subject: [PATCH] finalize Trb5sc stand-alone design with GbE and only slow control. Reset and Reboot via GbE still missing. --- .gitignore | 1 + gbe_template/config_compile_frankfurt.pl | 8 +- gbe_template/trb5sc_gbe_template.prj | 3 + gbe_template/trb5sc_gbe_template.vhd | 260 +++++++++++++++++------ 4 files changed, 206 insertions(+), 66 deletions(-) diff --git a/.gitignore b/.gitignore index 9f5d28d..3f6e911 100644 --- a/.gitignore +++ b/.gitignore @@ -36,3 +36,4 @@ diamond cores/serdes_sync_0 cores/pcs.vhd archv +_math_real.vhd diff --git a/gbe_template/config_compile_frankfurt.pl b/gbe_template/config_compile_frankfurt.pl index 9dc053b..3fb22d9 100644 --- a/gbe_template/config_compile_frankfurt.pl +++ b/gbe_template/config_compile_frankfurt.pl @@ -4,11 +4,11 @@ Package => 'CABGA756', Speedgrade => '8', -TOPNAME => "trb5sc_template", +TOPNAME => "trb5sc_gbe_template", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.12', -synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', +synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'trb5sc_tdc', @@ -16,8 +16,8 @@ par_options => '../par.p2t', #Include only necessary lpf files -include_TDC => 1, -include_GBE => 0, +include_TDC => 0, +include_GBE => 1, #Report settings firefox_open => 0, diff --git a/gbe_template/trb5sc_gbe_template.prj b/gbe_template/trb5sc_gbe_template.prj index 9809111..277f080 100644 --- a/gbe_template/trb5sc_gbe_template.prj +++ b/gbe_template/trb5sc_gbe_template.prj @@ -195,6 +195,9 @@ add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_standalone_sctrl.vhd" + add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" diff --git a/gbe_template/trb5sc_gbe_template.vhd b/gbe_template/trb5sc_gbe_template.vhd index 088a646..e62e24f 100644 --- a/gbe_template/trb5sc_gbe_template.vhd +++ b/gbe_template/trb5sc_gbe_template.vhd @@ -87,12 +87,6 @@ architecture arch of trb5sc_template is signal reset_i : std_logic; signal clear_i : std_logic; - signal sd_led_green : std_logic; - signal sd_led_red : std_logic; - signal sd_led_yellow : std_logic; - - signal uuid_i : std_logic_vector(63 downto 0); - signal gsc_init_data : std_logic_vector(15 downto 0); signal gsc_reply_data : std_logic_vector(15 downto 0); signal gsc_init_read : std_logic; @@ -110,9 +104,22 @@ architecture arch of trb5sc_template is attribute syn_preserve of GSR_N : signal is true; signal debug : std_logic_vector(127 downto 0); - signal status : std_logic_vector(15 downto 0); + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busgbeip_tx, busgbereg_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busgbeip_rx, busgbereg_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal bus_master_active : std_logic; + + signal timer : TIMERS; + signal additional_reg : std_logic_vector(31 downto 0); + signal led_off : std_logic; + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal sed_error_i : std_logic; + signal flash_ncs_i : std_logic; @@ -134,29 +141,7 @@ begin DEBUG_OUT => open ); -------------------------------------------------------------------------------- --- UUID handling, needed as MAC for GbE -------------------------------------------------------------------------------- - THE_UUID_STUFF: trb_net_i2cwire - generic map( - USE_TEMPERATURE_READOUT => 1, - CLK_PERIOD => 10 - ) - port map( - CLK => clk_sys, - RESET => clear_i, - READOUT_ENABLE_IN => '1', - --connection to I2C interface - SCL_INOUT => I2C_SCL, - SDA_INOUT => I2C_SDA, - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT => open, - ADDR_OUT => open, - WRITE_OUT => open, - TEMP_OUT => open, - ID_OUT => uuid_i, - STAT => open - ); + --------------------------------------------------------------------------- -- GbE @@ -194,9 +179,9 @@ begin -- Trigger TRIGGER_IN => '0', -- SFP - SD_PRSNT_N_IN => SFP_MOD_0, - SD_LOS_IN => SFP_LOS, - SD_TXDIS_OUT => SFP_TX_DIS, + SD_PRSNT_N_IN(0) => SFP_MOD_0, + SD_LOS_IN(0) => SFP_LOS, + SD_TXDIS_OUT(0) => SFP_TX_DIS, -- trigger channel -- only for LINK_HAS_READOUT CTS_NUMBER_IN => (others => '0'), @@ -218,60 +203,211 @@ begin FEE_STATUS_BITS_IN => (others => '0'), FEE_BUSY_IN => '0', -- unique adresses - MC_UNIQUE_ID_IN => uuid_i, - MY_TRBNET_ADDRESS_IN => x"d00f", - ISSUE_REBOOT_OUT => reboot_from_gbe, + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, + ISSUE_REBOOT_OUT => reboot_from_gbe, --BUG: needs to be connected -- slow control by GbE GSC_CLK_IN => clk_sys, - GSC_INIT_DATAREADY_OUT => open, - GSC_INIT_DATA_OUT => open, - GSC_INIT_PACKET_NUM_OUT => open, - GSC_INIT_READ_IN => '0', - GSC_REPLY_DATAREADY_IN => '0', - GSC_REPLY_DATA_IN => (others => '0'), - GSC_REPLY_PACKET_NUM_IN => (others => '0'), - GSC_REPLY_READ_OUT => open, - GSC_BUSY_IN => '0', + GSC_INIT_DATAREADY_OUT => gsc_init_dataready, + GSC_INIT_DATA_OUT => gsc_init_data, + GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, + GSC_INIT_READ_IN => gsc_init_read, + GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, + GSC_REPLY_DATA_IN => gsc_reply_data, + GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, + GSC_REPLY_READ_OUT => gsc_reply_read, + GSC_BUSY_IN => gsc_busy, -- readout - BUS_IP_RX => open, - BUS_IP_TX => open, - BUS_REG_RX => open, - BUS_REG_TX => open, + BUS_IP_RX => busgbeip_rx, -- registers inside GbE + BUS_IP_TX => busgbeip_tx, -- registers inside GbE + BUS_REG_RX => busgbereg_rx, -- registers inside GbE + BUS_REG_TX => busgbereg_tx, -- registers inside GbE -- Forwarder FWD_DST_MAC_IN => (others => '0'), FWD_DST_IP_IN => (others => '0'), FWD_DST_UDP_IN => (others => '0'), FWD_DATA_IN => (others => '0'), - FWD_DATA_VALID_IN => '0', - FWD_SOP_IN => '0', - FWD_EOP_IN => '0', - FWD_READY_OUT => open, - FWD_FULL_OUT => open, + FWD_DATA_VALID_IN(0) => '0', + FWD_SOP_IN(0) => '0', + FWD_EOP_IN(0) => '0', + FWD_READY_OUT(0) => open, + FWD_FULL_OUT(0) => open, -- reset - MAKE_RESET_OUT => reset_via_gbe, -- reset by GbE + MAKE_RESET_OUT => reset_via_gbe, -- reset by GbE --BUG: needs to be connected -- debug and status STATUS_OUT => status, --open, DEBUG_OUT => debug --open ); + + +------------------------------------------------------------------------------- +-- SCTRL endpoint for GbE standalone +------------------------------------------------------------------------------- + THE_ENDPOINT: entity trb_net16_endpoint_standalone_sctrl + generic map( + FIFO_TO_INT_DEPTH => 6, + FIFO_TO_APL_DEPTH => 6, + APL_WRITE_ALL_WORDS => c_NO, + INIT_ADDRESS => INIT_ADDRESS, + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_VAR_ENDPOINT_ID => c_NO, + REGIO_USE_1WIRE_INTERFACE => c_I2C + ) + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + --Port to GbE + GSC_INIT_DATAREADY_IN => gsc_init_dataready, + GSC_INIT_DATA_IN => gsc_init_data, + GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, + GSC_INIT_READ_OUT => gsc_init_read, + GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, + GSC_REPLY_DATA_OUT => gsc_reply_data, + GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, + GSC_REPLY_READ_IN => gsc_reply_read, + GSC_BUSY_OUT => gsc_busy, + GBE_MAKE_RESET_IN => reset_via_gbe, + --Slow Control Port + --common registers 0x00-0x2F + REGIO_COMMON_STAT_REG_IN => common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, + REGIO_COMMON_STAT_STROBE_OUT => open, + REGIO_COMMON_CTRL_STROBE_OUT => open, + --internal data port + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + --Data port - external master (e.g. Flash or Debug) + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + --Sensors & ID + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + -- Generic stuff + TIMERS_OUT => timer, + MY_ADDRESS_OUT => open + ); + + common_stat_reg <= (others => '0'); + + +------------------------------------------------------------------------------- +-- Bus Handler +------------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"8100", 4 => x"8300", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 8, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_RX(3) => busgbeip_rx, + BUS_RX(4) => busgbereg_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + BUS_TX(3) => busgbeip_tx, + BUS_TX(4) => busgbereg_tx, + STAT_DEBUG => open + ); + +------------------------------------------------------------------------------- +-- Control Tools +------------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => flash_ncs_i, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT => spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO(9 downto 0), + ADDITIONAL_REG => additional_reg, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => ADC_NCS, + ADC_MOSI => ADC_MOSI, + ADC_MISO => ADC_MISO, + ADC_CLK => ADC_SCLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2), + TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0), + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); +-- led_off <= additional_reg(0); + + -- FlashROM external connections + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + FLASH_NCS <= flash_ncs_i; + + CS <= spi_cs(3 downto 0); + spi_miso(3 downto 0) <= MISO; + + MOSI <= spi_mosi(0) when spi_cs(0) = '0' + else spi_mosi(1) when spi_cs(1) = '0' + else spi_mosi(2) when spi_cs(2) = '0' + else spi_mosi(3) when spi_cs(3) = '0' + else '0'; + + SCK <= spi_clk(0) when spi_cs(0) = '0' + else spi_clk(1) when spi_cs(1) = '0' + else spi_clk(2) when spi_cs(2) = '0' + else spi_clk(3) when spi_cs(3) = '0' + else '1'; + + --------------------------------------------------------------------------- -- I/Os --------------------------------------------------------------------------- --HDR_IO(15 downto 0) <= (others => '0'); - HDR_IO <= debug(15 downto 0); + --HDR_IO <= debug(15 downto 0); TEST(13 downto 2) <= (others => '0'); TEST(1) <= reset_via_gbe; -- to keep things in place TEST(14) <= flash_ncs_i; FLASH_NCS <= flash_ncs_i; - flash_ncs_i <= '1'; - FLASH_SCLK <= '0'; - FLASH_MOSI <= '0'; - FLASH_HOLD <= '0'; - FLASH_WP <= '1'; - PROGRAMN <= '1'; --------------------------------------------------------------------------- -- LED -- 2.43.0