From 84cd2f62bab5752a8e1995af296474281df86f73 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 7 Mar 2018 13:39:07 +0100 Subject: [PATCH] update backplane master with no-GBE option --- backplanemaster/config.vhd | 15 ++- backplanemaster/trb3sc_master.lpf | 17 ++- backplanemaster/trb3sc_master.vhd | 189 ++++++++++++++++++++++++++---- 3 files changed, 189 insertions(+), 32 deletions(-) diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index eb23b70..8304128 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -77,15 +77,16 @@ package config is --Without GbE: -- for MII_NUMBER=11 -- port 0-8: downlinks to other FPGA --- port 9: SFP2 --- port 10: SFP1 +-- port 9: SFP2 (outer) slow control +-- port 10: SFP1 (inner) trigger +-- port 11: internal sctrl constant INTERFACE_NUM_ARR : hub_mii_t := (11,10); constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0, 1,1,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0, 1,1,1,0,0,0,0,0)); - constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1, 1,1,1,0,0,0,0,0), + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1, 0,1,1,0,0,0,0,0), (1,1,1,1,1,1,1,1,1, 1,0,0,0,0,0,0,0)); - constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0), + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0, 1,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0, 0,1,1,0,0,0,0,0)); @@ -134,9 +135,11 @@ function generateIncludedFeatures return std_logic_vector is t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 -- t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1)); - t(22 downto 17) := "0100111"; --sctrl via GbE + if INCLUDE_GBE = c_YES then + t(22 downto 16) := "0100111"; --sctrl via GbE + end if; t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); - t(28) := std_logic_vector(to_unsigned(1,1)); + t(28 downto 28) := std_logic_vector(to_unsigned(1,1)); t(27 downto 24) := std_logic_vector(to_unsigned(2-INCLUDE_GBE,4)); --num SFPs with TrbNet t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf index 6fc192d..65605d2 100644 --- a/backplanemaster/trb3sc_master.lpf +++ b/backplanemaster/trb3sc_master.lpf @@ -1,6 +1,7 @@ LOCATE COMP "THE_MEDIA_INT_MIXED/THE_SERDES/PCSD_INST" SITE "PCSB" ; LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_4_DOWN2/THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "gen_PCSD.THE_MEDIA_PCSD/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSD" ; #REGION "MEDIA_DOWN1" "R93C10D" 22 160; #REGION "MEDIA_DOWN1" "R100C40D" 15 100; @@ -16,7 +17,7 @@ REGION "MEDIA_D" "R75C19D" 40 36; LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_A" ; LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_B" ; LOCATE UGROUP "THE_MEDIA_4_DOWN2/media_interface_group" REGION "MEDIA_C" ; -#LOCATE UGROUP "THE_MEDIA_4_DOWN_D/media_interface_group" REGION "MEDIA_D" ; +LOCATE UGROUP "gen_PCSD.THE_MEDIA_PCSD/media_interface_group" REGION "MEDIA_D" ; @@ -33,7 +34,6 @@ MULTICYCLE TO CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns; MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i" 15 ns; - MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns; @@ -46,6 +46,19 @@ MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; + +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_PCSD/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_PCSD/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_PCSD/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i"; +MULTICYCLE TO CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i" 15 ns; +MULTICYCLE FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i" 15 ns; +MULTICYCLE TO CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i" 15 ns; +MULTICYCLE FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i" 15 ns; + MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns; MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns; diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index ff06daf..23527b9 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -111,9 +111,9 @@ architecture trb3sc_arch of trb3sc_master is signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, + signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; - signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, + signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; @@ -152,7 +152,20 @@ architecture trb3sc_arch of trb3sc_master is signal gsc_busy : std_logic; signal my_address : std_logic_vector(15 downto 0); signal mc_unique_id : std_logic_vector(63 downto 0); - signal reset_via_gbe : std_logic; + signal reset_via_gbe : std_logic; + + signal med_dataready_out : std_logic_vector (11-1 downto 0); + signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (11-1 downto 0); + signal med_dataready_in : std_logic_vector (11-1 downto 0); + signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (11-1 downto 0); + signal med_stat_op : std_logic_vector (11*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); + signal rdack, wrack : std_logic; + signal reset_from_net_i : std_logic; signal trig_gen_out_i : std_logic_vector(3 downto 0); signal monitor_inputs_i : std_logic_vector(17 downto 0); @@ -177,9 +190,10 @@ THE_CLOCK_RESET : entity work.clock_reset_handler port map( INT_CLK_IN => CLK_CORE_PCLK, EXT_CLK_IN => CLK_EXT_PLL_LEFT, - NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full, - NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half, - RESET_FROM_NET => med2int(INTERFACE_NUM-1).stat_op(13), + NET_CLK_FULL_IN => med2int(9).clk_full, + NET_CLK_HALF_IN => med2int(9).clk_half, + RESET_FROM_NET => reset_from_net_i, + SEND_RESET_IN => med2int(9).stat_op(15), BUS_RX => bustc_rx, BUS_TX => bustc_tx, @@ -197,7 +211,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_GREEN_OUT => LED_RJ_GREEN, DEBUG_OUT => debug_clock_reset ); - +reset_from_net_i <= med2int(9).stat_op(13) or reset_via_gbe; --------------------------------------------------------------------------- -- TrbNet Uplink @@ -217,11 +231,11 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB MEDIA_MED2INT(0) => med2int(7), MEDIA_MED2INT(1) => med2int(6), MEDIA_MED2INT(2) => med2int(5), - MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1), + MEDIA_MED2INT(3) => med2int(9), MEDIA_INT2MED(0) => int2med(7), MEDIA_INT2MED(1) => int2med(6), MEDIA_INT2MED(2) => int2med(5), - MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1), + MEDIA_INT2MED(3) => int2med(9), --Sync operation RX_DLM => open, @@ -250,6 +264,43 @@ THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB CTRL_DEBUG => open ); +--------------------------------------------------------------------------- +-- PCSD Uplink when no GbE is used +--------------------------------------------------------------------------- +gen_PCSD : if INCLUDE_GBE = c_NO generate + THE_MEDIA_PCSD : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_NO + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(10), --10 or 8 + MEDIA_INT2MED => int2med(10), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => SFP_MOD0(0), + SD_LOS_IN => SFP_LOS(0), + SD_TXDIS_OUT => SFP_TX_DIS(0), + --Control Interface + BUS_RX => bussci4_rx, + BUS_TX => bussci4_tx, + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; --------------------------------------------------------------------------- -- TrbNet Downlink @@ -350,14 +401,13 @@ end generate; -- GbE --------------------------------------------------------------------------- gen_noGBE : if INCLUDE_GBE = 0 generate - gsc_reply_read <= '1'; - gsc_init_dataready <= '0'; - SFP_TX_DIS(0) <= '1'; busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write; busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write; end generate; gen_GBE : if INCLUDE_GBE = 1 generate + signal external_reset_i : std_logic; +begin GBE : entity work.gbe_wrapper generic map( DO_SIMULATION => 0, @@ -437,10 +487,10 @@ gen_GBE : if INCLUDE_GBE = 1 generate DEBUG_OUT => open ); -end generate; + --------------------------------------------------------------------------- --- Hub +-- Hub with GbE --------------------------------------------------------------------------- THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record @@ -467,7 +517,7 @@ end generate; MEDIA_MED2INT => med2int, MEDIA_INT2MED => int2med, - --Event information coming from CTSCTS_READOUT_TYPE_OUT + --Event information coming from CTS CTS_NUMBER_OUT => cts_number, CTS_CODE_OUT => cts_code, CTS_INFORMATION_OUT => cts_information, @@ -493,7 +543,7 @@ end generate; ONEWIRE => TEMPSENS, MY_ADDRESS_OUT => my_address, UNIQUE_ID_OUT => mc_unique_id, - EXTERNAL_SEND_RESET => reset_via_gbe, + EXTERNAL_SEND_RESET => external_reset_i, BUS_RX => ctrlbus_rx, BUS_TX => ctrlbus_tx, @@ -522,16 +572,99 @@ end generate; STAT_DEBUG => open, CTRL_DEBUG => (others => '0') ); + + external_reset_i <= reset_via_gbe or med2int(INTERFACE_NUM-1).stat_op(15); +end generate; + +--------------------------------------------------------------------------- +-- Hub without GbE +--------------------------------------------------------------------------- +gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate + + THE_HUB : trb_net16_hub_base + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => MII_IS_UPLINK, + MII_IS_DOWNLINK => MII_IS_DOWNLINK, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + COMMON_STAT_REGS => common_stat_reg, + COMMON_CTRL_REGS => common_ctrl_reg, + MY_ADDRESS_OUT => my_address, + --REGIO INTERFACE + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + ONEWIRE => TEMPSENS, + ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open + ); + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; + med_dataready_in(i) <= med2int(i).dataready; + med_read_in(i) <= med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + reboot_from_gbe <= '0'; + reset_via_gbe <= '0'; +end generate; --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, others => 0), + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"b600", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 9, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -548,6 +681,7 @@ end generate; BUS_RX(4) => bussci3_rx, BUS_RX(5) => busgbeip_rx, BUS_RX(6) => busgbereg_rx, + BUS_RX(7) => bussci4_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci1_tx, @@ -555,6 +689,7 @@ end generate; BUS_TX(4) => bussci3_tx, BUS_TX(5) => busgbeip_tx, BUS_TX(6) => busgbereg_tx, + BUS_TX(7) => bussci4_tx, STAT_DEBUG => open ); @@ -627,10 +762,16 @@ do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; LED_RED <= not sed_error_i; LED_YELLOW <= debug_clock_reset(2); LED_WHITE <= led; - LED_SFP_GREEN <= not med2int(INTERFACE_NUM-1).stat_op(9) & '1'; --SFP Link Status - LED_SFP_RED <= not (med2int(INTERFACE_NUM-1).stat_op(10) or med2int(INTERFACE_NUM-1).stat_op(11)) & '1'; --SFP RX/TX - - + LED_SFP_GREEN(1) <= not med2int(9).stat_op(9); --SFP Link Status + LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11)); --SFP RX/TX +gen_led_nogbe : if INCLUDE_GBE = c_NO generate + LED_SFP_GREEN(0) <= not med2int(10).stat_op(9); --SFP Link Status + LED_SFP_RED(0) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11)); --SFP RX/TX +end generate; +gen_led_gbe : if INCLUDE_GBE = c_YES generate + LED_SFP_GREEN(0) <= '1'; + LED_SFP_RED(0) <= '1'; +end generate; --------------------------------------------------------------------------- -- LCD Data to display --------------------------------------------------------------------------- @@ -662,7 +803,7 @@ do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; end process; led(0) <= time_counter(26) and time_counter(16); - led(1) <= not reset_i; + led(1) <= not (clear_i or reset_i); -- TEST_LINE <= med_stat_debug(15 downto 0); -- 2.43.0