From 8590020a32b4e2beab369c4559e1c9561953630a Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 18 Jun 2013 22:39:51 +0200 Subject: [PATCH] added max event size --- special/handler_data.vhd | 37 ++++++++++++------- special/handler_trigger_and_data.vhd | 3 +- trb_net16_endpoint_hades_full_handler.vhd | 44 +++++++++++++++++------ trb_net_components.vhd | 1 + 4 files changed, 61 insertions(+), 24 deletions(-) diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 4e3244d..67872e9 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -10,12 +10,12 @@ use work.lattice_ecp2m_fifo.all; entity handler_data is generic( DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; - DATA_BUFFER_DEPTH : integer range 8 to 15 := 9; + DATA_BUFFER_DEPTH : integer range 8 to 15 := 12; DATA_BUFFER_WIDTH : integer range 1 to 32 := 32; - DATA_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**8; + DATA_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**12-256; TRG_RELEASE_AFTER_DATA : integer range 0 to 1 := c_YES; HEADER_BUFFER_DEPTH : integer range 8 to 15 := 9; - HEADER_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**8 + HEADER_BUFFER_FULL_THRESH : integer range 0 to 2**15-1 := 2**9-128 ); port( CLOCK : in std_logic; @@ -49,6 +49,7 @@ entity handler_data is IPU_HDR_DATA_EMPTY_OUT : out std_logic; TMG_TRG_ERROR_IN : in std_logic; + MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; --Status STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); @@ -145,7 +146,7 @@ architecture handler_data_arch of handler_data is signal tmg_trg_error_i : std_logic; signal partially_missing_i : std_logic; - + signal fee_write_overflow : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); begin assert DATA_BUFFER_FULL_THRESH < 2**DATA_BUFFER_DEPTH-2 report "Data buffer threshold too high" severity error; @@ -182,12 +183,14 @@ begin header_buffer_data_in <= x"0" & "0" & partially_missing_i & tmg_trg_error_i & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; -process(CLOCK) - begin - if rising_edge(CLOCK) then - tmg_trg_error_i <= (TMG_TRG_ERROR_IN or tmg_trg_error_i) and not header_buffer_write; - end if; - end process; + process(CLOCK) + begin + if rising_edge(CLOCK) then + tmg_trg_error_i <= (TMG_TRG_ERROR_IN or tmg_trg_error_i) and not header_buffer_write; + end if; + end process; + + partially_missing_i <= or_all(fee_write_overflow); --------------------------------------------------------------------------- @@ -195,7 +198,7 @@ process(CLOCK) --------------------------------------------------------------------------- gen_fifos : for i in 0 to DATA_INTERFACE_NUMBER-1 generate - data_buffer_write(i) <= FEE_DATA_WRITE_IN(i) when current_buffer_state(i) = BUSY else '0'; + data_buffer_write(i) <= FEE_DATA_WRITE_IN(i) and not fee_write_overflow(i) when current_buffer_state(i) = BUSY else '0'; THE_DAT_FIFO : fifo_var_oreg generic map( @@ -215,6 +218,16 @@ process(CLOCK) Full => data_buffer_full(i), AlmostFull => data_buffer_almost_full(i) ); + + process begin + wait until rising_edge(CLOCK); + if(data_counter(i) >= unsigned(MAX_EVENT_SIZE_IN)) then + fee_write_overflow(i) <= '1'; + else + fee_write_overflow(i) <= '0'; + end if; + end process; + end generate; @@ -294,7 +307,7 @@ process(CLOCK) when BUSY => buffer_state_bits(i) <= "010"; - if FEE_DATA_WRITE_IN(i) = '1' then + if FEE_DATA_WRITE_IN(i) = '1' and fee_write_overflow(i) = '0' then data_counter(i) <= data_counter(i) + to_unsigned(1,1); end if; if FEE_DATA_FINISHED_IN(i) = '1' then diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index ee6d52a..94c1ac1 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -59,7 +59,7 @@ entity handler_trigger_and_data is FEE_DATA_ALMOST_FULL_OUT : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); TMG_TRG_ERROR_IN : in std_logic; - + MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; --Status Registers STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); @@ -199,6 +199,7 @@ begin IPU_HDR_DATA_READ_IN => ipu_header_read, IPU_HDR_DATA_EMPTY_OUT => ipu_header_empty, TMG_TRG_ERROR_IN => TMG_TRG_ERROR_IN, + MAX_EVENT_SIZE_IN => MAX_EVENT_SIZE_IN, -- Status STAT_DATA_BUFFER_LEVEL => buf_STAT_DATA_BUFFER_LEVEL, STAT_HEADER_BUFFER_LEVEL => buf_STAT_HEADER_BUFFER_LEVEL, diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index b7a71c6..894e0cd 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -207,11 +207,11 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal tbuf_dataready : std_logic; signal tbuf_read_enable : std_logic; - signal dummy : std_logic_vector(300 downto 0); - signal write_enable : std_logic_vector(6 downto 0); - signal read_enable : std_logic_vector(6 downto 0); - signal last_write_enable : std_logic_vector(6 downto 0); - signal last_read_enable : std_logic_vector(6 downto 0); + signal dummy : std_logic_vector(324 downto 0); + signal write_enable : std_logic_vector(7 downto 0); + signal read_enable : std_logic_vector(7 downto 0); + signal last_write_enable : std_logic_vector(7 downto 0); + signal last_read_enable : std_logic_vector(7 downto 0); signal debug_data_handler_i : std_logic_vector(31 downto 0); signal debug_ipu_handler_i : std_logic_vector(31 downto 0); @@ -229,7 +229,8 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal stat_buffer_ready : std_logic; signal stat_buffer_unknown : std_logic; signal stat_buffer_address : std_logic_vector(4 downto 0); - + signal max_event_size : std_logic_vector(15 downto 0); + signal new_max_size : std_logic_vector(15 downto 0); begin --------------------------------------------------------------------------- @@ -357,9 +358,9 @@ begin THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0) + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", 7 => x"7111", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, 7 => 0, others => 0) ) port map( CLK => CLK, @@ -418,6 +419,7 @@ begin BUS_READ_ENABLE_OUT(4) => read_enable(4), BUS_READ_ENABLE_OUT(5) => read_enable(5), BUS_READ_ENABLE_OUT(6) => stat_buffer_read, + BUS_READ_ENABLE_OUT(7) => read_enable(6), BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT, BUS_WRITE_ENABLE_OUT(1) => dummy(0), BUS_WRITE_ENABLE_OUT(2) => write_enable(2), @@ -425,11 +427,14 @@ begin BUS_WRITE_ENABLE_OUT(4) => write_enable(4), BUS_WRITE_ENABLE_OUT(5) => write_enable(5), BUS_WRITE_ENABLE_OUT(6) => write_enable(6), + BUS_WRITE_ENABLE_OUT(7) => write_enable(7), BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2), BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34), BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96), BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260), + BUS_DATA_OUT(239 downto 224)=> new_max_size, + BUS_DATA_OUT(255 downto 240)=> dummy(307 downto 292), BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, BUS_ADDR_OUT(19 downto 16) => dbuf_addr, BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), @@ -437,6 +442,7 @@ begin BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address, BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249), + BUS_ADDR_OUT(127 downto 112)=> dummy(323 downto 308), BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(94), BUS_TIMEOUT_OUT(2) => dummy(95), @@ -444,11 +450,14 @@ begin BUS_TIMEOUT_OUT(4) => dummy(193), BUS_TIMEOUT_OUT(5) => dummy(194), BUS_TIMEOUT_OUT(6) => dummy(243), + BUS_TIMEOUT_OUT(7) => dummy(324), BUS_DATA_IN(31 downto 0) => BUS_DATA_IN, BUS_DATA_IN(63 downto 32) => dbuf_data_in, BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0), BUS_DATA_IN(223 downto 192)=> stat_buffer_i, + BUS_DATA_IN(239 downto 224)=> max_event_size, + BUS_DATA_IN(255 downto 240)=> x"0000", BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, BUS_DATAREADY_IN(1) => dbuf_dataready, BUS_DATAREADY_IN(2) => tbuf_dataready, @@ -456,6 +465,7 @@ begin BUS_DATAREADY_IN(4) => last_read_enable(4), BUS_DATAREADY_IN(5) => last_read_enable(5), BUS_DATAREADY_IN(6) => stat_buffer_ready, + BUS_DATAREADY_IN(7) => last_read_enable(7), BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, BUS_WRITE_ACK_IN(1) => '0', BUS_WRITE_ACK_IN(2) => '0', @@ -463,6 +473,7 @@ begin BUS_WRITE_ACK_IN(4) => '0', BUS_WRITE_ACK_IN(5) => '0', BUS_WRITE_ACK_IN(6) => '0', + BUS_WRITE_ACK_IN(7) => write_enable(7), BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, BUS_NO_MORE_DATA_IN(1) => '0', BUS_NO_MORE_DATA_IN(2) => '0', @@ -470,13 +481,15 @@ begin BUS_NO_MORE_DATA_IN(4) => '0', BUS_NO_MORE_DATA_IN(5) => '0', BUS_NO_MORE_DATA_IN(6) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN, BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2), BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), - BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown + BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown, + BUS_UNKNOWN_ADDR_IN(7) => '0' ); proc_ack_strobes : process(CLK) @@ -487,7 +500,15 @@ begin end if; end process; - + proc_maxeventsize : process begin + wait until rising_edge(CLK); + if RESET = '1' then + max_event_size <= std_logic_vector(to_unsigned((2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH-1),16)); + elsif write_enable(7) = '1' then + max_event_size <= new_max_size; + end if; + end process; + --------------------------------------------------------------------------- -- Data and IPU Handler --------------------------------------------------------------------------- @@ -538,6 +559,7 @@ begin FEE_DATA_ALMOST_FULL_OUT => FEE_DATA_ALMOST_FULL_OUT, TMG_TRG_ERROR_IN => tmg_trg_error_i, + MAX_EVENT_SIZE_IN => max_event_size, --Status Registers STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level, STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, diff --git a/trb_net_components.vhd b/trb_net_components.vhd index dc3e06d..1ebf32b 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -1162,6 +1162,7 @@ component handler_data is IPU_HDR_DATA_EMPTY_OUT : out std_logic; TMG_TRG_ERROR_IN : in std_logic; + MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; --Status STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); STAT_HEADER_BUFFER_LEVEL : out std_logic_vector(31 downto 0); -- 2.43.0