From 8666ac62a188907430a548252eafc2638a1d6eb2 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Mon, 3 Nov 2014 10:09:35 +0100 Subject: [PATCH] CTS: Back up TDC 1.6.3, Better constraints for design --- cts/compile_central_frankfurt.pl | 2 - cts/compile_constraints.pl | 4 +- cts/tdc_release | 2 +- cts/trb3_central.prj | 1 + cts/trb3_central.vhd | 17 ++++- cts/trb3_central_constraints_2.lpf | 106 +++++++++++------------------ cts/trb3_central_constraints_3.lpf | 36 +++++----- 7 files changed, 78 insertions(+), 90 deletions(-) diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index def132f..eaf93e1 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -133,8 +133,6 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/trce -fullname -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -system "kill %1"; - chdir ".."; diff --git a/cts/compile_constraints.pl b/cts/compile_constraints.pl index 31eaf23..5ee432c 100755 --- a/cts/compile_constraints.pl +++ b/cts/compile_constraints.pl @@ -58,7 +58,7 @@ chdir($script_dir); system("cp ../base/trb3_central_cts.lpf $workdir/$TOPNAME.lpf"); system("cat tdc_release/tdc_constraints_4.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_TDC'}; -system("cat tdc_release/unimportant_lines_constraints.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_TDC'}; +#system("cat tdc_release/unimportant_lines_constraints.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_TDC'}; system("cat cbmnet_bridge/cbmnet_bridge.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_CBMNET'}; system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); @@ -77,7 +77,7 @@ $lpf =~ s#GEN_Channels_*_Channels/sync_q_2*#GEN_Channels.*.Channels/sync_q[2]#g; $lpf =~ s#GEN_TDC(.*)The_Buffer#GEN_TDC$1Buffer_64.The_Buffer#g; $lpf =~ s#THE_TDC/GenCoarseCounter_(\d+)_TheCoarseCounter#THE_TDC/GenCoarseCounter.$1.TheCoarseCounter#g; $lpf =~ s#THE_TDC/TheReadout#THE_TDC/TheFirstReadout#g; - +$lpf =~ s#gen_DEBUG_risingEdgeDetect_1#gen_DEBUG.risingEdgeDetect_1#g; open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; print FILE $lpf; diff --git a/cts/tdc_release b/cts/tdc_release index 355ed0c..93528a3 120000 --- a/cts/tdc_release +++ b/cts/tdc_release @@ -1 +1 @@ -../tdc_releases/tdc_v1.7.1/ \ No newline at end of file +../tdc_releases/tdc_v1.6.3/ \ No newline at end of file diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 8acaa2d..ecad6c7 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -77,6 +77,7 @@ add_file -vhdl -lib work "../base/trb3_components.vhd" add_file -vhdl -lib work "../base/code/mbs_vulom_recv.vhd" add_file -vhdl -lib work "../base/code/mainz_a2_recv.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 522c646..d101326 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -828,10 +828,23 @@ begin GBE_FEE_BUSY_OUT => gbe_fee_busy, -- out std_logic; -- reg io - REGIO_IN => cbm_regio_rx, - REGIO_OUT => cbm_regio_tx +-- REGIO_IN => cbm_regio_rx, +-- REGIO_OUT => cbm_regio_tx + REGIO_ADDR_IN => cbm_regio_rx.addr, + REGIO_DATA_IN => cbm_regio_rx.data, + REGIO_TIMEOUT_IN => cbm_regio_rx.timeout, + REGIO_READ_ENABLE_IN => cbm_regio_rx.read, + REGIO_WRITE_ENABLE_IN => cbm_regio_rx.write, + + REGIO_DATA_OUT => cbm_regio_tx.data, + REGIO_DATAREADY_OUT => cbm_regio_tx.rack, + REGIO_WRITE_ACK_OUT => cbm_regio_tx.wack, + REGIO_NO_MORE_DATA_OUT => cbm_regio_tx.nack, + REGIO_UNKNOWN_ADDR_OUT => cbm_regio_tx.unknown ); + cbm_regio_tx.ack <= cbm_regio_tx.rack or cbm_regio_tx.wack; + SFP_RATE_SEL(1) <= '1'; -- not supported by SFP, but in general, this should be the correct setting LED_TRIGGER_GREEN <= not cbm_link_active_i; LED_TRIGGER_RED <= '0'; diff --git a/cts/trb3_central_constraints_2.lpf b/cts/trb3_central_constraints_2.lpf index 8bcdabb..70e1a17 100644 --- a/cts/trb3_central_constraints_2.lpf +++ b/cts/trb3_central_constraints_2.lpf @@ -6,28 +6,42 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# SYSCONFIG MCCLK_FREQ=20 ; + FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ; # FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ; FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; # FREQUENCY PORT CLK_EXT_3 10 MHz; # FREQUENCY PORT CLK_EXT_4 10 MHz; -FREQUENCY NET "clk_200_i" 200.000000 MHz ; -FREQUENCY NET "clk_100_i_c" 100.000000 MHz ; -FREQUENCY NET "cts_trigger_out" 100.000000 MHz ; -FREQUENCY NET "GBE/serdes_rx_clk_c" 125.000000 MHz ; -FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.000000 MHz ; -FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.000000 MHz ; -FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.000000 MHz ; -FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.000000 MHz ; -FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.000000 MHz ; -FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" 250.000000 MHz ; -FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" 250.000000 MHz ; -FREQUENCY NET "cbm_clk_i_c" 125.000000 MHz ; + +FREQUENCY NET "GEN_CTS.THE_CTS/cts_trigger_out" 100.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; +FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/cbm_clk_i_c" 125.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.0 MHz; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; +FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUT" 250.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; +FREQUENCY NET "osc_int" 20.0 MHz; +FREQUENCY PORT "CLK_PCLK_RIGHT" 200.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.1.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.2.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.3.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.4.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.5.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; +FREQUENCY NET "GEN_TDC.THE_TDC/ReferenceChannel/Channel200/FSM_RD_STATE[2]" 100.0 MHz; + + + ################################################################# # Reset Nets ################################################################# GSR_NET NET "GSR_N"; + ################################################################# # Locate Serdes and media interfaces ################################################################# @@ -36,17 +50,21 @@ LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCS LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSC" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; + MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; -MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; +#MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; + REGION "MEDIA_UPLINK" "R92C90" 22 76 DEVSIZE; LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; + #REGION "MEDIA_ONBOARD" "R90C122" 20 40; #MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; #SPI Interface + REGION "REGION_SPI" "R9C95D" 20 20 DEVSIZE; LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; #LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; @@ -54,8 +72,10 @@ LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; # UGROUP "cts_group" # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; + MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20.000000 ns ; MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20.000000 ns ; + #TrbNet Hub REGION "REGION_IOBUF" "R35C35D" 65 85 DEVSIZE; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; @@ -103,6 +123,7 @@ LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF. LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; + #GbE Part UGROUP "tsmac" BLKNAME GBE/imp_gen.MAC @@ -120,7 +141,7 @@ UGROUP "gbe_rx_tx" BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR BLKNAME GBE/setup_imp_gen.SETUP; - #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; +#REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; #REGION "MED0" "R81C30D" 34 40 DEVSIZE; #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE; @@ -218,58 +239,11 @@ PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; -BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; -BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; - -# CBMNET -LOCATE COMP "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; -DEFINE BUS cbm_rx_data - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[0]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[1]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[2]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[3]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[4]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[5]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[6]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[7]" - NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[8]"; -DEFINE BUS cbm_tx_data - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[0]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[1]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[2]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[3]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[4]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[5]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[6]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[7]" - NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[8]"; - -PRIORITIZE BUS "cbm_rx_data" 100 ; -PRIORITIZE BUS "cbm_tx_data" 100 ; - -MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_TX_GEAR/data_in_buf250_0_i*" 2 X; -MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/delay_clock_buf_i" 2 X; -MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/data_out_buf125_i*" 2 X; - -BLOCK NET "cbm_phy_debug*" ; -REGION "REGIONTDCPLACEHOLDER" "R2C115D" 31 67 DEVSIZE; -PROHIBIT REGION "REGIONTDCPLACEHOLDER" ; - -#PROHIBIT PRIMARY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" ; -#PROHIBIT SECONDARY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" ; -#PROHIBIT PRIMARY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" ; -#PROHIBIT SECONDARY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" ; +#BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; +#BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; -UGROUP "CBM_PHY_UGROUP" BBOX 13 26 - BLKNAME GEN_CBMNET.THE_CBM_PHY - BLKNAME GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR - BLKNAME GEN_CBMNET.THE_CBM_PHY/THE_TX_GEAR; -LOCATE UGROUP "CBM_PHY_UGROUP" SITE "R105C110D" ; +LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R105C110D"; +LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R76C85D"; +LOCATE COMP "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; -UGROUP "CBMNET_group" BBOX 36 50 -# BLKNAME GEN_CBMNET.THE_CBMNET_READOUT - BLKNAME GEN_CBMNET.THE_CBM_ENDPOINT - BLKNAME GEN_CBMNET.THE_DLM_REFLECT - BLKNAME GEN_CBMNET.THE_SYNC_MODULE; -LOCATE UGROUP "CBMNET_group" SITE "R80C85D" ; diff --git a/cts/trb3_central_constraints_3.lpf b/cts/trb3_central_constraints_3.lpf index 6ea9981..b703e58 100644 --- a/cts/trb3_central_constraints_3.lpf +++ b/cts/trb3_central_constraints_3.lpf @@ -9,32 +9,32 @@ SYSCONFIG MCCLK_FREQ=20 ; FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ; # FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ; -FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; +#FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ; +#FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; # FREQUENCY PORT CLK_EXT_3 10 MHz; # FREQUENCY PORT CLK_EXT_4 10 MHz; +FREQUENCY PORT "CLK_GPLL_RIGHT" 125.0 MHz; +FREQUENCY PORT "CLK_PCLK_RIGHT" 200.0 MHz; +FREQUENCY PORT "JINLVDS[0]" 200.0 MHz; FREQUENCY NET "GEN_CTS.THE_CTS/cts_trigger_out" 100.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUTz" 250.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; -FREQUENCY NET "osc_int" 20.0 MHz; -FREQUENCY PORT "CLK_PCLK_RIGHT" 200.0 MHz; +FREQUENCY NET "osc_int" 200.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.1.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.2.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.3.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.4.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; -FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.5.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/ReferenceChannel/Channel200/FSM_RD_STATE[2]" 100.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUTz" 250.0 MHz; - ################################################################# # Reset Nets @@ -50,17 +50,16 @@ LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSC" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; +UGROUP "THE_RESET_HANDLER_GRP" BLKNAME THE_RESET_HANDLER; MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; #MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; #REGION "MEDIA_UPLINK" "R100C115D" 20 60 DEVSIZE; -LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +#LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +#LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; #LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; -UGROUP "THE_MEDIA_ONBOARD_GROUP" BBOX 23 56 - BLKNAME THE_MEDIA_ONBOARD; -LOCATE UGROUP "THE_MEDIA_ONBOARD_GROUP" SITE "R100C125D" ; + @@ -79,8 +78,8 @@ LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; -MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20.000000 ns ; -MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20.000000 ns ; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm.THE_MBS/trg_sync" 20.000000 ns ; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm.THE_MBS/error_reg" 20.000000 ns ; #TrbNet Hub REGION "REGION_IOBUF" "R35C20D" 65 85 DEVSIZE; @@ -248,8 +247,11 @@ PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; #BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; #BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; -LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R100C100D"; +LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R100C118D"; LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R42C106D"; LOCATE COMP "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; +UGROUP "THE_MEDIA_ONBOARD_GROUP" BBOX 25 45 + BLKNAME THE_MEDIA_ONBOARD; +LOCATE UGROUP "THE_MEDIA_ONBOARD_GROUP" SITE "R98C75D" ; \ No newline at end of file -- 2.43.0