From 86cc64d6d19089c6eb84a507bc0fdb2908fe6cb1 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 10 Apr 2014 15:03:10 +0200 Subject: [PATCH] few bugfixes to USB sctrl --- pulser/lcd_config.vhd | 2 +- pulser/padiwa_pulser.vhd | 4 ++-- source/lcd.vhd | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pulser/lcd_config.vhd b/pulser/lcd_config.vhd index d7fcb02..2fa1b80 100644 --- a/pulser/lcd_config.vhd +++ b/pulser/lcd_config.vhd @@ -7,7 +7,7 @@ package lcd_config is type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); - constant dataram : data_t := ( + constant dataram_pack : data_t := ( x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", diff --git a/pulser/padiwa_pulser.vhd b/pulser/padiwa_pulser.vhd index d53a57e..4c4b8dd 100644 --- a/pulser/padiwa_pulser.vhd +++ b/pulser/padiwa_pulser.vhd @@ -80,7 +80,7 @@ THE_PLL : entity work.pll --------------------------------------------------------------------------- THE_UART : entity work.uart_sctrl port map( - CLK => clk_i, + CLK => clk_osc, RESET => '0', UART_RX => SPARE_LINE(0), UART_TX => SPARE_LINE(2), @@ -97,7 +97,7 @@ THE_UART : entity work.uart_sctrl PROC_REGISTERS : process begin - wait until rising_edge(clk_i); + wait until rising_edge(clk_osc); if bus_write= '1' then if uart_addr = x"01" then lcd_data_i(31 downto 0) <= uart_rx_data; diff --git a/source/lcd.vhd b/source/lcd.vhd index 8384d5f..71f2c39 100644 --- a/source/lcd.vhd +++ b/source/lcd.vhd @@ -157,6 +157,8 @@ constant fontram : fontram_t := ( type initdc_t is array (0 to 15) of std_logic; constant initdc : initdc_t := ('0','1','0','1','0','0','1','1','1','1','0','1','1','1','1','0'); + constant dataram: data_t := dataram_pack; + signal timer : unsigned(27 downto 0) := (others => '0'); --2**16: 2.5ms --2**20: 40ms -- 2.43.0