From 870d82122f3c1a6e29e26b95147484f19d496694 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Fri, 22 Dec 2017 13:10:18 +0100 Subject: [PATCH] clocking for mupix through pll and ddr resources. --- base/trb3_periph_mupix8.lpf | 4 +- mupix/Mupix8/cores/pll_mupix_main.ipx | 8 ++ mupix/Mupix8/cores/pll_mupix_main.lpc | 69 +++++++++++++++++ mupix/Mupix8/cores/pll_mupix_main.vhd | 95 ++++++++++++++++++++++++ mupix/Mupix8/trb3_periph.prj | 1 + mupix/Mupix8/trb3_periph.vhd | 44 +++++++++-- mupix/Mupix8/trb3_periph_constraints.lpf | 5 +- 7 files changed, 215 insertions(+), 11 deletions(-) create mode 100644 mupix/Mupix8/cores/pll_mupix_main.ipx create mode 100644 mupix/Mupix8/cores/pll_mupix_main.lpc create mode 100644 mupix/Mupix8/cores/pll_mupix_main.vhd diff --git a/base/trb3_periph_mupix8.lpf b/base/trb3_periph_mupix8.lpf index b152f7c..ddc6149 100644 --- a/base/trb3_periph_mupix8.lpf +++ b/base/trb3_periph_mupix8.lpf @@ -5,11 +5,11 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Clock I/O ################################################################# -#LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; +LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20"; #LOCATE COMP "CLK_PCLK_LEFT" SITE "M4"; LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18"; LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10"; -LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; +#LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1"; #LOCATE COMP "CLK_GPLL_LEFT" SITE "U25"; DEFINE PORT GROUP "CLK_group" "CLK*" ; diff --git a/mupix/Mupix8/cores/pll_mupix_main.ipx b/mupix/Mupix8/cores/pll_mupix_main.ipx new file mode 100644 index 0000000..01dd05b --- /dev/null +++ b/mupix/Mupix8/cores/pll_mupix_main.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/mupix/Mupix8/cores/pll_mupix_main.lpc b/mupix/Mupix8/cores/pll_mupix_main.lpc new file mode 100644 index 0000000..e1178a6 --- /dev/null +++ b/mupix/Mupix8/cores/pll_mupix_main.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_mupix_main +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=12/22/2017 +Time=11:58:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=200 +Div=8 +ClkOPBp=0 +Post=8 +U_OFrq=125 +OP_Tol=0.0 +OFrq=125.000000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=5 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=2.739454 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_mupix_main -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/mupix/Mupix8/cores/pll_mupix_main.vhd b/mupix/Mupix8/cores/pll_mupix_main.vhd new file mode 100644 index 0000000..4b41040 --- /dev/null +++ b/mupix/Mupix8/cores/pll_mupix_main.vhd @@ -0,0 +1,95 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.6.0.83.4 +-- Module Version: 5.7 +--/home/soft/lattice/diamond/3.6_x64/ispfpga/bin/lin64/scuba -w -n pll_mupix_main -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Fri Dec 22 11:58:04 2017 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_mupix_main is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); +end pll_mupix_main; + +architecture Structure of pll_mupix_main is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 5, CLKI_DIV=> 8, + FIN=> "200.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_mupix_main is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/mupix/Mupix8/trb3_periph.prj b/mupix/Mupix8/trb3_periph.prj index 971e3c1..7133eae 100644 --- a/mupix/Mupix8/trb3_periph.prj +++ b/mupix/Mupix8/trb3_periph.prj @@ -143,6 +143,7 @@ add_file -vhdl -lib work "../../../trbnet/media_interfaces/trb_net16_med_ecp3_sf #ip cores for mupix design add_file -vhdl -lib "work" "../../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "cores/pll_mupix_main.vhd" #MuPix Files add_file -vhdl -lib "work" "trb3_periph.vhd" diff --git a/mupix/Mupix8/trb3_periph.vhd b/mupix/Mupix8/trb3_periph.vhd index ac9eb2b..eda27b7 100644 --- a/mupix/Mupix8/trb3_periph.vhd +++ b/mupix/Mupix8/trb3_periph.vhd @@ -20,10 +20,10 @@ use ecp3.components.all; entity trb3_periph is port( --Clocks - CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + --CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA --CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz --CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL left! - --CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! + CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! --Trigger TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out @@ -112,8 +112,7 @@ entity trb3_periph is --attribute syn_useioff of DAC_SDI : signal is true; --attribute syn_useioff of DAC_SCK : signal is true; --attribute syn_useioff of DAC_CS : signal is true; - - + end entity; @@ -198,6 +197,12 @@ architecture trb3_periph_arch of trb3_periph is SLV_UNKNOWN_ADDR_OUT : out std_logic); end component resethandler; + component pll_mupix_main + port (CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + end component; + --Constants constant REGIO_NUM_STAT_REGS : integer := 5; constant REGIO_NUM_CTRL_REGS : integer := 3; @@ -205,6 +210,10 @@ architecture trb3_periph_arch of trb3_periph is attribute syn_keep : boolean; attribute syn_preserve : boolean; + attribute ODDRAPPS : string; + attribute ODDRAPPS of mupix_oddr_1 : label is "SCLK_ALIGNED"; + attribute ODDRAPPS of mupix_oddr_2 : label is "SCLK_ALIGNED"; + --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL @@ -345,6 +354,7 @@ architecture trb3_periph_arch of trb3_periph is --dummy signal dummy_counter : integer range 0 to 7 := 0; + signal mupix_clk_i : std_logic; begin @@ -381,7 +391,7 @@ begin --------------------------------------------------------------------------- THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_GPLL_RIGHT, + CLK => CLK_PCLK_RIGHT, RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, @@ -781,8 +791,28 @@ begin SLV_NO_MORE_DATA_OUT => resethandler_regio_no_more_data_out_0, SLV_UNKNOWN_ADDR_OUT => resethandler_regio_unknown_addr_out_0); - clkext <= clk_100_i; - clkref <= clk_100_i; + --clkext <= clk_100_i; + --clkref <= clk_100_i; + + mupix_main_pll_1 : pll_mupix_main + port map ( + CLK=> CLK_PCLK_RIGHT, + CLKOP=> mupix_clk_i, + LOCK=> open); + + mupix_oddr_1 : ODDRXD1 + port map( + SCLK => mupix_clk_i, + DA => '1', + DB => '0', + Q => clkext); + + mupix_oddr_2 : ODDRXD1 + port map( + SCLK => mupix_clk_i, + DA => '1', + DB => '0', + Q => clkref); --dummy process to test syncres dummy_proc : process(clk_100_i) diff --git a/mupix/Mupix8/trb3_periph_constraints.lpf b/mupix/Mupix8/trb3_periph_constraints.lpf index 8d560a8..677710b 100644 --- a/mupix/Mupix8/trb3_periph_constraints.lpf +++ b/mupix/Mupix8/trb3_periph_constraints.lpf @@ -8,10 +8,11 @@ SYSCONFIG MCCLK_FREQ = 20; - #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + USE PRIMARY NET "CLK_PCLK_RIGHT_c"; ################################################################# # Reset Nets -- 2.43.0