From 8788a5ac14ed18134eec29be8875b133f91aea04 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 29 Jun 2010 20:12:15 +0000 Subject: [PATCH] *** empty log message *** --- compile_frankfurt.pl | 2 +- design/mdc_oepb_pack.vhd | 26 +- design/mode_line_multiplexer.vhd | 87 +- design/trigger_distributor.vhd | 532 +++--------- design2/control_line_handle.vhd | 304 +++++++ design2/data_handler.vhd | 172 ++++ design2/initialization_RAM.vhd | 462 +++++++++++ design2/load_mode_line.vhd | 459 ++++++++++ design2/load_tdc_setup.vhd | 589 +++++++++++++ design2/mdc_control.vhd | 461 +++++++++++ design2/mdc_oepb_pack.vhd | 385 +++++++++ design2/send_token_to_mb.vhd | 209 +++++ design2/tdc_readout.vhd | 183 ++++ design2/trigger_begrun_state.vhd | 347 ++++++++ design2/trigger_handler.vhd | 198 +++++ mdc_oepb.prj | 58 +- mdc_oepb.vhd | 1336 +++++++++++------------------- mdc_oepb_testbench.vhd | 249 ++++++ 18 files changed, 4689 insertions(+), 1370 deletions(-) create mode 100644 design2/control_line_handle.vhd create mode 100644 design2/data_handler.vhd create mode 100644 design2/initialization_RAM.vhd create mode 100644 design2/load_mode_line.vhd create mode 100644 design2/load_tdc_setup.vhd create mode 100644 design2/mdc_control.vhd create mode 100644 design2/mdc_oepb_pack.vhd create mode 100644 design2/send_token_to_mb.vhd create mode 100644 design2/tdc_readout.vhd create mode 100644 design2/trigger_begrun_state.vhd create mode 100644 design2/trigger_handler.vhd create mode 100644 mdc_oepb_testbench.vhd diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index a84ba04..223acc5 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -12,7 +12,7 @@ use Data::Dumper; use warnings; use strict; -my $lattice_path = '/d/sugar/lattice/ispLever7.2/isptools/'; +my $lattice_path = '/d/sugar/lattice/ispLEVER8.0/isptools/'; my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; #my $synplify_path = '/home/hadaq/bin/'; diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd index 35ea382..3bee392 100644 --- a/design/mdc_oepb_pack.vhd +++ b/design/mdc_oepb_pack.vhd @@ -13,9 +13,6 @@ component mdc_addon_daq_bus_0 CLK : in std_logic; --A_ADD : inout std_logic_vector(8 downto 0); RESET : in std_logic; - A_ADS_0 : in std_logic; - A_ADS_1 : in std_logic; - A_ADS_2 : in std_logic; -- A_AOD : inout std_logic; A_ACK : in std_logic; A_CMS : out std_logic; @@ -24,14 +21,6 @@ component mdc_addon_daq_bus_0 A_GDE : out std_logic; A_RDO : in std_logic; A_RESERV : in std_logic; - A_DRA : out std_logic; - A_DRB_1 : out std_logic; - A_DRB_2 : out std_logic; - A_DRE : out std_logic; - A_ENB_1 : out std_logic; - A_ENB_2 : out std_logic; - A_ENR_1 : out std_logic; - A_ENR_2 : out std_logic; A_FET_ENABLE : out std_logic; A_REN : out std_logic; A_MOD : out std_logic; @@ -40,8 +29,6 @@ component mdc_addon_daq_bus_0 A_WRM : out std_logic; TOKEN_TO_MUX_OUT : out std_logic; TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); - LA : out std_logic_vector(31 downto 0); - D : out std_logic_vector(6 downto 0); A_RDO_OUT : out std_logic; ROC1_WRITTEN_OUT : out std_logic; DATA_TYPE_SELECT_IN : in std_logic_vector(15 downto 0); @@ -74,6 +61,7 @@ component mdc_addon_daq_bus_0 DEBUG_REGISTER_5_BUS_0 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_6_BUS_0 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_7_BUS_0 : out std_logic_vector(7 downto 0); + DEBUG_REGISTER_HANDLE_TLD : out std_logic_vector(32 downto 0); ------------------------------------------------------------------------------- -- TRB net connections ------------------------------------------------------------------------------- @@ -142,8 +130,6 @@ component mdc_addon_daq_bus_0 A_RDM : out std_logic; --ready TO first motherboard A_GDE : out std_logic; --global disable A_RDO : in std_logic; --ready FROM first motherboard - A_DRE : out std_logic; --address/data line enable - A_ENR_1 : out std_logic; --A_GDE enable A_MOD : out std_logic; -- TDC working mode A_RES : out std_logic; -- TDC working mode @@ -161,7 +147,6 @@ component mdc_addon_daq_bus_0 RAM_READ_ENABLE_IN : in std_logic; RAM_WRITE_ENABLE_IN : in std_logic; - -- test pins connected to HPLA DEBUG_REGISTER : out std_logic_vector(24 downto 0); ENABLE_MODE_LINE : in std_logic_vector(3 downto 0); ROC1_WRITTEN : out std_logic; @@ -187,7 +172,6 @@ component mdc_addon_daq_bus_0 A_ACK : in std_logic; A_DST : in std_logic; -- A_RDO : in std_logic; - A_DRE : out std_logic; TOKEN_IN : in std_logic_vector(3 downto 0); INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); ------------------------------------------------------------------------------- @@ -356,4 +340,12 @@ component xor2test Input : in std_logic_vector( 3 downto 0)); end component; +component debug_memory + port (Data: in std_logic_vector(17 downto 0); Clock: in std_logic; + WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); Empty: out std_logic; + Full: out std_logic); +end component; + + end package mdc_oepb_pack; diff --git a/design/mode_line_multiplexer.vhd b/design/mode_line_multiplexer.vhd index bc56ce3..e0c0eec 100644 --- a/design/mode_line_multiplexer.vhd +++ b/design/mode_line_multiplexer.vhd @@ -13,24 +13,24 @@ entity mode_line_multiplexer is CLK : in std_logic; --for testing --mode lines input from "trigger_begrun" - A_MOD_TB : in std_logic; -- TDC working mode - A_RES_TB : in std_logic; -- TDC working mode + A_MOD_TB : in std_logic; -- TDC working mode + A_RES_TB : in std_logic; -- TDC working mode A_TOK_TB : in std_logic; -- TDC working mode A_WRM_TB : in std_logic; -- TDC working mode A_RDM_TB : in std_logic; --ready TO first motherboard A_RDO_TB : out std_logic; --ready FROM first motherboard A_GDE_TB : in std_logic; --global disable --mode lines input from from "send_token" - A_MOD_ST : in std_logic; -- TDC working mode - A_RES_ST : in std_logic; -- TDC working mode + A_MOD_ST : in std_logic; -- TDC working mode + A_RES_ST : in std_logic; -- TDC working mode A_TOK_ST : in std_logic; -- TDC working mode A_WRM_ST : in std_logic; -- TDC working mode A_RDM_ST : in std_logic; --ready TO first motherboard A_RDO_ST : out std_logic; --ready FROM first motherboard A_GDE_ST : in std_logic; --global disable --mode lines to from MB - A_MOD : out std_logic; -- TDC working mode - A_RES : out std_logic; -- TDC working mode + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode A_TOK : out std_logic; -- TDC working mode A_WRM : out std_logic; -- TDC working mode A_RDM : out std_logic; --ready TO first motherboard @@ -48,50 +48,41 @@ architecture behavioral of mode_line_multiplexer is begin -- behavioral - process (ENABLE_MODE_LINE, A_RDO, - A_MOD_TB, A_RES_TB, A_TOK_TB, A_WRM_TB, A_RDM_TB, - A_MOD_ST, A_RES_ST, A_TOK_ST, A_WRM_ST, A_RDM_ST, - A_GDE_ST,A_GDE_TB,CLK) + process (CLK) + begin + if rising_edge(CLK) then + case ENABLE_MODE_LINE is -begin - if rising_edge(CLK) then - + when x"D" => --begrun trigger + DEBUG_REGISTER <= "0000"; + A_MOD <= A_MOD_TB; + A_RES <= A_RES_TB; + A_TOK <= A_TOK_TB; + A_WRM <= A_WRM_TB; + A_RDM <= A_RDM_TB; --token out + A_RDO_TB <= A_RDO; --token back + A_GDE <= A_GDE_TB; - case ENABLE_MODE_LINE is - - when x"D" => --begrun trigger - DEBUG_REGISTER <= "0000"; - A_MOD <= A_MOD_TB; - A_RES <= A_RES_TB; - A_TOK <= A_TOK_TB; - A_WRM <= A_WRM_TB; - A_RDM <= A_RDM_TB; --token out - A_RDO_TB <= A_RDO; --token back - A_GDE <= A_GDE_TB; + when x"1" => --normal trigger + DEBUG_REGISTER <= "0001"; + A_MOD <= A_MOD_ST; + A_RES <= A_RES_ST; + A_TOK <= A_TOK_ST; + A_WRM <= A_WRM_ST; + A_RDM <= A_RDM_ST; --token + A_RDO_ST <= A_RDO; --token back + A_GDE <= A_GDE_ST; - when x"1" => --normal trigger - DEBUG_REGISTER <= "0001"; - A_MOD <= A_MOD_ST; - A_RES <= A_RES_ST; - A_TOK <= A_TOK_ST; - A_WRM <= A_WRM_ST; - A_RDM <= A_RDM_ST; --token - A_RDO_ST <= A_RDO; --token back - A_GDE <= A_GDE_ST; - - when others => --in case wrong trigger the trigger_begrun is connected to out - A_MOD <= A_MOD_ST; - A_RES <= A_RES_ST; - A_TOK <= A_TOK_ST; - A_WRM <= A_WRM_ST; - A_RDM <= A_RDM_ST; --token - A_RDO_ST <= A_RDO; --token back - A_GDE <= A_GDE_ST; - - - end case; - end if; - -end process; + when others => --in case wrong trigger the trigger_begrun is connected to out + A_MOD <= A_MOD_ST; + A_RES <= A_RES_ST; + A_TOK <= A_TOK_ST; + A_WRM <= A_WRM_ST; + A_RDM <= A_RDM_ST; --token + A_RDO_ST <= A_RDO; --token back + A_GDE <= A_GDE_ST; + end case; + end if; + end process; end behavioral; diff --git a/design/trigger_distributor.vhd b/design/trigger_distributor.vhd index 4d19a37..f16df2c 100644 --- a/design/trigger_distributor.vhd +++ b/design/trigger_distributor.vhd @@ -1,311 +1,137 @@ -------------------------------------------------------------------------------- --- Attilio Tarantola --- Create Date: 18/11/2007 --- Description: When I receive a trigger this entity distribute it to all bus/buses, wait --- for the token back. --- --- 29/02/2008 I add the calibration states. When a calibration trigger is --- retrived, it sends the cal trigger to all buses, the CAL parameters are loaded --- and data is collected. The input A_RDO_IN is the AND between all buses --- This entity generates the token back for TRB. --- INIT_ALL_BUSES_OUT <= "1" normal trigger --- INIT_ALL_BUSES_OUT <= "B" begrun trigger --- INIT_ALL_BUSES_OUT <= "C" calibration trigger --- INIT_ALL_BUSES_OUT <= "0" idle --- --- 01/12/2008 I start adapting to the OEPB -------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.all; -use IEEE.STD_LOGIC_ARITH.all; -use IEEE.STD_LOGIC_UNSIGNED.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. --- library UNISIM; --- use UNISIM.VComponents.all; entity trigger_distributor is port( - CLK : in std_logic; - RESET : in std_logic; - INTERNAL_RESET_IN : in std_logic; - - A_RDO_IN : in std_logic; - TRIGGER_IN : in std_logic; - TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0); - INIT_ALL_BUSES_OUT : out std_logic_vector(3 downto 0); - ROC1_WRITTEN_IN : in std_logic; - TOKEN_TO_TRB_OUT : out std_logic; - CAL_TRIGGER_REGISTER_IN : in std_logic_vector(15 downto 0); - - DEBUG_REGISTER_OUT : out std_logic_vector(31 downto 0); - LED_CNT_1_OUT : out std_logic; - LED_CNT_2_OUT : out std_logic; - LED_ERROR_OUT : out std_logic; - LED_GOOD_OUT : out std_logic); -end trigger_distributor; + CLK : in std_logic; + RESET : in std_logic; + + TRG_VALID_BEGRUN_IN : in std_logic; --begin run pseudo "trigger" + TRG_VALID_TIMING_IN : in std_logic; --treated as normal readout + TRG_VALID_NOTIMING_IN : in std_logic; --treated as calibration + + DO_BEGRUN_OUT : out std_logic; --start begin run + DO_READOUT_OUT : out std_logic; --start readout + DO_CALIB_OUT : out std_logic; --start calibration + + FINISHED_BEGRUN : in std_logic; --TDC are initialized + FINISHED_READOUT : in std_logic; --token received back after readout + FINISHED_CALIB : in std_logic; --token received back after calib + + STAT_DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; architecture behavioral of trigger_distributor is - - constant WAIT_AFTER_ROC1_IS_LOADED : std_logic_vector(12 downto 0) := "0011111010000"; + + constant WAIT_AFTER_BEGRUN : unsigned(11 downto 0) := x"7D0"; type state_type is (idle_state, normal_trigger_state, begrun_trigger_state, wait_roc1_written, wait_token_back_state, roc1_written_state, send_token_state, ---calibration state calibration_state, wait_cal1_written); - signal current_state, next_state : state_type; - - signal reset_calibration_counter : std_logic; - signal reg_init_all_buses, next_init_all_buses : std_logic_vector(3 downto 0); - signal reg_token_to_trb, next_token_to_trb : std_logic; - signal counter_number_of_trigger : std_logic_vector(11 downto 0); - signal up_number_of_trigger : std_logic; - signal register_trigger_condition : std_logic_vector(15 downto 0); - signal internal_calibration_trigger : std_logic; - signal reg_trigger_type_in : std_logic_vector(3 downto 0); - signal reg_trigger_in : std_logic; - signal reg_debug_register, next_debug_register : std_logic_vector(3 downto 0); - signal debug_normal_trigger_number, debug_calibration_trigger_number : std_logic_vector(7 downto 0); - signal debug_token_back_number : std_logic_vector(7 downto 0); - signal pulse_a_rdo_in : std_logic; - -- signal pulse_begin_run_trigger : std_logic; - signal not_reset : std_logic; - signal counter_wait_after_roc1 : std_logic_vector(12 downto 0); - signal pulse_internal_reset_in : std_logic; -------------------------------------------------------------------------------- --- I use this exeption for naming signal(they should be lower case in general). In this case --- capital letters with "reg" or "next" at the beginning. -------------------------------------------------------------------------------- - signal reg_LED_CNT_1_OUT, reg_LED_CNT_2_OUT : std_logic; - signal reg_LED_ERROR_OUT, reg_LED_GOOD_OUT : std_logic; - signal next_LED_CNT_1_OUT, next_LED_CNT_2_OUT : std_logic; - signal next_LED_ERROR_OUT, next_LED_GOOD_OUT : std_logic; - signal reg_internal_reset_in : std_logic; - - component edge_to_pulse - port ( - CLOCK : in std_logic; - ENABLE_CLK_IN : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component; - -begin -- behavioral - - -------------------------------------------------------------------------------- --- it creates a pulse of 10ns from the input signal. --- A_RDO_IN is the token back. -------------------------------------------------------------------------------- - A_RDO_PULSE : edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN => '1', - SIGNAL_IN => A_RDO_IN, - PULSE_OUT => pulse_a_rdo_in); + + signal counter_wait_after_roc1 : unsigned(11 downto 0); + + signal current_state, next_state : state_type; + signal state_bits : std_logic_vector(3 downto 0); + signal do_begrun_i, next_do_begrun_i : std_logic; + signal do_readout_i, next_do_readout_i : std_logic; + signal do_calib_i, next_do_calib_i : std_logic; + +begin ------------------------------------------------------------------------------- --- it creates a pulse of 10ns from the input signal. --- After the the firmware is loaded in the FPGA, the begin run trigger is --- generated automatically and the FEE is initialized. +-- Connections to output ports ------------------------------------------------------------------------------- --- BEGIN_RUN_TRIGGER_FROM_RESET : edge_to_pulse --- port map ( --- CLOCK => CLK, --- ENABLE_CLK_IN => '1', --- SIGNAL_IN => not_reset, --- PULSE_OUT => pulse_begin_run_trigger); + DO_BEGRUN_OUT <= do_begrun_i; + DO_READOUT_OUT <= do_readout_i; + DO_CALIB_OUT <= do_calib_i; --- not_reset <= not(RESET); ------------------------------------------------------------------------------- -- Register and reset for the FSM --- Signals in the sensitivity list (CLK,RESET) are important for the simulation!! ------------------------------------------------------------------------------- - REGISTER_ADDR_DATA_MODE : process (CLK,RESET) + PROC_FSM_SYNC : process (CLK) begin if (rising_edge(CLK)) then if RESET = '1' then - current_state <= idle_state; - reg_token_to_trb <= '0'; - reg_init_all_buses <= (others => '0'); - reg_debug_register <= (others => '0'); - reg_LED_CNT_1_OUT <= '0'; - reg_LED_CNT_2_OUT <= '0'; - reg_LED_ERROR_OUT <= '0'; - reg_LED_GOOD_OUT <= '0'; + current_state <= idle_state; + do_begrun_i <= '0'; + do_readout_i <= '0'; + do_calib_i <= '0'; else - current_state <= next_state; - reg_token_to_trb <= next_token_to_trb; - reg_init_all_buses <= next_init_all_buses; - reg_debug_register <= next_debug_register; - reg_LED_CNT_1_OUT <= next_LED_CNT_1_OUT; - reg_LED_CNT_2_OUT <= next_LED_CNT_2_OUT; - reg_LED_ERROR_OUT <= next_LED_ERROR_OUT; - reg_LED_GOOD_OUT <= next_LED_GOOD_OUT; + current_state <= next_state; + do_begrun_i <= next_do_begrun_i; + do_readout_i <= next_do_readout_i; + do_calib_i <= next_do_calib_i; end if; end if; - end process REGISTER_ADDR_DATA_MODE; - - -------------------------------------------------------------------------------- --- Connections to OUTPUT ports -------------------------------------------------------------------------------- - TOKEN_TO_TRB_OUT <= reg_token_to_trb; - INIT_ALL_BUSES_OUT <= reg_init_all_buses; - DEBUG_REGISTER_OUT <= x"0000000"& reg_debug_register; - LED_CNT_1_OUT <= reg_LED_CNT_1_OUT; - LED_CNT_2_OUT <= reg_LED_CNT_2_OUT; - LED_ERROR_OUT <= reg_LED_ERROR_OUT; - LED_GOOD_OUT <= reg_LED_GOOD_OUT; + end process; -------------------------------------------------------------------------------- --- FSM: combinatorial part. It takes input trigger and distributes to other --- entities. It sends calibration trigger. --- Take care not to use inferred latches, most likely you don't want that!! --- Check the .srr report! Also here signals in the sensitivity list are --- important for simulation -------------------------------------------------------------------------------- - process (current_state, reg_trigger_in, - ROC1_WRITTEN_IN, A_RDO_IN, - counter_wait_after_roc1, reg_internal_reset_in) + PROC_FSM_COMB : process (current_state, + TRG_VALID_BEGRUN_IN, TRG_VALID_TIMING_IN, TRG_VALID_NOTIMING_IN) begin - - next_debug_register <= (others => '0'); - next_init_all_buses <= (others => '0'); - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - - next_LED_CNT_1_OUT <= '1'; --'1' is off, '0' is on - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; + next_state <= current_state; + next_do_begrun_i <= do_begrun_i; + next_do_readout_i <= do_readout_i; + next_do_calib_i <= do_calib_i; case current_state is - when idle_state => - next_debug_register <= x"1"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '0'; - next_init_all_buses <= (others => '0'); - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - if (reg_internal_reset_in = '1') then - next_state <= begrun_trigger_state; - elsif (reg_trigger_in = '1') then - if (register_trigger_condition(3 downto 0) = x"C") then - next_state <= calibration_state; - else - next_state <= normal_trigger_state; - end if; - else - next_state <= idle_state; + when idle_state => + + if TRG_VALID_BEGRUN_IN = '1' then + next_state <= begrun_trigger_state; + next_do_begrun_out <= '1'; + elsif TRG_VALID_TIMING_IN = '1' then + next_state <= normal_trigger_state; + next_do_readout_i <= '1'; + elsif TRG_VALID_NOTIMING_IN = '1' then + next_state <= calibration_state; + next_do_calib_i <= '1'; end if; -------------------------------------------------------------------------------- ---NORMAL TRIGGER -------------------------------------------------------------------------------- when normal_trigger_state => - next_debug_register <= x"2"; - next_LED_CNT_1_OUT <= '0'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; - next_init_all_buses <= X"1"; - next_token_to_trb <= '0'; - up_number_of_trigger <= '1'; - reset_calibration_counter <= '0'; - next_state <= wait_token_back_state; + next_state <= wait_token_back_state; when wait_token_back_state => - next_debug_register <= x"3"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '0'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; - next_init_all_buses <= X"0"; - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - if A_RDO_IN = '1' then - next_state <= send_token_state; - else - next_state <= wait_token_back_state; + if FINISHED_READOUT = '1' then + next_state <= idle_state; end if; when send_token_state => - next_debug_register <= x"4"; - next_LED_CNT_1_OUT <= '0'; - next_LED_CNT_2_OUT <= '0'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '1'; - next_init_all_buses <= X"0"; - next_token_to_trb <= '1'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - -- next_state <= normal_trigger_state; next_state <= idle_state; ------------------------------------------------------------------------------- -- BEGRUN TRIGGER. -- After FPGA is loaded automatically done. ------------------------------------------------------------------------------- when begrun_trigger_state => - next_debug_register <= x"5"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '0'; - next_LED_GOOD_OUT <= '1'; - next_init_all_buses <= X"D"; - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - next_state <= wait_roc1_written; + next_state <= wait_roc1_written; when wait_roc1_written => - next_debug_register <= x"6"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '0'; - next_LED_GOOD_OUT <= '1'; - - next_init_all_buses <= X"0"; - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; if ROC1_WRITTEN_IN = '1' then - next_state <= roc1_written_state; - else - next_state <= wait_roc1_written; + next_state <= roc1_written_state; end if; when roc1_written_state => - next_debug_register <= x"7"; - next_LED_CNT_1_OUT <= '0'; - next_LED_CNT_2_OUT <= '0'; - next_LED_ERROR_OUT <= '0'; - next_LED_GOOD_OUT <= '1'; - next_init_all_buses <= (others => '0'); - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '0'; - if counter_wait_after_roc1 = WAIT_AFTER_ROC1_IS_LOADED then - --next_state <= normal_trigger_state; - next_state <= idle_state; - else - next_state <= roc1_written_state; + if counter_wait_after_roc1 = WAIT_AFTER_BEGRUN then + next_state <= idle_state; end if; - + ------------------------------------------------------------------------------- --CALIBRATION TRIGGER. --When the calibration starts the REG2 is @@ -314,198 +140,64 @@ begin -- behavioral --In the entity send_token_to_mb.vhd I check the token comes back within 2msec. ------------------------------------------------------------------------------- when calibration_state => - next_debug_register <= x"8"; - next_LED_CNT_1_OUT <= '1'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '0'; - next_init_all_buses <= X"C"; --start calibration - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '1'; - next_state <= wait_cal1_written; + next_state <= wait_cal1_written; when wait_cal1_written => - next_debug_register <= x"9"; - next_LED_CNT_1_OUT <= '0'; - next_LED_CNT_2_OUT <= '1'; - next_LED_ERROR_OUT <= '1'; - next_LED_GOOD_OUT <= '0'; - next_init_all_buses <= X"0"; - next_token_to_trb <= '0'; - up_number_of_trigger <= '0'; - reset_calibration_counter <= '1'; - if A_RDO_IN = '1' then --the token comes back as for normal event - next_state <= send_token_state; - else - next_state <= wait_cal1_written; + if A_RDO_IN = '1' then + next_state <= send_token_state; end if; when others => - next_state <= idle_state; + next_state <= idle_state; end case; end process; - ------------------------------------------------------------------------------ ---Counts the number of normal trigger. This number is used to generate the ---calibration trigger internally. ---This counter is resetted after the calibration trigger is executed. ------------------------------------------------------------------------------ - process(CLK, RESET, reset_calibration_counter, up_number_of_trigger) - begin - if (rising_edge(CLK)) then - if (RESET = '1' or reset_calibration_counter = '1') then - counter_number_of_trigger <= (others => '0'); - elsif (up_number_of_trigger = '1') then - counter_number_of_trigger <= counter_number_of_trigger + 1; - else - counter_number_of_trigger <= counter_number_of_trigger; - end if; - end if; - end process; - - -------------------------------------------------------------------------------- --- CAL_TRIGGER_REGISTER_IN says how often the calibration trigger --- has to be genereted. This register is written by the TRB at startup. -------------------------------------------------------------------------------- - process (CLK, RESET) - begin - if (rising_edge(CLK)) then - if RESET = '1' then - register_trigger_condition <= (others => '0'); - else - register_trigger_condition <= CAL_TRIGGER_REGISTER_IN; - end if; - end if; - end process; - - -------------------------------------------------------------------------------- --- Register input trigger signals. They come from TRB. -------------------------------------------------------------------------------- - process (CLK, RESET) - begin - if (rising_edge(CLK)) then - if RESET = '1' then - reg_trigger_type_in <= (others => '0'); - reg_trigger_in <= '0'; - reg_internal_reset_in <= '0'; - else - reg_trigger_type_in <= TRIGGER_TYPE_IN; - reg_trigger_in <= TRIGGER_IN; - reg_internal_reset_in <= INTERNAL_RESET_IN; - end if; - end if; - end process; - - -------------------------------------------------------------------------------- --- The calibration trigger is generated every --- x"register_trigger_condition(15 downto 4)" number of normal trigger -------------------------------------------------------------------------------- --- process (CLK, RESET, register_trigger_condition) --- begin --- if (rising_edge(CLK)) then --- if (RESET = '1') then --- internal_calibration_trigger <= '0'; - --- -- elsif ( (register_trigger_condition(3 downto 0) = x"E") and --- -- (counter_number_of_trigger(11 downto 0) = register_trigger_condition(15 downto 4)) ) then --enable cal trigger --- -- internal_calibration_trigger <= '1'; - --- elsif (register_trigger_condition(3 downto 0) = x"C") then --only cal trigger --- internal_calibration_trigger <= '1'; - --- elsif (register_trigger_condition(3 downto 0) = x"D") then --disable cal trigger --- internal_calibration_trigger <= '0'; - --- else --- internal_calibration_trigger <= '0'; --- end if; --- end if; --- end process; - - -------------------------------------------------------------------------------- --- DEBUG INFO PROCESS -------------------------------------------------------------------------------- - process (CLK, RESET) - begin - if (rising_edge(CLK)) then - if (RESET = '1') then - debug_normal_trigger_number <= (others => '0'); - elsif (up_number_of_trigger = '1') then - debug_normal_trigger_number <= debug_normal_trigger_number + 1; - else - debug_normal_trigger_number <= debug_normal_trigger_number; - end if; - end if; - end process; - -------------------------------------------------------------------------------- --- DEBUG INFO PROCESS -------------------------------------------------------------------------------- - process (CLK, RESET, current_state) - begin - if (rising_edge(CLK)) then - if (RESET = '1') then - debug_calibration_trigger_number <= (others => '0'); - elsif (current_state = calibration_state) then - debug_calibration_trigger_number <= debug_calibration_trigger_number + 1; - else - debug_calibration_trigger_number <= debug_calibration_trigger_number; - end if; - end if; - end process; -------------------------------------------------------------------------------- --- DEBUG INFO PROCESSES: it counts number of token received from FEE -------------------------------------------------------------------------------- - process (CLK, RESET, pulse_a_rdo_in) - begin - if (rising_edge(CLK)) then - if RESET = '1' then - debug_token_back_number <= (others => '0'); - elsif pulse_a_rdo_in = '1' then - debug_token_back_number <= debug_token_back_number + 1; - else - debug_token_back_number <= debug_token_back_number; - end if; - end if; - end process; - ------------------------------------------------------------------------------- --- After the FEE parameters(ROC1) have been loaded an internal signal is --- generated (ROC1_WRITTEN_IN = '1'). --- After this stage the FEE can receive the --- data request. --- counter_wait_after_roc1 separates the configuration stage from the --- acquisition stage. +-- After the FEE parameters(ROC1) have been loaded, wait for 20us until +-- triggers are accepted ------------------------------------------------------------------------------- - process (CLK, RESET, current_state) + PROC_WAIT_COUNTER : process (CLK) begin if (rising_edge(CLK)) then if (RESET = '1') then counter_wait_after_roc1 <= (others => '0'); elsif current_state = roc1_written_state then - counter_wait_after_roc1 <= counter_wait_after_roc1 + 1; - else - counter_wait_after_roc1 <= counter_wait_after_roc1; + counter_wait_after_roc1 <= counter_wait_after_roc1 + to_unsigned(1,1); end if; end if; end process; -end behavioral; - - - - + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case current_state is + when idle_state => state_bits <= x"1"; + when normal_trigger_state => state_bits <= x"2"; + when wait_token_back_state => state_bits <= x"3"; + when send_token_state => state_bits <= x"4"; + when begrun_trigger_state => state_bits <= x"5"; + when wait_roc1_written => state_bits <= x"6"; + when roc1_written_state => state_bits <= x"7"; + when calibration_state => state_bits <= x"8"; + when wait_cal1_written => state_bits <= x"9"; + when others => state_bits <= x"F"; + end case; + end if; + end process; +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + STAT_DEBUG_OUT(3 downto 0) <= state_bits; + STAT_DEBUG_OUT(4) <= do_begrun_i; + STAT_DEBUG_OUT(5) <= do_readout_i; + STAT_DEBUG_OUT(6) <= do_calib_i; + STAT_DEBUG_OUT(31 downto 7) <= (others => '0'); +end behavioral; \ No newline at end of file diff --git a/design2/control_line_handle.vhd b/design2/control_line_handle.vhd new file mode 100644 index 0000000..8938e9c --- /dev/null +++ b/design2/control_line_handle.vhd @@ -0,0 +1,304 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity control_line_handle is + port( + CLK : in std_logic; + RESET : in std_logic; + --to MBO + A_ADD : out std_logic_vector(8 downto 0); --address/data line + A_AOD : out std_logic; -- address or data + A_DST : out std_logic; -- data strobe + A_RDM : out std_logic; -- ready TO first motherboard + A_GDE : out std_logic; -- global disable + A_RDO : in std_logic; -- ready FROM first motherboard + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + OUTPUT_ENABLE : out std_logic; + + --FSM control + START_CALIB_IN : in std_logic; --start calibration trigger + START_BEGRUN_IN : in std_logic; --start begrun trigger + START_READOUT_IN : in std_logic; --begin tdc readout (either calib. or trigger) + FINISHED_READOUT_IN : in std_logic; --All entities back to idle + + --Status + TOKEN_MISSING_OUT : out std_logic; --token timeout - not received back, readout finished + TOKEN_BACK_OUT : out std_logic; --token back, readout finished + FINISHED_BEGRUN_OUT : out std_logic; --finished begrun trigger + FINISHED_LOAD_CALIB_OUT : out std_logic; --finished loading calib settings, readout can be started + START_DEBUG_READOUT_OUT : out std_logic; --begrun trigger read-back settings + + --Config + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + + --Config RAM + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit + RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_TRIGGER_BEGRUN: out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_MODE : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_TDC : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_SEND_TOKEN : out std_logic_vector(31 downto 0) + ); + +end entity; + +architecture behavioral of control_line_handle is + +--signal declarations + type state_type is (idle, trigger_begrun, send_token, trigger_calibration); + + signal current_state : state_type; + signal next_state : state_type; + + signal finished_load_calib_i : std_logic; + signal finished_begrun_i : std_logic; + signal A_MOD_TB_i, A_RES_TB_i, A_TOK_TB_i, A_WRM_TB_i, A_RDM_TB_i, A_RDO_TB_i : std_logic; + signal A_MOD_ST_i, A_RES_ST_i, A_TOK_ST_i, A_WRM_ST_i, A_RDM_ST_i, A_RDO_ST_i : std_logic; + signal A_GDE_ST_i, A_GDE_TB_i : std_logic; + signal real_gde_i : std_logic; + signal tmp_gde_i : std_logic; + signal mb_initialized : std_logic; + signal next_mb_initialized : std_logic; + signal reset_send_token : std_logic; + + signal line_select : std_logic; + signal next_line_select : std_logic; + signal state_bits : std_logic_vector(3 downto 0); + + signal token_back_i : std_logic; + signal no_token_back_i : std_logic; + signal start_debug_readout_i : std_logic; + +begin + +------------------------------------------------------------------------------- +-- trigger_begrun_state +------------------------------------------------------------------------------- + + the_trg_begrun : trigger_begrun_state + port map ( + CLK => CLK, + RESET => RESET, + --MBO + A_ADD => A_ADD, + A_AOD => A_AOD, + A_DST => A_DST, + A_RDM => A_RDM_TB_i, + A_GDE => A_GDE_TB_i, + A_RDO => A_RDO_TB_i, + A_MOD => A_MOD_TB_i, + A_RES => A_RES_TB_i, + A_TOK => A_TOK_TB_i, + A_WRM => A_WRM_TB_i, + OUTPUT_ENABLE => OUTPUT_ENABLE, + --SCtrl + RAM_ADDRESS_IN => RAM_ADDRESS_IN, + RAM_DATA_IN => RAM_DATA_IN, + RAM_DATA_OUT => RAM_DATA_OUT, + RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN, + RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN, + --Trigger In + DO_BEGRUN_IN => START_BEGRUN_IN, + DO_CALIB_TRIGGER_IN => START_CALIB_IN, + --Status Out + FINISHED_BEGRUN_OUT => finished_begrun_i, + FINISHED_LOAD_CALIB_OUT => finished_load_calib_i, + START_DEBUG_READOUT_OUT => start_debug_readout_i, + --Configuration + MOTHERBOARD_TYPE_IN => MOTHERBOARD_TYPE_IN, + --Debug + DEBUG_REGISTER => DEBUG_REGISTER_TRIGGER_BEGRUN, + DEBUG_REGISTER_LOAD_MODE => DEBUG_REGISTER_LOAD_MODE, + DEBUG_REGISTER_LOAD_TDC => DEBUG_REGISTER_LOAD_TDC + ); + + THE_MUX : process (CLK) + begin + if rising_edge(CLK) then + case line_select is + when '0' => --begrun trigger or calib loading + A_MOD <= A_MOD_TB_i; + A_RES <= A_RES_TB_i; + A_TOK <= A_TOK_TB_i; + A_WRM <= A_WRM_TB_i; + A_RDM <= A_RDM_TB_i; + A_RDO_TB_i <= A_RDO; + A_GDE <= A_GDE_TB_i; + + when others => --normal trigger or calib readout + A_MOD <= A_MOD_ST_i; + A_RES <= A_RES_ST_i; + A_TOK <= A_TOK_ST_i; + A_WRM <= A_WRM_ST_i; + A_RDM <= A_RDM_ST_i; + A_RDO_ST_i <= A_RDO; + A_GDE <= real_gde_i; + end case; + end if; + end process; + + real_gde_i <= tmp_gde_i or A_GDE_ST_i; + + proc_real_gde : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or A_RDO_ST_i = '1' then + tmp_gde_i <= '0'; + elsif finished_load_calib_i = '1' then + tmp_gde_i <= '1'; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- send_token_to_mb +------------------------------------------------------------------------------- + + the_send_token : send_token_to_mb + port map ( + CLK => CLK, + RESET => reset_send_token, + DO_READOUT_IN => START_READOUT_IN, + FINISH_IN => FINISHED_READOUT_IN, + A_MOD => A_MOD_ST_i, + A_RES => A_RES_ST_i, + A_TOK => A_TOK_ST_i, + A_WRM => A_WRM_ST_i, + A_RDM => A_RDM_ST_i, + A_RDO => A_RDO_ST_i, + A_GDE => A_GDE_ST_i, + FINISHED_READOUT_OUT => token_back_i, + NO_TOKEN_BACK_OUT => no_token_back_i, + DEBUG_REGISTER => DEBUG_REGISTER_SEND_TOKEN + ); + + reset_send_token <= RESET or not mb_initialized; + + +------------------------------------------------------------------------------- +-- send_token_to_mb +------------------------------------------------------------------------------- + + + + proc_fsm_sync : process (CLK) + begin + --process + if rising_edge(CLK) then + if RESET = '1' then + current_state <= idle; + line_select <= '0'; + mb_initialized<= '0'; + else + current_state <= next_state; + line_select <= next_line_select; + mb_initialized<= next_mb_initialized; + end if; + end if; + end process; + + + proc_fsm_comb : process (current_state, finished_load_calib_i, finished_begrun_i, + START_CALIB_IN, START_BEGRUN_IN, START_READOUT_IN, + mb_initialized, line_select, token_back_i, no_token_back_i) + begin + next_state <= current_state; + next_line_select <= line_select; + next_mb_initialized <= mb_initialized; + + case current_state is + when idle => + next_line_select <= '0'; + if START_BEGRUN_IN = '1' then + next_state <= trigger_begrun; + next_line_select <= '0'; + elsif START_READOUT_IN = '1' then + next_state <= send_token; + next_line_select <= '1'; + elsif START_CALIB_IN = '1' then + next_state <= trigger_calibration; + next_line_select <= '0'; + end if; + + when trigger_begrun => + if finished_begrun_i = '1' then + next_state <= idle; + next_mb_initialized <= '1'; + end if; + + when trigger_calibration => + if finished_load_calib_i = '1' then + next_state <= idle; + end if; + + when send_token => + if token_back_i = '1' or no_token_back_i = '1' then + next_state <= idle; + end if; + + when others => + next_state <= idle; + + end case; + end process; + + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + + FINISHED_LOAD_CALIB_OUT <= finished_load_calib_i; + START_DEBUG_READOUT_OUT <= start_debug_readout_i; + + TOKEN_BACK_OUT <= token_back_i; + TOKEN_MISSING_OUT <= no_token_back_i; + FINISHED_BEGRUN_OUT <= finished_begrun_i; + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case next_state is + when idle => state_bits <= x"0"; + when trigger_begrun => state_bits <= x"1"; + when trigger_calibration => state_bits <= x"2"; + when send_token => state_bits <= x"3"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + + DEBUG_REGISTER(3 downto 0) <= state_bits; + DEBUG_REGISTER(4) <= finished_begrun_i; + DEBUG_REGISTER(5) <= finished_load_calib_i; + DEBUG_REGISTER(6) <= token_back_i; + DEBUG_REGISTER(7) <= no_token_back_i; + DEBUG_REGISTER(8) <= mb_initialized; + DEBUG_REGISTER(9) <= line_select; + DEBUG_REGISTER(10) <= tmp_gde_i; + DEBUG_REGISTER(11) <= start_debug_readout_i; + DEBUG_REGISTER(31 downto 12) <= (others => '0'); + + + +end behavioral; + + + diff --git a/design2/data_handler.vhd b/design2/data_handler.vhd new file mode 100644 index 0000000..5f108fa --- /dev/null +++ b/design2/data_handler.vhd @@ -0,0 +1,172 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity data_handler is + port( + CLK : in std_logic; + RESET : in std_logic; + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + + START_READOUT_IN : in std_logic; + FINISHED_READOUT_IN : in std_logic; + --Config + SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on + SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal + SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy + DUMMY_DATA_CONFIG : in std_logic_vector(15 downto 0); --11..0: number of debug words + --Data Input from FEE + DATA_BUS_IN : in std_logic_vector(23 downto 0); + DATA_VALID_IN : in std_logic; + --Data to Endpoint + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); +end entity; + +--gets data from TDC interface, packs into right data format, and write to data buffer + +-- reg_data_bus_out(23) <= '0'; +-- reg_data_bus_out(22 downto 19) <= FLAG_EVENT_COUNTER_IN; +-- reg_data_bus_out(18 downto 12) <= A_ADD_IN(8 downto 2); --TDC NR and TDC CH +-- reg_data_bus_out(11) <= A_RESERV_IN; --HIT NR +-- reg_data_bus_out(10 downto 9) <= A_ADD_IN(1 downto 0); --TDC DATA +-- reg_data_bus_out(8 downto 0) <= saved_data(8 downto 0);--TDC DATA + +architecture arch of data_handler is + + type state_t is (IDLE, SEND_DATA, SEND_LONG_DATA, SEND_DUMMY, FINISH); + signal current_state : state_t; + signal state_bits : std_logic_vector(3 downto 0); + + signal data_i : std_logic_vector(31 downto 0); + signal data_write_i : std_logic; + signal data_finished_i : std_logic; + + signal dummy_counter : unsigned(11 downto 0); + +begin + +------------------------------------------------------------------------------- +-- Main State Machine +------------------------------------------------------------------------------- + THE_FSM : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= IDLE; + data_write_i <= '0'; + data_finished_i <= '0'; + else + data_write_i <= '0'; + data_finished_i <= '0'; + dummy_counter <= (others => '0'); + + case current_state is + when IDLE => + if START_READOUT_IN = '1' then + if SEND_DUMMY_DATA_IN = '1' then + current_state <= SEND_DUMMY; + elsif SELECT_DATA_FORMAT_IN = '1' then + current_state <= SEND_LONG_DATA; + else + current_state <= SEND_DATA; + end if; + end if; + + when SEND_LONG_DATA => + data_i(31 downto 29) <= "000"; + data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_i(21) <= DATA_BUS_IN(11); + data_i(20 downto 11) <= (others => '0'); + data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0); + data_write_i <= DATA_VALID_IN; + if FINISHED_READOUT_IN = '1' then + current_state <= FINISH; + end if; + + when SEND_DATA => --NOT IMPLEMENTED + data_i(31 downto 29) <= "000"; + data_i(28 downto 22) <= DATA_BUS_IN(18 downto 12); + data_i(21) <= DATA_BUS_IN(11); + data_i(20 downto 11) <= (others => '0'); + data_i(10 downto 0) <= DATA_BUS_IN(10 downto 0); + data_write_i <= DATA_VALID_IN; + if FINISHED_READOUT_IN = '1' then + current_state <= FINISH; + end if; + + when SEND_DUMMY => + if dummy_counter < unsigned(DUMMY_DATA_CONFIG(11 downto 0)) then + data_i(31 downto 30) <= "01"; + data_i(29 downto 12) <= (others => '0'); + data_i(11 downto 0) <= dummy_counter; + data_write_i <= '1'; + dummy_counter <= dummy_counter + to_unsigned(1,1); + else + dummy_counter <= dummy_counter; + end if; + if FINISHED_READOUT_IN = '1' then + current_state <= FINISH; + end if; + + when FINISH => + data_finished_i <= '1'; + current_state <= IDLE; + + when others => + current_state <= IDLE; + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + FEE_DATA_OUT <= data_i; + FEE_DATA_WRITE_OUT <= data_write_i; + FEE_DATA_FINISHED_OUT <= data_finished_i; + + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case current_state is + when IDLE => state_bits <= x"0"; + when SEND_DATA => state_bits <= x"1"; + when SEND_LONG_DATA => state_bits <= x"2"; + when SEND_DUMMY => state_bits <= x"3"; + when FINISH => state_bits <= x"4"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + + + DEBUG_REGISTER(3 downto 0) <= state_bits; + DEBUG_REGISTER(4) <= START_READOUT_IN; + DEBUG_REGISTER(5) <= FINISHED_READOUT_IN; + DEBUG_REGISTER(6) <= data_write_i; + DEBUG_REGISTER(7) <= SEND_DEBUG_INFORMATION_IN; + DEBUG_REGISTER(8) <= SEND_DUMMY_DATA_IN; + DEBUG_REGISTER(9) <= SELECT_DATA_FORMAT_IN; + DEBUG_REGISTER(10) <= DATA_VALID_IN; + DEBUG_REGISTER(31 downto 11) <= (others => '0'); + + +end architecture; diff --git a/design2/initialization_RAM.vhd b/design2/initialization_RAM.vhd new file mode 100644 index 0000000..95f431c --- /dev/null +++ b/design2/initialization_RAM.vhd @@ -0,0 +1,462 @@ +-- VHDL netlist generated by SCUBA ispLever_v70_Prod_Build (55) +-- Module Version: 4.1 +--/storage120/lattice/isplever7.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 11 -rp 1010 -data_width 16 -rdata_width 16 -num_rows 512 -outdataA REGISTERED -outdataB REGISTERED -gsr ENABLED -writemodeA NORMAL -writemodeB NORMAL -resetmode SYNC -memfile ROC1_initialization.mem -memformat orca -e + +-- Mon Oct 27 14:40:36 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity initialization_RAM is + port ( + DataInA: in std_logic_vector(15 downto 0); + DataInB: in std_logic_vector(15 downto 0); + AddressA: in std_logic_vector(8 downto 0); + AddressB: in std_logic_vector(8 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(15 downto 0); + QB: out std_logic_vector(15 downto 0)); +end initialization_RAM; + +architecture Structure of initialization_RAM is + + -- internal signal declarations + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (INITVAL_3F : in String; INITVAL_3E : in String; + INITVAL_3D : in String; INITVAL_3C : in String; + INITVAL_3B : in String; INITVAL_3A : in String; + INITVAL_39 : in String; INITVAL_38 : in String; + INITVAL_37 : in String; INITVAL_36 : in String; + INITVAL_35 : in String; INITVAL_34 : in String; + INITVAL_33 : in String; INITVAL_32 : in String; + INITVAL_31 : in String; INITVAL_30 : in String; + INITVAL_2F : in String; INITVAL_2E : in String; + INITVAL_2D : in String; INITVAL_2C : in String; + INITVAL_2B : in String; INITVAL_2A : in String; + INITVAL_29 : in String; INITVAL_28 : in String; + INITVAL_27 : in String; INITVAL_26 : in String; + INITVAL_25 : in String; INITVAL_24 : in String; + INITVAL_23 : in String; INITVAL_22 : in String; + INITVAL_21 : in String; INITVAL_20 : in String; + INITVAL_1F : in String; INITVAL_1E : in String; + INITVAL_1D : in String; INITVAL_1C : in String; + INITVAL_1B : in String; INITVAL_1A : in String; + INITVAL_19 : in String; INITVAL_18 : in String; + INITVAL_17 : in String; INITVAL_16 : in String; + INITVAL_15 : in String; INITVAL_14 : in String; + INITVAL_13 : in String; INITVAL_12 : in String; + INITVAL_11 : in String; INITVAL_10 : in String; + INITVAL_0F : in String; INITVAL_0E : in String; + INITVAL_0D : in String; INITVAL_0C : in String; + INITVAL_0B : in String; INITVAL_0A : in String; + INITVAL_09 : in String; INITVAL_08 : in String; + INITVAL_07 : in String; INITVAL_06 : in String; + INITVAL_05 : in String; INITVAL_04 : in String; + INITVAL_03 : in String; INITVAL_02 : in String; + INITVAL_01 : in String; INITVAL_00 : in String; + GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute INITVAL_3F : string; + attribute INITVAL_3E : string; + attribute INITVAL_3D : string; + attribute INITVAL_3C : string; + attribute INITVAL_3B : string; + attribute INITVAL_3A : string; + attribute INITVAL_39 : string; + attribute INITVAL_38 : string; + attribute INITVAL_37 : string; + attribute INITVAL_36 : string; + attribute INITVAL_35 : string; + attribute INITVAL_34 : string; + attribute INITVAL_33 : string; + attribute INITVAL_32 : string; + attribute INITVAL_31 : string; + attribute INITVAL_30 : string; + attribute INITVAL_2F : string; + attribute INITVAL_2E : string; + attribute INITVAL_2D : string; + attribute INITVAL_2C : string; + attribute INITVAL_2B : string; + attribute INITVAL_2A : string; + attribute INITVAL_29 : string; + attribute INITVAL_28 : string; + attribute INITVAL_27 : string; + attribute INITVAL_26 : string; + attribute INITVAL_25 : string; + attribute INITVAL_24 : string; + attribute INITVAL_23 : string; + attribute INITVAL_22 : string; + attribute INITVAL_21 : string; + attribute INITVAL_20 : string; + attribute INITVAL_1F : string; + attribute INITVAL_1E : string; + attribute INITVAL_1D : string; + attribute INITVAL_1C : string; + attribute INITVAL_1B : string; + attribute INITVAL_1A : string; + attribute INITVAL_19 : string; + attribute INITVAL_18 : string; + attribute INITVAL_17 : string; + attribute INITVAL_16 : string; + attribute INITVAL_15 : string; + attribute INITVAL_14 : string; + attribute INITVAL_13 : string; + attribute INITVAL_12 : string; + attribute INITVAL_11 : string; + attribute INITVAL_10 : string; + attribute INITVAL_0F : string; + attribute INITVAL_0E : string; + attribute INITVAL_0D : string; + attribute INITVAL_0C : string; + attribute INITVAL_0B : string; + attribute INITVAL_0A : string; + attribute INITVAL_09 : string; + attribute INITVAL_08 : string; + attribute INITVAL_07 : string; + attribute INITVAL_06 : string; + attribute INITVAL_05 : string; + attribute INITVAL_04 : string; + attribute INITVAL_03 : string; + attribute INITVAL_02 : string; + attribute INITVAL_01 : string; + attribute INITVAL_00 : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute GSR : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute MEM_LPC_FILE of initialization_RAM_0_0_0 : label is "initialization_RAM.lpc"; + attribute MEM_INIT_FILE of initialization_RAM_0_0_0 : label is "ROC1_initialization.mem"; + attribute INITVAL_3F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_3A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_39 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_38 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_37 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_36 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_35 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_34 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_33 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_32 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_31 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_30 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_2A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_29 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_28 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_27 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_26 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_25 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_24 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_23 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_22 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_21 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_20 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1F of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1E of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1D of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1C of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1B of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_1A of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_19 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_18 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_17 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_16 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + attribute INITVAL_15 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +------------------------------------------------------------------------------- +-- calibration +------------------------------------------------------------------------------- + attribute INITVAL_14 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114"; + attribute INITVAL_13 of initialization_RAM_0_0_0 : label is "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4"; + attribute INITVAL_12 of initialization_RAM_0_0_0 : label is "0x0009900084000990006400099000440009900024000BD00184000BD00164000BD00144000BD00124"; + attribute INITVAL_11 of initialization_RAM_0_0_0 : label is "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024"; + attribute INITVAL_10 of initialization_RAM_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114"; + attribute INITVAL_0F of initialization_RAM_0_0_0 : label is "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024"; + attribute INITVAL_0E of initialization_RAM_0_0_0 : label is "0X000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024"; +------------------------------------------------------------------------------- +-- +------------------------------------------------------------------------------- + attribute INITVAL_0D of initialization_RAM_0_0_0 : label is "0x000000000000000000000000000000000100011400011000340001100030000110001C0001100018"; + attribute INITVAL_0C of initialization_RAM_0_0_0 : label is "0x00011000140001100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010";--DAQ REGISTER: 35 31 1D 19 15 11 + + attribute INITVAL_0B of initialization_RAM_0_0_0 : label is "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC";--REGISTER_3 + --scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + initialization_RAM_0_0_0: DP16KB + -- synopsys translate_off + generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000", + +------------------------------------------------------------------------------- +-- FEE CALIBRATION (1 LONG) +------------------------------------------------------------------------------- + INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114", + --AFTER MODE CHANGED + INITVAL_13=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4", + -- "0x0009900084000990006400099000440009900024000BD00184000BD00164000BD00144000BD00124", + + INITVAL_11=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1 + +------------------------------------------------------------------------------- +-- FEE CALIBRATION (1 SHORT) +------------------------------------------------------------------------------- + INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114", + --AFTER MODE CHANGED + INITVAL_0F=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1 + INITVAL_0E=> "0x000BD00104000BD000E4000BD000C4000BD000A4000BD00084000BD00064000BD00044000BD00024",--REGISTER_1 + +------------------------------------------------------------------------------- +-- FEE INIT: 1 LONG MB +------------------------------------------------------------------------------- + + INITVAL_0D=> "0x000000000000000000000000000000000100011400011000340001100030000110001C0001100018", -- GLOBAL DISABLE in CPLD + INITVAL_0C=> "0x00011000140001100010000FF00034000FF00030000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 35 31 1D 19 15 11 + + INITVAL_0B=> "0x000FF0018C000FF0016C000FF0014C000FF0012C000FF0010C000FF000EC000FF000CC000FF000AC", + -- "0x000FF0008C000FF0006C000FF0004C000FF0002C000FF00188000FF00168000FF00148000FF00128", + + INITVAL_09=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2 + INITVAL_08=> "0x0009900184000990016400099001440009900124000990010400099000E400099000C400099000A4", + -- "0x00099000840009900064000990004400099000240001700180000170016000017001400001700120", + INITVAL_06=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0 + +------------------------------------------------------------------------------ +-- FEE INIT: 1 SHORT MB (CHANGE REGISTER_2 TO CHOOSE WHICH CHANNEL CALIBRATE) +------------------------------------------------------------------------------- + INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000001000114", + INITVAL_04=> "0x000000001C000000001800000000140000000010000FF0001C000FF00018000FF00014000FF00010",--DAQ REGISTER: 1D 19 15 11 + INITVAL_03=> "0x000FF0010C000FF000EC000FF000CC000FF000AC000FF0008C000FF0006C000FF0004C000FF0002C",--REGISTER_3 + INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2 + --INITVAL_02=> "0x000FF00108000FF000E8000FF000C8000FF000A8000FF00088000FF00068000FF00048000FF00028",--REGISTER_2 + --2 CAL TDC1 ONLY + INITVAL_01=> "0x000990010400099000E400099000C400099000A40009900084000990006400099000440009900024",--REGISTER_1 + INITVAL_00=> "0x000170010000017000E000017000C000017000A00001700080000170006000017000400001700020",--REGISTER_0(101_lastTDC_shortMb) + + CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "SYNC", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>DataInA(0), DIA1=>DataInA(1), DIA2=>DataInA(2), + DIA3=>DataInA(3), DIA4=>DataInA(4), DIA5=>DataInA(5), + DIA6=>DataInA(6), DIA7=>DataInA(7), DIA8=>DataInA(8), + DIA9=>DataInA(9), DIA10=>DataInA(10), DIA11=>DataInA(11), + DIA12=>DataInA(12), DIA13=>DataInA(13), DIA14=>DataInA(14), + DIA15=>DataInA(15), DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, + ADA3=>scuba_vlo, ADA4=>AddressA(0), ADA5=>AddressA(1), + ADA6=>AddressA(2), ADA7=>AddressA(3), ADA8=>AddressA(4), + ADA9=>AddressA(5), ADA10=>AddressA(6), ADA11=>AddressA(7), + ADA12=>AddressA(8), ADA13=>scuba_vlo, CEA=>ClockEnA, + CLKA=>ClockA, WEA=>WrA, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>ResetA, DIB0=>DataInB(0), + DIB1=>DataInB(1), DIB2=>DataInB(2), DIB3=>DataInB(3), + DIB4=>DataInB(4), DIB5=>DataInB(5), DIB6=>DataInB(6), + DIB7=>DataInB(7), DIB8=>DataInB(8), DIB9=>DataInB(9), + DIB10=>DataInB(10), DIB11=>DataInB(11), DIB12=>DataInB(12), + DIB13=>DataInB(13), DIB14=>DataInB(14), DIB15=>DataInB(15), + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vhi, + ADB1=>scuba_vhi, ADB2=>scuba_vlo, ADB3=>scuba_vlo, + ADB4=>AddressB(0), ADB5=>AddressB(1), ADB6=>AddressB(2), + ADB7=>AddressB(3), ADB8=>AddressB(4), ADB9=>AddressB(5), + ADB10=>AddressB(6), ADB11=>AddressB(7), ADB12=>AddressB(8), + ADB13=>scuba_vlo, CEB=>ClockEnB, CLKB=>ClockB, WEB=>WrB, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>ResetB, DOA0=>QA(0), DOA1=>QA(1), DOA2=>QA(2), + DOA3=>QA(3), DOA4=>QA(4), DOA5=>QA(5), DOA6=>QA(6), + DOA7=>QA(7), DOA8=>QA(8), DOA9=>QA(9), DOA10=>QA(10), + DOA11=>QA(11), DOA12=>QA(12), DOA13=>QA(13), DOA14=>QA(14), + DOA15=>QA(15), DOA16=>open, DOA17=>open, DOB0=>QB(0), + DOB1=>QB(1), DOB2=>QB(2), DOB3=>QB(3), DOB4=>QB(4), + DOB5=>QB(5), DOB6=>QB(6), DOB7=>QB(7), DOB8=>QB(8), + DOB9=>QB(9), DOB10=>QB(10), DOB11=>QB(11), DOB12=>QB(12), + DOB13=>QB(13), DOB14=>QB(14), DOB15=>QB(15), DOB16=>open, + DOB17=>open); + +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of initialization_RAM is + for Structure + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/design2/load_mode_line.vhd b/design2/load_mode_line.vhd new file mode 100644 index 0000000..18b365d --- /dev/null +++ b/design2/load_mode_line.vhd @@ -0,0 +1,459 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + + +entity load_mode_line is + generic ( + timecounter_width : integer := 13 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + + --Control + DO_BEGRUN_IN : in std_logic; + DO_CALIB_TRIGGER_IN : in std_logic; + CALIBRATION_STEP_MODE_LINE : in std_logic_vector(3 downto 0); + TDC_SETTING_LOADED_IN : in std_logic; + + --MBO + GDE : out std_logic; + MODD : out std_logic; + RES : out std_logic; + TOK : out std_logic; + WRM : out std_logic; + RDM : out std_logic; + RDO : in std_logic; + + --Status + START_LOAD_TDC_SETTINGS_OUT : out std_logic; + START_DEBUG_READOUT_OUT : out std_logic; + TDC_SETTINGS_WRITTEN : out std_logic; + CAL1_WRITTEN : out std_logic; + + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + +end load_mode_line; + +architecture Behavioral of load_mode_line is + +-- subtype mode_definition is std_logic_vector(4 downto 0); + +-- constant reset_mode : mode_definition := "00000"; -- hex 00 +-- constant jtag : mode_definition := "11000"; -- hex 70 +-- constant init : mode_definition := "01000"; -- hex 50 +-- constant init_tok : mode_definition := "01001"; -- hex 51: init mode + send token +-- constant unknown : mode_definition := "00100"; -- hex 48 not declared by Jan???!!! +-- constant setr : mode_definition := "10110"; -- hex 6c +-- constant setr_tok : mode_definition := "10111"; -- hex 6d +-- constant all_null : mode_definition := "00000"; -- hex 00 + +--ok for 25MHz +--constant time_limit : std_logic_vector(width - 1 downto 0) := "0011111010000"; + constant time_limit : unsigned(timecounter_width - 1 downto 0) := (others => '1'); + + type state_type is (idle_state, reset_mode_state, + jtag_state, init_state, + init_tok_state, wait_token_1_state, + wait_token_2_state, + unknown_state, setr_state, + setr_tok_state, + set_mode_after_loaded_ROC1, + dummy_state, + debug_readout, + jtag_2_state, unknown_2_state, + wait_state, + --CALIBRATION STATE + start_calibration_sequence, write_mb_control_register_1, + write_mb_control_register_3, write_mb_control_register_0, + write_mb_control_register_2, acquisition_mode_state, + wait_calibration_mode_0, wait_calibration_mode_1, + wait_calibration_mode_3, + stop_calibration_on_acquisition_mode, + prepare_readout_state, + set_mode_after_loaded_CAL1, + dummy_calibration_state); + + signal current_state : state_type; + signal next_state : state_type; + + signal time_counter : unsigned(timecounter_width - 1 downto 0); + signal clear_time_counter : std_logic; + signal reg_MODD : std_logic; + signal reg_RES : std_logic; + signal reg_TOK : std_logic; + signal reg_WRM : std_logic; + signal reg_RDM : std_logic; + signal reg_GDE : std_logic; + + signal reg_start_load_tdc_settings : std_logic; + signal next_start_load_tdc_settings : std_logic; + signal reg_TDC_SETTINGS_WRITTEN : std_logic; + signal next_TDC_SETTINGS_WRITTEN : std_logic; + signal reg_cal1_written : std_logic; + signal next_cal1_written : std_logic; + + signal next_do_debug_readout : std_logic; + signal reg_do_debug_readout : std_logic; + + signal reg_state_bits : std_logic_vector(7 downto 0); + signal next_state_bits : std_logic_vector(7 downto 0); + + signal next_MOD_RES_TOK_WRM_RDM_GDE : std_logic_vector(5 downto 0); + +begin + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + GDE <= reg_GDE; + MODD <= reg_MODD; + RES <= reg_RES; + TOK <= reg_TOK; + WRM <= reg_WRM; + RDM <= reg_RDM; + START_LOAD_TDC_SETTINGS_OUT <= reg_start_load_tdc_settings; + START_DEBUG_READOUT_OUT <= reg_do_debug_readout; + TDC_SETTINGS_WRITTEN <= reg_TDC_SETTINGS_WRITTEN; + CAL1_WRITTEN <= reg_cal1_written; + +------------------------------------------------------------------------------- +-- FSM +------------------------------------------------------------------------------- + + proc_FSM_SYNC : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= idle_state; + reg_GDE <= '0'; + reg_MODD <= '0'; + reg_RES <= '0'; + reg_TOK <= '0'; + reg_WRM <= '0'; + reg_RDM <= '0'; + reg_start_load_tdc_settings <= '0'; + reg_state_bits <= (others => '0'); + reg_cal1_written <= '0'; + reg_do_debug_readout <= '0'; + reg_TDC_SETTINGS_WRITTEN <= '0'; + else + current_state <= next_state; + reg_GDE <= next_MOD_RES_TOK_WRM_RDM_GDE(0); + reg_MODD <= next_MOD_RES_TOK_WRM_RDM_GDE(5); + reg_RES <= next_MOD_RES_TOK_WRM_RDM_GDE(4); + reg_TOK <= next_MOD_RES_TOK_WRM_RDM_GDE(3); + reg_WRM <= next_MOD_RES_TOK_WRM_RDM_GDE(2); + reg_RDM <= next_MOD_RES_TOK_WRM_RDM_GDE(1); + reg_start_load_tdc_settings <= next_start_load_tdc_settings; + reg_TDC_SETTINGS_WRITTEN <= next_TDC_SETTINGS_WRITTEN; + reg_state_bits <= next_state_bits; + reg_cal1_written <= next_cal1_written; + reg_do_debug_readout <= next_do_debug_readout; + end if; + end if; + end process; + + + proc_FSM_COMB : process (DO_BEGRUN_IN, RDO, current_state, + TDC_SETTING_LOADED_IN, time_counter, + DO_CALIB_TRIGGER_IN, CALIBRATION_STEP_MODE_LINE) + begin + next_state_bits <= (others => '0'); + next_TDC_SETTINGS_WRITTEN <= '0'; + next_cal1_written <= '0'; + next_MOD_RES_TOK_WRM_RDM_GDE <= "000000"; + next_start_load_tdc_settings <= '0'; + clear_time_counter <= '0'; + next_state <= current_state; + next_do_debug_readout <= '0'; + + case current_state is + + when idle_state => + next_state_bits <= x"00"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "000000"; -- hex 00 + clear_time_counter <= '1'; + if DO_BEGRUN_IN = '1' then + next_state <= reset_mode_state; + end if; + + when reset_mode_state => + next_state_bits <= x"01"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "000000"; -- hex 00 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= jtag_state; + end if; + + when jtag_state => + next_state_bits <= x"02"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "100101"; -- hex 70 + + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= init_state; + end if; + + when init_state => + next_state_bits <= x"03"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "100001"; -- hex 50 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= init_tok_state; + end if; + + when init_tok_state => + next_state_bits <= x"04"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "100011"; -- hex 51 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= wait_token_1_state; + end if; + + when wait_token_1_state => + next_state_bits <= x"05"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "100011"; -- hex 51 + clear_time_counter <= '1'; + if RDO = '1' then + next_state <= unknown_state; + end if; + + when unknown_state => + next_state_bits <= x"0B"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= setr_state; + end if; + + when setr_state => + next_state_bits <= x"0C"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "011101"; -- hex 6C + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= setr_tok_state; + end if; + + when setr_tok_state => + next_state_bits <= x"0D"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "011111"; -- hex 6D + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= wait_token_2_state; + --here the MBO sends back data that is just ignored by the OEP + end if; + + when wait_token_2_state => + next_state_bits <= x"06"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "011111"; -- hex 6D + clear_time_counter <= '1'; + if RDO = '1' then + next_state <= jtag_2_state; + end if; + + when jtag_2_state => + next_state_bits <= x"07"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "100101"; -- hex 70 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= unknown_2_state; + end if; + + when unknown_2_state => --start loading TDC settings + next_state_bits <= x"08"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_start_load_tdc_settings <= '1'; + next_state <= dummy_state; + end if; + + when dummy_state => + next_state_bits <= x"09"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + clear_time_counter <= '1'; + next_state <= wait_state; + + when wait_state => --wait until finished loading TDC settings + next_state_bits <= x"0A"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + clear_time_counter <= '1'; + if TDC_SETTING_LOADED_IN = '1' then + next_state <= debug_readout; + next_do_debug_readout <= '1'; + end if; + + when debug_readout => --here the MBO sends back data + next_state_bits <= x"DD"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "011111"; -- hex 6D + clear_time_counter <= '1'; + if RDO = '1' then + next_state <= set_mode_after_loaded_ROC1; + end if; + + +------------------------------------------------------------------------------- +--this state should be executed only after the ROC1 +--file is loaded. this state loads the mode line: 1A01 64 +--If I get the CALIBRATION TRIGGER I start the procedure for PROCESS +--the CALIBRATION. +------------------------------------------------------------------------------- + when set_mode_after_loaded_ROC1 => + clear_time_counter <= '1'; + next_state_bits <= x"0E"; + next_TDC_SETTINGS_WRITTEN <= '1'; + -- hex 64 + next_MOD_RES_TOK_WRM_RDM_GDE <= "010100"; --GDE=0? -- hex 64 + if DO_CALIB_TRIGGER_IN = '1' then + next_state <= start_calibration_sequence; + end if; + + when start_calibration_sequence => + next_state_bits <= x"0F"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= wait_calibration_mode_0; + end if; + + when wait_calibration_mode_0 => + next_state_bits <= x"10"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + clear_time_counter <= '1'; + if CALIBRATION_STEP_MODE_LINE = x"1" then + next_state <= write_mb_control_register_0; --TSTW + end if; + + when write_mb_control_register_0 => + next_state_bits <= x"11"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001000"; -- hex 08 + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= wait_calibration_mode_1; + end if; + + when wait_calibration_mode_1 => + next_state_bits <= x"12"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001000"; -- hex 08 + clear_time_counter <= '1'; + if CALIBRATION_STEP_MODE_LINE = x"2" then + next_state <= write_mb_control_register_1; --TSTW + end if; + + when write_mb_control_register_1 => + next_state_bits <= x"13"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001000"; -- hex 08 + if time_counter = time_limit then + next_state <= write_mb_control_register_2; + clear_time_counter <= '1'; + end if; + + when write_mb_control_register_2 => + next_state_bits <= x"14"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001000"; -- hex 08 + if time_counter = time_limit then + next_state <= write_mb_control_register_3; + clear_time_counter <= '1'; + end if; + + when write_mb_control_register_3 => + next_state_bits <= x"15"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + if time_counter = time_limit then + next_state <= wait_calibration_mode_3; + clear_time_counter <= '1'; + end if; + + when wait_calibration_mode_3 => + next_state_bits <= x"16"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "001001"; -- hex 48 + clear_time_counter <= '1'; + if CALIBRATION_STEP_MODE_LINE = x"3" then + next_state <= acquisition_mode_state; + end if; + + when acquisition_mode_state => + next_state_bits <= x"17"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "111101"; -- hex 7C + if time_counter = time_limit then + next_state <= prepare_readout_state; + clear_time_counter <= '1'; + end if; + + when prepare_readout_state => + next_state_bits <= x"19"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; -- hex 64+GDE + if time_counter = time_limit then + next_state <= dummy_calibration_state; + clear_time_counter <= '1'; + end if; + + when dummy_calibration_state => + next_state_bits <= x"21"; + next_cal1_written <= '1'; --cal done + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; -- hex 64+GDE + next_state <= stop_calibration_on_acquisition_mode; + clear_time_counter <= '1'; + + when stop_calibration_on_acquisition_mode => + next_state_bits <= x"18"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; -- hex 64+GDE + clear_time_counter <= '1'; + if RDO = '1' then + next_state <= set_mode_after_loaded_CAL1; + elsif DO_CALIB_TRIGGER_IN = '1' then + next_state <= start_calibration_sequence; + end if; + + when set_mode_after_loaded_CAL1 => + next_state_bits <= x"20"; + next_MOD_RES_TOK_WRM_RDM_GDE <= "010100"; -- hex 64 + clear_time_counter <= '1'; + if DO_CALIB_TRIGGER_IN = '1' then + next_state <= start_calibration_sequence; + end if; + + + when others => + next_state <= idle_state; + + end case; + end process; + + proc_timer : process (CLK) + begin + if rising_edge(CLK) then + if (RESET = '1' or clear_time_counter = '1') then + time_counter <= (others => '0'); + else + time_counter <= time_counter + to_unsigned(1,1); + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + DEBUG_REGISTER(7 downto 0) <= reg_state_bits; + DEBUG_REGISTER(8) <= reg_TDC_SETTINGS_WRITTEN; + DEBUG_REGISTER(9) <= reg_cal1_written; + DEBUG_REGISTER(15 downto 10) <= (others => '0'); + DEBUG_REGISTER(16) <= reg_GDE; + DEBUG_REGISTER(17) <= reg_MODD; + DEBUG_REGISTER(18) <= reg_RES; + DEBUG_REGISTER(19) <= reg_TOK; + DEBUG_REGISTER(20) <= reg_WRM; + DEBUG_REGISTER(21) <= reg_RDM; + DEBUG_REGISTER(31 downto 22) <= (others => '0'); + +end Behavioral; + diff --git a/design2/load_tdc_setup.vhd b/design2/load_tdc_setup.vhd new file mode 100644 index 0000000..8e74aff --- /dev/null +++ b/design2/load_tdc_setup.vhd @@ -0,0 +1,589 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + + +entity load_tdc_setup is + generic ( + timecounter_width : integer := 6 + -- number of bit of the counter if 4 and clk 100MHz + -- the state remain active 320 ns + -- width nr 3 => dst width 160 ns + -- width nr 4 => dst width 317 ns + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --MBO + A_ADD : out std_logic_vector(8 downto 0); + A_DST : out std_logic; + A_AOD : out std_logic; + --Control In + TRIGGER_BEGRUN_IN : in std_logic; + TRIGGER_CALIB_IN : in std_logic; + CALIBRATION_STEP_TDC_SETUP : in std_logic_vector(3 downto 0); + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + TDC_SETTING_LOADED_OUT : out std_logic; + -- signals for ram + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit + RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + -- Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behaviour of load_tdc_setup is + +--constant declaration + constant time_limit : unsigned(timecounter_width - 1 downto 0) := (others => '1'); + + constant cpld_register_data : std_logic_vector(8 downto 0) := '1' & x"14"; + +--ok 25MHz +--constant time_limit : std_logic_vector(width - 1 downto 0) := "010000"; + + type state_type is (idle_state, + set_address_state, write_address_state, write_address_strobe, + write_address_strobe_next, write_address_no_strobe, + + set_data_state, write_data_state, write_data_strobe, + write_data_strobe_next, write_data_no_strobe, + write_data_no_strobe_next, stop_state, + dummy_wait, maximum_counter_value, + -- calibration states + calibration_state_0, calibration_state_1, + calibration_state_2, calibration_state_3, + calibration_state_4, calibration_state_5, + calibration_state_6, dummy_calibration_state, dummy_calibration_state_2, + calibration_address_no_strobe_0, calibration_address_with_strobe_0, + calibration_address_no_strobe_1, calibration_dummy_wait, + calibration_data_no_strobe_0, calibration_data_with_strobe_0, + calibration_data_no_strobe_1, calibration_data_no_strobe_2, + calibration_maximum_counter_value, wait_mode_load, + wait_calibration_state_6, + dummy_calibration_state_3, test_wait, + test_wait_1); + + signal current_state : state_type; + signal next_state : state_type; + + signal send_data : std_logic_vector(15 downto 0); + signal up_counter_i : std_logic; + signal next_calfile_second_part : std_logic; + signal calfile_second_part : std_logic; + signal time_counter : unsigned(timecounter_width - 1 downto 0); + signal reg_A_DST : std_logic; + signal next_A_DST : std_logic; + signal reg_A_AOD : std_logic; + signal next_A_AOD : std_logic; + signal reg_TDC_SETTING_LOADED_OUT : std_logic; + signal next_TDC_SETTING_LOADED_OUT : std_logic; + signal motherboard_type_in_i : std_logic_vector(3 downto 0); + signal stop_counter_ram : std_logic_vector(9 downto 0); + signal counter_ram : std_logic_vector(9 downto 0); + signal offset_ram : unsigned(9 downto 0); + signal temp_counter_ram : unsigned(9 downto 0); + signal calibration_stop_counter_ram_0 : std_logic_vector(9 downto 0); + signal calibration_offset_ram : unsigned(9 downto 0); + signal calibration_stop_counter_ram_1 : std_logic_vector(9 downto 0); + signal calibration_stop_counter_ram : std_logic_vector(9 downto 0); + signal next_debug_register : std_logic_vector(7 downto 0); + signal reg_debug_register : std_logic_vector(7 downto 0); + signal processing_calibration : std_logic; + signal next_processing_calibration : std_logic; + signal clear_time_counter : std_logic; + +begin + +------------------------------------------------------------------------------- +-- RAM with config settings +------------------------------------------------------------------------------- + THE_CONFIG_RAM: initialization_RAM + port map ( + DataInA => (others => '0'), + DataInB => RAM_DATA_IN, + AddressA => counter_ram(8 downto 0), + AddressB => RAM_ADDRESS_IN, + ClockA => CLK, + ClockB => CLK, + ClockEnA => '1', + ClockEnB => '1', + WrA => '0', + WrB => RAM_WRITE_ENABLE_IN, + ResetA => '0', + ResetB => '0', + QA => send_data, + QB => RAM_DATA_OUT + ); + +------------------------------------------------------------------------------- +--purpose: state machine synchronization +------------------------------------------------------------------------------- + PROC_FSM_SYNC : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= idle_state; + reg_A_DST <= '0'; + reg_A_AOD <= '0'; + reg_TDC_SETTING_LOADED_OUT <= '0'; + reg_debug_register(7 downto 0) <= (others => '0'); + processing_calibration <= '0'; + calfile_second_part <= '0'; + else + current_state <= next_state; + reg_A_DST <= next_A_DST; + reg_A_AOD <= next_A_AOD; + reg_TDC_SETTING_LOADED_OUT <= next_TDC_SETTING_LOADED_OUT; + reg_debug_register(7 downto 0) <= next_debug_register; + processing_calibration <= next_processing_calibration; + calfile_second_part <= next_calfile_second_part; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +--here the state machine starts it extract data and address +--from ram and put them in the bus +------------------------------------------------------------------------------- + PROC_FSM : process (current_state, counter_ram,TRIGGER_BEGRUN_IN, stop_counter_ram, + calibration_stop_counter_ram, time_counter, CALIBRATION_STEP_TDC_SETUP, + TRIGGER_CALIB_IN, calfile_second_part, send_data, processing_calibration + ) + begin + next_state <= current_state; + next_A_DST <= '0'; + next_A_AOD <= '0'; + next_debug_register <= (others => '0'); + up_counter_i <= '0'; + next_calfile_second_part <= calfile_second_part; + next_TDC_SETTING_LOADED_OUT <= '0'; + A_ADD <= (others => '0'); + clear_time_counter <= '0'; + next_processing_calibration <= processing_calibration; + + case current_state is + + when idle_state => + next_debug_register <= x"01"; + next_A_AOD <= '0'; + clear_time_counter <= '1'; + if TRIGGER_BEGRUN_IN = '1' then + next_state <= set_address_state; + next_processing_calibration <= '0'; + end if; +------------------------------------------------------------------------------- +-- ROC DATA: WRITE ADDRESS PART only for first trigger +------------------------------------------------------------------------------- +--here I put data on the bus and NO strobe + when set_address_state => + next_debug_register <= x"02"; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= write_address_strobe; + end if; + + when write_address_strobe => + next_debug_register <= x"03"; + next_A_DST <= '1'; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= write_address_no_strobe; + end if; + + when write_address_no_strobe => + next_debug_register <= x"04"; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= dummy_wait; + end if; + +--here I increment the counter to extract data + when dummy_wait => + next_debug_register <= x"05"; + next_A_AOD <= '0'; + up_counter_i <= '1'; + clear_time_counter <= '1'; + A_ADD <= send_data(8 downto 0); + next_state <= set_data_state; +--------------------------------------------------------------------------- +--WRITE DATA PART +--------------------------------------------------------------------------- +--I put data on the bus and no strobe + when set_data_state => + next_debug_register <= x"06"; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0';--x"17"; --send_data;. . + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= write_data_strobe; + end if; + + when write_data_strobe => + next_debug_register <= x"07"; + next_A_DST <= '1';--'1'; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0'; + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= write_data_no_strobe; + end if; + + when write_data_no_strobe => + next_debug_register <= x"08"; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0'; + if time_counter = time_limit then + clear_time_counter <= '1'; + next_state <= write_data_no_strobe_next; + end if; + + when write_data_no_strobe_next => + next_debug_register <= x"09"; + next_A_AOD <= '0'; + up_counter_i <= '1'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + next_state <= maximum_counter_value; + + when maximum_counter_value => + next_debug_register <= x"0A"; + next_A_AOD <= '0'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + if counter_ram >= stop_counter_ram then +-- if counter_ram >= x"51" then + next_TDC_SETTING_LOADED_OUT <= '1'; + next_state <= stop_state; + else + next_state <= set_address_state; --goes again to load next address + end if; + +-- Stay here after ROC1 has been loaded + when stop_state => + next_debug_register <= x"0B"; + next_A_AOD <= '0'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + next_calfile_second_part <= '0'; + if TRIGGER_CALIB_IN = '1' then + next_processing_calibration <= '1'; + next_state <= calibration_state_0; + end if; + +------------------------------------------------------------------------------- +-- CALIBRATION PROCESS +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- CPLD register GDE at the beginning and at the end of CAL file. +------------------------------------------------------------------------------- + when calibration_state_0 => --write CPLD REGISTER: address, NO strobe + next_processing_calibration <= '1'; + next_debug_register <= x"0C"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + A_ADD <= cpld_register_data; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_state_1; + end if; + + when calibration_state_1 => --write CPLD REGISTER: address, with strobe + next_debug_register <= x"0D"; + next_A_DST <= '1'; + next_A_AOD <= '0'; + A_ADD <= cpld_register_data;--'1' & x"15"; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_state_2; + end if; + + when calibration_state_2 => --write CPLD REGISTER : address, NO strobe + next_debug_register <= x"0E"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + A_ADD <= cpld_register_data;--'1' & x"15"; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_state_3; + end if; + + when calibration_state_3 => --write CPLD REGISTER : data, NO strobe + next_debug_register <= x"0F"; + next_A_DST <= '0'; + next_A_AOD <= '1'; + A_ADD <= x"00" & '0'; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_state_4; + end if; + + when calibration_state_4 => --write CPLD REGISTER : data, strobe + next_debug_register <= x"10"; + next_A_DST <= '1'; + next_A_AOD <= '1'; + A_ADD <= x"00" & '0'; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_state_5; + end if; + + when calibration_state_5 => --write CPLD REGISTER : data, NO strobe + next_debug_register <= x"11"; + next_A_DST <= '0'; + next_A_AOD <= '1'; + A_ADD <= x"00" & '0'; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= test_wait; + end if; + + when test_wait => + next_debug_register <= x"21"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + A_ADD <= x"00" & '0'; + clear_time_counter <= '1'; + next_state <= test_wait_1; + + when test_wait_1 => + next_debug_register <= x"20"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + A_ADD <= x"00" & '0'; + clear_time_counter <= '1'; + next_state <= wait_calibration_state_6; +------------------------------------------------------------------------------ +-- +------------------------------------------------------------------------------ + when wait_calibration_state_6 => --wait till TSTW+GDE (1a01 08) mode line are fixed + next_debug_register <= x"12"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + clear_time_counter <= '1'; + if CALIBRATION_STEP_TDC_SETUP = x"1" then + next_state <= dummy_calibration_state; + end if; + + when dummy_calibration_state => --start loading data + next_debug_register <= x"13"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + up_counter_i <= '1'; + A_ADD <= send_data(8 downto 0); + clear_time_counter <= '1'; + next_state <= dummy_calibration_state_2; + + when dummy_calibration_state_2 => --start loading data + next_debug_register <= x"13"; + next_A_DST <= '0'; + next_A_AOD <= '0'; + up_counter_i <= '1'; + A_ADD <= send_data(8 downto 0); + clear_time_counter <= '1'; + next_state <= calibration_address_no_strobe_0; + +------------------------------------------------------------------------------- +-- CALIBRATION LOAD REGISTER 1 +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- WRITE ADDRESS PART +------------------------------------------------------------------------------- +--here I put data on the bus and NO strobe + when calibration_address_no_strobe_0 => + next_debug_register <= x"14"; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_address_with_strobe_0; + end if; + + when calibration_address_with_strobe_0 => + next_debug_register <= x"15"; + next_A_DST <= '1'; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_address_no_strobe_1; + end if; + + when calibration_address_no_strobe_1 => + next_debug_register <= x"16"; + next_A_AOD <= '0'; + A_ADD <= send_data(8 downto 0); + if time_counter >= time_limit then + up_counter_i <= '1'; + clear_time_counter <= '1'; + next_state <= calibration_data_no_strobe_0; + end if; + +--here I increment the counter to extract data +-- when calibration_dummy_wait => +-- next_debug_register <= x"17"; +-- next_A_AOD <= '0'; +-- A_ADD <= send_data(8 downto 0); +-- clear_time_counter <= '1'; +-- next_state <= calibration_data_no_strobe_0; +--------------------------------------------------------------------------- +--CALIBRATION: WRITE DATA PART +--------------------------------------------------------------------------- +--I put data on the bus and no strobe + when calibration_data_no_strobe_0 => + next_debug_register <= x"18"; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0';--x"17"; --send_data;. . + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_data_with_strobe_0; + end if; + + when calibration_data_with_strobe_0 => + next_debug_register <= x"19"; + next_A_DST <= '1';--'1'; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0'; + if time_counter >= time_limit then + clear_time_counter <= '1'; + next_state <= calibration_data_no_strobe_1; + end if; + + when calibration_data_no_strobe_1 => + next_debug_register <= x"1A"; + next_A_AOD <= '1'; + A_ADD <= send_data(7 downto 0) & '0'; + if time_counter >= time_limit then + up_counter_i <= '1'; + clear_time_counter <= '1'; + next_state <= calibration_maximum_counter_value; + end if; + +-- when calibration_data_no_strobe_2 => +-- next_debug_register <= x"1B"; +-- next_A_AOD <= '0'; +-- A_ADD <= send_data(7 downto 0) & '0'; +-- clear_time_counter <= '1'; +-- next_state <= calibration_maximum_counter_value; + + when calibration_maximum_counter_value => + next_debug_register <= x"1C"; + next_A_AOD <= '0'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + if counter_ram >= calibration_stop_counter_ram then + next_state <= wait_mode_load; + else + next_state <= calibration_address_no_strobe_0; --goes again to load next address + end if; + + when wait_mode_load => --08 08 48 + next_debug_register <= x"1D"; + next_A_AOD <= '0'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + if (CALIBRATION_STEP_TDC_SETUP = x"3" and calfile_second_part = '0') then + next_state <= dummy_calibration_state_3; + elsif (CALIBRATION_STEP_TDC_SETUP = x"3" and calfile_second_part = '1') then + next_state <= stop_state; --calibration finished + end if; + + when dummy_calibration_state_3 => + next_debug_register <= x"1F"; + next_A_AOD <= '0'; + A_ADD <= send_data(7 downto 0) & '0'; + clear_time_counter <= '1'; + next_calfile_second_part <= '1'; --use second part of CAL1 + next_state <= calibration_address_no_strobe_0; + + when others => + next_state <= idle_state; + + end case; + end process; + +------------------------------------------------------------------------------- +--this counter mantain the tdc setup data lines fixed at a certain value +--(see debouncer in CPLD on motherboard) +------------------------------------------------------------------------------- +proc_time_counter : process (CLK) + begin + if rising_edge(CLK) then + if (RESET = '1' or clear_time_counter = '1') then + time_counter <= (others => '0'); + else + time_counter <= time_counter + to_unsigned(1,1); + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +--Load min / max values for RAM addresses +------------------------------------------------------------------------------- +calibration_stop_counter_ram_0 <= "01" & x"27" when motherboard_type_in_i = x"2" else "00" & x"EF"; +calibration_offset_ram <= "01" & x"0E" when motherboard_type_in_i = x"2" else "00" & x"DE"; +calibration_stop_counter_ram_1 <= "01" & x"41" when motherboard_type_in_i = x"2" else "01" & x"01"; +stop_counter_ram <= "00" & x"D9" when motherboard_type_in_i = x"2" else "00" & x"51"; +offset_ram <= "00" & x"60" when motherboard_type_in_i = x"2" else "00" & x"00"; + + +------------------------------------------------------------------------------- +-- the counter extracts data from the ram. +-- the data is sended as follows: +-- address_1 => data_1, address_2 => data_2, . . +------------------------------------------------------------------------------- +proc_ram_addr : process (CLK) + begin + if rising_edge(CLK) then + if (RESET = '1' or current_state = stop_state) then + temp_counter_ram <= (others => '0'); + elsif up_counter_i = '1' then + temp_counter_ram <= temp_counter_ram + to_unsigned(1,1); + end if; + end if; + end process; + +counter_ram <= std_logic_vector(temp_counter_ram + offset_ram) when processing_calibration = '0' else + std_logic_vector(temp_counter_ram + calibration_offset_ram); + +calibration_stop_counter_ram <= (calibration_stop_counter_ram_0) when calfile_second_part = '0' + else (calibration_stop_counter_ram_1); + + + + + +------------------------------------------------------------------------------- +-- Connecting input / output +------------------------------------------------------------------------------- + A_DST <= reg_A_DST; + A_AOD <= reg_A_AOD; + TDC_SETTING_LOADED_OUT <= reg_TDC_SETTING_LOADED_OUT; + motherboard_type_in_i <= MOTHERBOARD_TYPE_IN; + DEBUG_REGISTER(7 downto 0) <= reg_debug_register(7 downto 0); + DEBUG_REGISTER(17 downto 8) <= counter_ram; + DEBUG_REGISTER(18) <= reg_TDC_SETTING_LOADED_OUT; + DEBUG_REGISTER(19) <= calfile_second_part; + DEBUG_REGISTER(20) <= processing_calibration; + DEBUG_REGISTER(31 downto 21) <= (others => '0'); + + +end architecture; diff --git a/design2/mdc_control.vhd b/design2/mdc_control.vhd new file mode 100644 index 0000000..2512159 --- /dev/null +++ b/design2/mdc_control.vhd @@ -0,0 +1,461 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; +use work.lattice_ecp2m_fifo.all; + + + +entity mdc_control is + port( + CLK : in std_logic; + RESET : in std_logic; + + A_ADD : inout std_logic_vector(8 downto 0); + A_AOD : inout std_logic; + A_DST : inout std_logic; + A_RDM : out std_logic; + A_GDE : out std_logic; + A_RDO : in std_logic; + A_MOD : out std_logic; + A_RES : out std_logic; + A_TOK : out std_logic; + A_WRM : out std_logic; + A_RESERVE : in std_logic; + + TRIGGER_IN : in std_logic; -- external CMS in + TRIGGER_OUT : out std_logic; -- CMS to MBO + TRIGGER_MONITOR_OUT : out std_logic; -- to endpoint + + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_RELEASE_OUT : out std_logic; + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); --config RAM + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + RAM_READY_OUT : out std_logic; + + STAT_ADDRESS_IN : in std_logic_vector(3 downto 0); --status register + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_READ_ENABLE_IN : in std_logic; + STAT_READY_OUT : out std_logic; + + RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo + RB_READ_ENABLE_IN : in std_logic; + RB_READY_OUT : out std_logic; + RB_EMPTY_OUT : out std_logic; + + COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0); + COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); + CTRL_REG_IN : in std_logic_vector(63 downto 0); + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture arch of mdc_control is + + + + signal add_out_i : std_logic_vector(8 downto 0); + signal aod_out_i : std_logic; + signal dst_out_i : std_logic; + signal add_in_i : std_logic_vector(8 downto 0); + signal aod_in_i : std_logic; + signal dst_in_i : std_logic; + + signal trigger_i : std_logic; + signal trigger_timing : std_logic; + signal trigger_pseudo_timing : std_logic; + signal trigger_pseudo_tmg_long : std_logic; + signal trg_pulse_counter : unsigned(4 downto 0); + signal reg_timing_trigger : std_logic; + signal trigger_begin_run : std_logic; + signal trigger_reg_pulse_i : std_logic; + + signal reset_readout_logic_i : std_logic; + signal motherboard_type_i : std_logic_vector( 3 downto 0); + signal data_format_i : std_logic; + signal data_debug_i : std_logic; + signal data_dummy_i : std_logic; + signal cms_active_i : std_logic; + signal dummy_data_config_i : std_logic_vector(15 downto 0); + + signal start_trigger_i : std_logic; + signal start_calib_i : std_logic; + signal start_begrun_i : std_logic; + signal start_readout_i : std_logic; + signal finished_readout_i : std_logic; + signal finished_begrun_i : std_logic; + + signal cal1_loaded_i : std_logic; + signal token_missing_i : std_logic; + signal token_back_i : std_logic; + + signal data_bus_i : std_logic_vector(23 downto 0); + signal data_bus_valid_i : std_logic; + + signal debug_control_i : std_logic_vector(31 downto 0); + signal debug_trigger_handler_i : std_logic_vector(31 downto 0); + signal debug_data_handler_i : std_logic_vector(31 downto 0); + signal debug_tdc_readout_i : std_logic_vector(31 downto 0); + signal debug_ctrl_line_handle_i: std_logic_vector(31 downto 0); + signal debug_trigger_begrun_i : std_logic_vector(31 downto 0); + signal debug_load_mode_i : std_logic_vector(31 downto 0); + signal debug_load_tdc_i : std_logic_vector(31 downto 0); + signal debug_send_token_i : std_logic_vector(31 downto 0); + + signal start_readback_i : std_logic; + signal databus_output_enable : std_logic; + signal ram_ready_out_del : std_logic; + signal last_rb_read_enable_in : std_logic; + signal readback_mem_write : std_logic; + signal readback_mem_full : std_logic; + +begin + +------------------------------------------------------------------------------- +-- Select Internal or external common stop, produce trigger signals +------------------------------------------------------------------------------- + + TRIGGER_OUT <= trigger_i; + TRIGGER_MONITOR_OUT <= trigger_reg_pulse_i; + + trigger_i <= (TRIGGER_IN and cms_active_i) or trigger_pseudo_tmg_long; + trigger_reg_pulse_i <= (trigger_timing and cms_active_i) or trigger_pseudo_timing; + + THE_CMS_SYNC : signal_sync + generic map( + DEPTH => 2, + WIDTH => 1 + ) + port map( + RESET => RESET, + D_IN(0) => TRIGGER_IN, + CLK0 => CLK, + CLK1 => CLK, + D_OUT(0) => reg_timing_trigger + ); + + PULSE_TIMING_TRIGGER : edge_to_pulse + port map ( + CLOCK => CLK, + en_clk => '1', + SIGNAL_IN => reg_timing_trigger, + PULSE => trigger_timing + ); + + + PULSE_PSEUDO_TIMING : process(CLK) + begin + if rising_edge(CLK) then + if reset_readout_logic_i = '1' then + trg_pulse_counter <= (others => '0'); + trigger_pseudo_tmg_long <= '0'; + elsif trg_pulse_counter = 0 then + trigger_pseudo_tmg_long <= '0'; + if trigger_pseudo_timing = '1' then + trg_pulse_counter <= trg_pulse_counter + to_unsigned(1,5); + trigger_pseudo_tmg_long <= '1'; + end if; + else + trg_pulse_counter <= trg_pulse_counter + to_unsigned(1,5); + trigger_pseudo_tmg_long <= '1'; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +-- Trigger Handler +------------------------------------------------------------------------------- + the_trigger_handler : trigger_handler + port map( + CLK => CLK, + RESET => reset_readout_logic_i, + TRG_BEGRUN_IN => trigger_begin_run, + --LVL1 trigger + LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN, + LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN, + LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN, + LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN, + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, + LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, + LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN, + LVL1_RELEASE_OUT => LVL1_RELEASE_OUT, + LVL1_STATUSBITS_OUT => LVL1_STATUSBITS_OUT, + DO_BEGIN_RUN_IN => trigger_begin_run, + --FSM control + START_TRIGGER_OUT => start_trigger_i, + START_CALIB_OUT => start_calib_i, + START_BEGRUN_OUT => start_begrun_i, + START_READOUT_OUT => start_readout_i, + FINISHED_READOUT_OUT => finished_readout_i, + --FSM status + FINISHED_BEGRUN_IN => finished_begrun_i, + CAL1_LOADED_IN => cal1_loaded_i, + TOKEN_MISSING_IN => token_missing_i, + TOKEN_BACK_IN => token_back_i, + --debug + DEBUG_REGISTER => debug_trigger_handler_i + ); + + +------------------------------------------------------------------------------- +-- Data Handler +------------------------------------------------------------------------------- + the_data_handler : data_handler + port map( + CLK => CLK, + RESET => reset_readout_logic_i, + --LVL1 + LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN, + LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN, + LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN, + --Readout + START_READOUT_IN => start_readout_i, + FINISHED_READOUT_IN => finished_readout_i, + --Config + SELECT_DATA_FORMAT_IN => data_format_i, + SEND_DEBUG_INFORMATION_IN => data_debug_i, + SEND_DUMMY_DATA_IN => data_dummy_i, + DUMMY_DATA_CONFIG => dummy_data_config_i, + --Data Input from FEE + DATA_BUS_IN => data_bus_i, + DATA_VALID_IN => data_bus_valid_i, + --Data Output to Endpoint + FEE_DATA_OUT => FEE_DATA_OUT, + FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT, + FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT, + --Debug + DEBUG_REGISTER => debug_data_handler_i + ); + +------------------------------------------------------------------------------- +-- TDC Readout +------------------------------------------------------------------------------- + the_tdc_readout : tdc_readout + port map( + CLK => CLK, + RESET => reset_readout_logic_i, + --MBO + A_ADD_IN => add_in_i, + A_AOD_IN => aod_in_i, + A_DST_IN => dst_in_i, + A_RESERV_IN => A_RESERVE, + --Control + START_READOUT_IN => start_readout_i, + TOKEN_IN => A_RDO, + FINISHED_IN => finished_readout_i, + FLAG_EVENT_COUNTER_IN => LVL1_INT_TRG_NUMBER_IN(3 downto 0), + --Data + DATA_BUS_OUT => data_bus_i, + DATA_VALID_OUT => data_bus_valid_i, + --Debug + DEBUG_REGISTER_OUT => debug_tdc_readout_i + ); + +------------------------------------------------------------------------------- +-- MBO control line handler +------------------------------------------------------------------------------- + the_control_line_hander : control_line_handle + port map( + CLK => CLK, + RESET => reset_readout_logic_i, + --MBO + A_ADD => add_out_i, + A_AOD => aod_out_i, + A_DST => dst_out_i, + A_RDM => A_RDM, + A_GDE => A_GDE, + A_RDO => A_RDO, + A_MOD => A_MOD, + A_RES => A_RES, + A_TOK => A_TOK, + A_WRM => A_WRM, + OUTPUT_ENABLE => databus_output_enable, + --FSM control + START_CALIB_IN => start_calib_i, + START_BEGRUN_IN => start_begrun_i, + START_READOUT_IN => start_readout_i, + FINISHED_READOUT_IN => finished_readout_i, + --Status + TOKEN_MISSING_OUT => token_missing_i, + TOKEN_BACK_OUT => token_back_i, + FINISHED_BEGRUN_OUT => finished_begrun_i, + FINISHED_LOAD_CALIB_OUT => cal1_loaded_i, + START_DEBUG_READOUT_OUT => start_readback_i, + --Config + MOTHERBOARD_TYPE_IN => motherboard_type_i, + --Config RAM + RAM_ADDRESS_IN => RAM_ADDRESS_IN, + RAM_DATA_IN => RAM_DATA_IN, + RAM_DATA_OUT => RAM_DATA_OUT, + RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN, + RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN, + --Debug + DEBUG_REGISTER => debug_ctrl_line_handle_i, + DEBUG_REGISTER_TRIGGER_BEGRUN=> debug_trigger_begrun_i, + DEBUG_REGISTER_LOAD_MODE => debug_load_mode_i, + DEBUG_REGISTER_LOAD_TDC => debug_load_tdc_i, + DEBUG_REGISTER_SEND_TOKEN => debug_send_token_i + ); + + proc_del_ram_ready : process(CLK) + begin + if rising_edge(CLK) then + ram_ready_out_del <= RAM_READ_ENABLE_IN or RAM_WRITE_ENABLE_IN; + RAM_READY_OUT <= ram_ready_out_del; + end if; + end process; + +------------------------------------------------------------------------------- +-- Debug Registers +------------------------------------------------------------------------------- + proc_debug_regs : process(CLK) + variable tmp : integer range 0 to 15; + begin + if rising_edge(CLK) then + STAT_READY_OUT <= STAT_READ_ENABLE_IN; + if STAT_READ_ENABLE_IN = '1' then + tmp := to_integer(unsigned(STAT_ADDRESS_IN)); + case tmp is + when 0 => STAT_DATA_OUT <= debug_control_i; + when 1 => STAT_DATA_OUT <= debug_trigger_handler_i; + when 2 => STAT_DATA_OUT <= debug_data_handler_i; + when 3 => STAT_DATA_OUT <= debug_tdc_readout_i; + when 4 => STAT_DATA_OUT <= debug_ctrl_line_handle_i; + when 5 => STAT_DATA_OUT <= debug_trigger_begrun_i; + when 6 => STAT_DATA_OUT <= debug_load_mode_i; + when 7 => STAT_DATA_OUT <= debug_load_tdc_i; + when 8 => STAT_DATA_OUT <= debug_send_token_i; + when others => + STAT_DATA_OUT <= (others => '0'); + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- Readback FiFo +------------------------------------------------------------------------------- + THE_TDC_READBACK_MEM : fifo_18x256_oreg + port map ( + Data(7 downto 0) => add_in_i(8 downto 1), + Data(8) => add_in_i(0), + Data(15 downto 9) => (others => '0'), + Data(16) => dst_in_i, + Data(17) => aod_in_i, + Clock => CLK, + AmFullThresh => (others => '0'), + WrEn => readback_mem_write, + RdEn => RB_READ_ENABLE_IN, + Reset => RESET, + Q => RB_DATA_OUT(17 downto 0), + Empty => RB_EMPTY_OUT, + Full => readback_mem_full + ); + + PULSE_DEBUG_WRITE : edge_to_pulse + port map ( + CLOCK => CLK, + en_clk => '1', + signal_in => dst_in_i, + PULSE => readback_mem_write + ); + + +-- RB_EMPTY_OUT <= '0'; +process(CLK) + begin + if rising_edge(CLK) then + last_rb_read_enable_in <= RB_READ_ENABLE_IN; + RB_READY_OUT <= last_rb_read_enable_in; + end if; + end process; + RB_DATA_OUT(31 downto 18) <= (others => '0'); + + + +------------------------------------------------------------------------------- +-- Other settings +------------------------------------------------------------------------------- + PROC_REG_SETTINGS : process(CLK) + begin + if rising_edge(CLK) then + reset_readout_logic_i <= RESET or COMMON_CTRL_REG_IN(0); + motherboard_type_i <= CTRL_REG_IN(7 downto 4); + dummy_data_config_i <= CTRL_REG_IN(63 downto 48); + trigger_pseudo_timing <= COMMON_CTRL_REG_IN(16); + trigger_begin_run <= COMMON_CTRL_REG_IN(22); + data_format_i <= COMMON_CTRL_REG_IN(84); + data_dummy_i <= COMMON_CTRL_REG_IN(85); + data_debug_i <= COMMON_CTRL_REG_IN(94); + cms_active_i <= COMMON_CTRL_REG_IN(95); + end if; + end process; + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + + databus_output_enable <= '1'; + + PROC_OUTPUT_SYNC : process(CLK) + begin + if rising_edge(CLK) then + if databus_output_enable = '1' then + A_AOD <= aod_out_i; + A_DST <= dst_out_i; + A_ADD <= add_out_i; + else + A_AOD <= 'Z'; + A_DST <= 'Z'; + A_ADD <= (others => 'Z'); + end if; + end if; + end process; + + + PROC_INPUT_SYNC : process(CLK) + begin + if rising_edge(CLK) then + add_in_i <= A_ADD; + aod_in_i <= A_AOD; + dst_in_i <= A_DST; + end if; + end process; + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + debug_control_i(0) <= token_back_i; + debug_control_i(1) <= token_missing_i; + debug_control_i(2) <= cms_active_i; + + debug_control_i(31 downto 3) <= (others => '0'); + + DEBUG_OUT <= debug_control_i; + COMMON_STAT_REG_OUT <= (others => '0'); + +end architecture; \ No newline at end of file diff --git a/design2/mdc_oepb_pack.vhd b/design2/mdc_oepb_pack.vhd new file mode 100644 index 0000000..128c515 --- /dev/null +++ b/design2/mdc_oepb_pack.vhd @@ -0,0 +1,385 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.ALL; +library work; +use work.trb_net_std.all; + +package mdc_oepb_pack is + + + component control_line_handle is + port( + CLK : in std_logic; + RESET : in std_logic; + --to MBO + A_ADD : out std_logic_vector(8 downto 0); --address/data line + A_AOD : out std_logic; -- address or data + A_DST : out std_logic; -- data strobe + A_RDM : out std_logic; -- ready TO first motherboard + A_GDE : out std_logic; -- global disable + A_RDO : in std_logic; -- ready FROM first motherboard + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + OUTPUT_ENABLE : out std_logic; + + --FSM control + START_CALIB_IN : in std_logic; --start calibration trigger + START_BEGRUN_IN : in std_logic; --start begrun trigger + START_READOUT_IN : in std_logic; --begin tdc readout (either calib. or trigger) + FINISHED_READOUT_IN : in std_logic; --All entities back to idle + + --Status + TOKEN_MISSING_OUT : out std_logic; --token timeout - not received back, readout finished + TOKEN_BACK_OUT : out std_logic; --token back, readout finished + FINISHED_BEGRUN_OUT : out std_logic; --finished begrun trigger + FINISHED_LOAD_CALIB_OUT : out std_logic; --finished loading calib settings, readout can be started + START_DEBUG_READOUT_OUT : out std_logic; --begrun trigger read-back settings + + --Config + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + + --Config RAM + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); --16 bit + RAM_DATA_OUT : out std_logic_vector(15 downto 0); --16 bit + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_TRIGGER_BEGRUN: out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_MODE : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_TDC : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_SEND_TOKEN : out std_logic_vector(31 downto 0) + ); + end component; + + + + component data_handler is + port( + CLK : in std_logic; + RESET : in std_logic; + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + + START_READOUT_IN : in std_logic; + FINISHED_READOUT_IN : in std_logic; + --Config + SEND_DEBUG_INFORMATION_IN : in std_logic; --0: off, 1: on + SELECT_DATA_FORMAT_IN : in std_logic; --0: compressed, 1: normal + SEND_DUMMY_DATA_IN : in std_logic; --0: normal, 1: dummy + DUMMY_DATA_CONFIG : in std_logic_vector(15 downto 0); --11..0: number of debug words + --Data Input from FEE + DATA_BUS_IN : in std_logic_vector(23 downto 0); + DATA_VALID_IN : in std_logic; + --Data to Endpoint + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + end component; + + + component edge_to_pulse is + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + + + + component initialization_RAM + port ( + DataInA : in std_logic_vector(15 downto 0); + DataInB : in std_logic_vector(15 downto 0); + AddressA : in std_logic_vector(8 downto 0); + AddressB : in std_logic_vector(8 downto 0); + ClockA : in std_logic; + ClockB : in std_logic; + ClockEnA : in std_logic; + ClockEnB : in std_logic; + WrA : in std_logic; + WrB : in std_logic; + ResetA : in std_logic; + ResetB : in std_logic; + QA : out std_logic_vector(15 downto 0); + QB : out std_logic_vector(15 downto 0)); + end component; + + + component mdc_control is + port( + CLK : in std_logic; + RESET : in std_logic; + + A_ADD : inout std_logic_vector(8 downto 0); + A_AOD : inout std_logic; + A_DST : inout std_logic; + A_RDM : out std_logic; + A_GDE : out std_logic; + A_RDO : in std_logic; + A_MOD : out std_logic; + A_RES : out std_logic; + A_TOK : out std_logic; + A_WRM : out std_logic; + A_RESERVE : in std_logic; + + TRIGGER_IN : in std_logic; -- external CMS in + TRIGGER_OUT : out std_logic; -- CMS to MBO + TRIGGER_MONITOR_OUT : out std_logic; -- to endpoint + + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_RELEASE_OUT : out std_logic; + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); --config RAM + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + RAM_READY_OUT : out std_logic; + + STAT_ADDRESS_IN : in std_logic_vector(3 downto 0); --status register + STAT_DATA_OUT : out std_logic_vector(31 downto 0); + STAT_READ_ENABLE_IN : in std_logic; + STAT_READY_OUT : out std_logic; + + RB_DATA_OUT : out std_logic_vector(31 downto 0); --Readback fifo + RB_READ_ENABLE_IN : in std_logic; + RB_READY_OUT : out std_logic; + RB_EMPTY_OUT : out std_logic; + + COMMON_STAT_REG_OUT : out std_logic_vector(63 downto 0); + COMMON_CTRL_REG_IN : in std_logic_vector(95 downto 0); + CTRL_REG_IN : in std_logic_vector(63 downto 0); + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + component load_tdc_setup is + generic ( + timecounter_width : integer := 6 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + --MBO + A_ADD : out std_logic_vector(8 downto 0); + A_DST : out std_logic; + A_AOD : out std_logic; + --Control In + TRIGGER_BEGRUN_IN : in std_logic; + TRIGGER_CALIB_IN : in std_logic; + CALIBRATION_STEP_TDC_SETUP : in std_logic_vector(3 downto 0); + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + TDC_SETTING_LOADED_OUT : out std_logic; + -- signals for RAM with TDC / CPLD settings + RAM_ADDRESS_IN : in std_logic_vector(8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + -- Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component load_mode_line is + generic ( + timecounter_width : integer := 13 + ); + port( + CLK : in std_logic; + RESET : in std_logic; + + --Control + DO_BEGRUN_IN : in std_logic; + DO_CALIB_TRIGGER_IN : in std_logic; + CALIBRATION_STEP_MODE_LINE : in std_logic_vector(3 downto 0); + TDC_SETTING_LOADED_IN : in std_logic; + + --MBO + GDE : out std_logic; + MODD : out std_logic; + RES : out std_logic; + TOK : out std_logic; + WRM : out std_logic; + RDM : out std_logic; + RDO : in std_logic; + + --Status + START_LOAD_TDC_SETTINGS_OUT : out std_logic; + START_DEBUG_READOUT_OUT : out std_logic; + TDC_SETTINGS_WRITTEN : out std_logic; + CAL1_WRITTEN : out std_logic; + + --Debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + end component; + + + + component send_token_to_mb is + port ( + CLK : in std_logic; + RESET : in std_logic; + DO_READOUT_IN : in std_logic; + FINISH_IN : in std_logic; + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + A_RDM : out std_logic; -- ready TO MBO + A_RDO : in std_logic; -- ready FROM MBO + A_GDE : out std_logic; -- global disable + FINISHED_READOUT_OUT : out std_logic; -- active if token came back + NO_TOKEN_BACK_OUT : out std_logic; -- active when notoken + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + component tdc_readout is + port( + CLK : in std_logic; + RESET : in std_logic; + + A_ADD_IN : in std_logic_vector(8 downto 0); + A_AOD_IN : in std_logic; + A_DST_IN : in std_logic; + A_RESERV_IN : in std_logic; + + START_READOUT_IN : in std_logic; --read TDC data + TOKEN_IN : in std_logic; --Token from MBO + FINISHED_IN : in std_logic; --Readout process finished, reset + + FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); + + DATA_BUS_OUT : out std_logic_vector(23 downto 0); + DATA_VALID_OUT : out std_logic; + + DEBUG_REGISTER_OUT : out std_logic_vector(31 downto 0) + ); + end component; + + + + + component trigger_begrun_state is + port( + CLK : in std_logic; + RESET : in std_logic; + + --MBO Connection + A_ADD : out std_logic_vector(8 downto 0); + A_AOD : out std_logic; + A_DST : out std_logic; + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + A_RDM : out std_logic; -- ready TO MBO + A_RDO : in std_logic; -- ready FROM MBO + A_GDE : out std_logic; -- global disable + OUTPUT_ENABLE : out std_logic; + + --Initialization RAM + RAM_ADDRESS_IN : in std_logic_vector( 8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + + --Trigger + DO_BEGRUN_IN : in std_logic; + DO_CALIB_TRIGGER_IN : in std_logic; + --Configuration + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + --Status + FINISHED_BEGRUN_OUT : out std_logic; + FINISHED_LOAD_CALIB_OUT : out std_logic; + START_DEBUG_READOUT_OUT : out std_logic; + DEBUG_REGISTER : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_MODE : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_TDC : out std_logic_vector(31 downto 0) + ); + end component; + + + + component trigger_handler is + port( + CLK : in std_logic; + RESET : in std_logic; + + TRG_BEGRUN_IN : in std_logic; + --LVL1 trigger + LVL1_TRG_DATA_VALID_IN : in std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_IN : in std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; --valid trigger within timing trigger has been received + LVL1_INVALID_TRG_IN : in std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + + LVL1_RELEASE_OUT : out std_logic; + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + + DO_BEGIN_RUN_IN : in std_logic; + + --FSM control + START_TRIGGER_OUT : out std_logic; --start normal trigger + START_CALIB_OUT : out std_logic; --start calibration trigger + START_BEGRUN_OUT : out std_logic; --start begrun trigger + START_READOUT_OUT : out std_logic; --begin tdc readout aka send token and read data + FINISHED_READOUT_OUT : out std_logic; --All entities back to idle + + --FSM status + FINISHED_BEGRUN_IN : in std_logic; --loading settings finished + CAL1_LOADED_IN : in std_logic; --calibration settings have been loaded + TOKEN_MISSING_IN : in std_logic; --token timeout - not received back + TOKEN_BACK_IN : in std_logic; --token back, readout finished + + --debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); + end component; + + + + + + +end package; \ No newline at end of file diff --git a/design2/send_token_to_mb.vhd b/design2/send_token_to_mb.vhd new file mode 100644 index 0000000..c1f1316 --- /dev/null +++ b/design2/send_token_to_mb.vhd @@ -0,0 +1,209 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity send_token_to_mb is + port ( + CLK : in std_logic; + RESET : in std_logic; + DO_READOUT_IN : in std_logic; + FINISH_IN : in std_logic; + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + A_RDM : out std_logic; -- ready TO MBO + A_RDO : in std_logic; -- ready FROM MBO + A_GDE : out std_logic; -- global disable + FINISHED_READOUT_OUT : out std_logic; -- active if token came back + NO_TOKEN_BACK_OUT : out std_logic; -- active when notoken + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture behavioral of send_token_to_mb is + +constant time_limit : unsigned(19 downto 0) := x"0001F"; -- 320 ns +constant wait_for_token_limit : unsigned(19 downto 0) := x"3FFFF"; -- ~ 2.6 ms + +type state_type is (idle_state, send_token_state, + wait_token_back_state, token_not_back_state, + token_is_back_state, wait_state); + +signal current_state, next_state : state_type; + +signal reg_finished_readout, next_finished_readout : std_logic; +signal reg_no_token_back, next_not_token_back : std_logic; + +signal reg_A_GDE : std_logic; +signal reg_A_MOD : std_logic; +signal reg_A_RES : std_logic; +signal reg_A_TOK : std_logic; +signal reg_A_WRM : std_logic; +signal reg_A_RDM : std_logic; +signal next_MOD_RES_TOK_WRM_RDM_GDE : std_logic_vector(5 downto 0); + +signal time_counter : unsigned(19 downto 0); +signal time_counter_reset : std_logic; +signal state_bits : std_logic_vector(3 downto 0); + +begin + + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + A_MOD <= reg_A_MOD; + A_RES <= reg_A_RES; + A_TOK <= reg_A_TOK; + A_WRM <= reg_A_WRM; + A_RDM <= reg_A_RDM; + A_GDE <= reg_A_GDE; + FINISHED_READOUT_OUT <= reg_finished_readout; + NO_TOKEN_BACK_OUT <= reg_no_token_back; + +------------------------------------------------------------------------------- +-- State Machine +------------------------------------------------------------------------------- + + PROC_FSM_REG : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_A_MOD <= '0'; + reg_A_RES <= '0'; + reg_A_TOK <= '0'; + reg_A_WRM <= '0'; + reg_A_RDM <= '0'; + reg_A_GDE <= '0'; + reg_finished_readout <= '0'; + reg_no_token_back <= '0'; + current_state <= idle_state; + else + reg_A_MOD <= next_MOD_RES_TOK_WRM_RDM_GDE(5); + reg_A_RES <= next_MOD_RES_TOK_WRM_RDM_GDE(4); + reg_A_TOK <= next_MOD_RES_TOK_WRM_RDM_GDE(3); + reg_A_WRM <= next_MOD_RES_TOK_WRM_RDM_GDE(2); + reg_A_RDM <= next_MOD_RES_TOK_WRM_RDM_GDE(1); + reg_A_GDE <= next_MOD_RES_TOK_WRM_RDM_GDE(0); + reg_finished_readout <= next_finished_readout; + reg_no_token_back <= next_not_token_back; + current_state <= next_state; + end if; + end if; + end process; + + + + PROC_FSM_COMB : process (current_state, DO_READOUT_IN, A_RDO, time_counter, finish_in) + begin + --hex 64 + GDE + next_state <= current_state; + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; + next_finished_readout <= '0'; + next_not_token_back <= '0'; + time_counter_reset <= '0'; + + case current_state is + + when idle_state => + --hex 64 + GDE + next_MOD_RES_TOK_WRM_RDM_GDE <= "010100"; + time_counter_reset <= '1'; + if DO_READOUT_IN = '1' then + next_state <= wait_state; + end if; + + when wait_state => + -- hex 64 + GDE + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; + if time_counter = 2 * time_limit then + next_state <= send_token_state; + time_counter_reset <= '1'; + end if; + + when send_token_state => + -- hex 65 + next_MOD_RES_TOK_WRM_RDM_GDE <= "010111"; + if time_counter = time_limit then + next_state <= wait_token_back_state; + time_counter_reset <= '1'; + end if; + + when wait_token_back_state => + -- hex 65 + next_MOD_RES_TOK_WRM_RDM_GDE <= "010111"; + if A_RDO = '1' then + next_state <= token_is_back_state; + elsif time_counter = wait_for_token_limit then + next_state <= token_not_back_state; + time_counter_reset <= '1'; + end if; + + when token_is_back_state => + -- hex 64 + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; + next_finished_readout <= '1'; --token received normally + if FINISH_IN = '1' then + next_state <= idle_state; + end if; + + when token_not_back_state => + -- hex 64 + next_MOD_RES_TOK_WRM_RDM_GDE <= "010101"; + next_not_token_back <= '1'; --token NOT back + next_finished_readout <= '1'; + if FINISH_IN = '1' then + next_state <= idle_state; + end if; + + when others => + next_state <= idle_state; + + end case; + end process; + + +------------------------------------------------------------------------------- +-- Timer +------------------------------------------------------------------------------- + proc_time_counter : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or time_counter_reset = '1' then + time_counter <= (others => '0'); + else + time_counter <= time_counter + to_unsigned(1,1); + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case next_state is + when idle_state => state_bits <= x"0"; + when send_token_state => state_bits <= x"2"; + when wait_token_back_state => state_bits <= x"3"; + when token_is_back_state => state_bits <= x"4"; + when token_not_back_state => state_bits <= x"5"; + when wait_state => state_bits <= x"1"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + + DEBUG_REGISTER(3 downto 0) <= state_bits; + DEBUG_REGISTER(31 downto 4) <= (others => '0'); + + +end architecture; \ No newline at end of file diff --git a/design2/tdc_readout.vhd b/design2/tdc_readout.vhd new file mode 100644 index 0000000..6f87209 --- /dev/null +++ b/design2/tdc_readout.vhd @@ -0,0 +1,183 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity tdc_readout is + port( + CLK : in std_logic; + RESET : in std_logic; + + A_ADD_IN : in std_logic_vector(8 downto 0); + A_AOD_IN : in std_logic; + A_DST_IN : in std_logic; + A_RESERV_IN : in std_logic; + + START_READOUT_IN : in std_logic; --read TDC data + TOKEN_IN : in std_logic; --Token from MBO + FINISHED_IN : in std_logic; + + FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); + + DATA_BUS_OUT : out std_logic_vector(23 downto 0); + DATA_VALID_OUT : out std_logic; + + DEBUG_REGISTER_OUT : out std_logic_vector(31 downto 0) + ); +end tdc_readout; + +architecture behavioral of tdc_readout is + + type state_type is (idle_state, + wait_for_AOD_low_state, save_H_word_state_next, + save_L_word_state, save_L_word_state_next, + wait_1_state, wait_2_state, wait_3_state, wait_4_state, + send_data_with_valid); + + signal current_state : state_type; + signal next_state : state_type; + signal reg_debug_register : std_logic_vector(3 downto 0); + signal next_debug_register : std_logic_vector(3 downto 0); + signal reg_data_bus_out : std_logic_vector(23 downto 0); + signal reg_data_valid_out : std_logic; + signal saved_data : std_logic_vector(8 downto 0); + signal reg_test_data_max_words : std_logic_vector(11 downto 0); + signal state_bits : std_logic_vector(3 downto 0); + +begin + +------------------------------------------------------------------------------ +-- Readout state machine +------------------------------------------------------------------------------ + PROC_FSM_REG : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or FINISHED_IN = '1' then + current_state <= idle_state; + else + current_state <= next_state; + end if; + end if; + end process; + + + PROC_FSM_COMB : process(current_state, TOKEN_IN, START_READOUT_IN, A_DST_IN, A_AOD_IN, TOKEN_IN) + begin + next_state <= current_state; + + case current_state is + when idle_state => + if START_READOUT_IN = '1' then + next_state <= save_L_word_state; + end if; + + when save_L_word_state => + if A_DST_IN = '1' and A_AOD_IN = '1' then + next_state <= wait_1_state; + elsif TOKEN_IN = '1' then + next_state <= idle_state; + end if; + + when wait_1_state => + next_state <= wait_2_state; + + when wait_2_state => + next_state <= save_L_word_state_next; + + when save_L_word_state_next => --here I save data + next_state <= wait_for_AOD_low_state; + + when wait_for_AOD_low_state => + if A_DST_IN = '1' and A_AOD_IN = '0' then + next_state <= wait_3_state; + end if; + + when wait_3_state => + next_state <= wait_4_state; + + when wait_4_state => + next_state <= save_H_word_state_next; + + when save_H_word_state_next => --here I save data + next_state <= send_data_with_valid; + + when send_data_with_valid => + next_state <= save_L_word_state; + + when others => + next_state <= idle_state; + + end case; + end process; + + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case next_state is + when idle_state => state_bits <= x"0"; + when save_L_word_state => state_bits <= x"1"; + when wait_1_state => state_bits <= x"3"; + when wait_2_state => state_bits <= x"4"; + when save_L_word_state_next => state_bits <= x"5"; + when wait_for_AOD_low_state => state_bits <= x"6"; + when wait_3_state => state_bits <= x"7"; + when wait_4_state => state_bits <= x"8"; + when save_H_word_state_next => state_bits <= x"9"; + when send_data_with_valid => state_bits <= x"A"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + + +------------------------------------------------------------------------------ +-- Store data and write to output +------------------------------------------------------------------------------ + proc_save_data : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or FINISHED_IN = '1' then + saved_data <= (others => '0'); + reg_data_valid_out <= '0'; + elsif (current_state = save_H_word_state_next) then + reg_data_bus_out(23) <= '0'; + reg_data_bus_out(22 downto 19) <= FLAG_EVENT_COUNTER_IN; + reg_data_bus_out(18 downto 12) <= A_ADD_IN(8 downto 2); --TDC NR and TDC CH + reg_data_bus_out(11) <= A_RESERV_IN; --HIT NR + reg_data_bus_out(10 downto 9) <= A_ADD_IN(1 downto 0); --TDC DATA + reg_data_bus_out(8 downto 0) <= saved_data(8 downto 0);--TDC DATA + reg_data_valid_out <= '1'; + elsif (current_state = save_L_word_state_next) then + saved_data(8 downto 0) <= A_ADD_IN(8 downto 0); + reg_data_valid_out <= '0'; + else + reg_data_valid_out <= '0'; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- +-- Data Output +------------------------------------------------------------------------------- + DATA_VALID_OUT <= reg_data_valid_out; + DATA_BUS_OUT <= reg_data_bus_out; + + +------------------------------------------------------------------------------- +-- Debug +------------------------------------------------------------------------------- + DEBUG_REGISTER_OUT(3 downto 0) <= state_bits; + DEBUG_REGISTER_OUT(4) <= reg_data_valid_out; + DEBUG_REGISTER_OUT(5) <= TOKEN_IN; + DEBUG_REGISTER_OUT(6) <= A_DST_IN; + DEBUG_REGISTER_OUT(7) <= A_AOD_IN; + DEBUG_REGISTER_OUT(8) <= A_RESERV_IN; + DEBUG_REGISTER_OUT(12 downto 9) <= FLAG_EVENT_COUNTER_IN; + DEBUG_REGISTER_OUT(31 downto 13) <= (others => '0'); + +end behavioral; diff --git a/design2/trigger_begrun_state.vhd b/design2/trigger_begrun_state.vhd new file mode 100644 index 0000000..93cf627 --- /dev/null +++ b/design2/trigger_begrun_state.vhd @@ -0,0 +1,347 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.STD_LOGIC_ARITH.all; +use IEEE.STD_LOGIC_UNSIGNED.all; + + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity trigger_begrun_state is + port( + CLK : in std_logic; + RESET : in std_logic; + + --MBO Connection + A_ADD : out std_logic_vector(8 downto 0); + A_AOD : out std_logic; + A_DST : out std_logic; + A_MOD : out std_logic; -- TDC working mode + A_RES : out std_logic; -- TDC working mode + A_TOK : out std_logic; -- TDC working mode + A_WRM : out std_logic; -- TDC working mode + A_RDM : out std_logic; -- ready TO MBO + A_RDO : in std_logic; -- ready FROM MBO + A_GDE : out std_logic; -- global disable + OUTPUT_ENABLE : out std_logic; + + --Initialization RAM + RAM_ADDRESS_IN : in std_logic_vector( 8 downto 0); + RAM_DATA_IN : in std_logic_vector(15 downto 0); + RAM_DATA_OUT : out std_logic_vector(15 downto 0); + RAM_READ_ENABLE_IN : in std_logic; + RAM_WRITE_ENABLE_IN : in std_logic; + + --Trigger + DO_BEGRUN_IN : in std_logic; + DO_CALIB_TRIGGER_IN : in std_logic; + --Configuration + MOTHERBOARD_TYPE_IN : in std_logic_vector(3 downto 0); + --Status + FINISHED_BEGRUN_OUT : out std_logic; + FINISHED_LOAD_CALIB_OUT : out std_logic; + START_DEBUG_READOUT_OUT : out std_logic; + DEBUG_REGISTER : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_MODE : out std_logic_vector(31 downto 0); + DEBUG_REGISTER_LOAD_TDC : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture Behavioral of trigger_begrun_state is + + + type state_type is (idle_state, load_data_mode_state, + load_tdc_data_state, read_back_tdc_state, + calibration_state_0, calibration_state_1, + calibration_state_2, calibration_state_3, + calibration_state_4, calibration_state_5, + calibration_state_6, + dummy_calibration_state_0, + dummy_calibration_state_1); + + signal current_state : state_type; + signal next_state : state_type; + + signal tdc_setting_loaded_i : std_logic; + + signal debug_register_load_tdc_setup_i : std_logic_vector(31 downto 0); + signal debug_register_load_mode_line_i : std_logic_vector(31 downto 0); + + signal next_do_tdc_begrun_i : std_logic; + signal do_tdc_begrun_i : std_logic; + signal finished_begrun_i : std_logic; + signal finished_load_calib_i : std_logic; + signal reset_i : std_logic; + + signal do_tdc_calib_trigger_i : std_logic; + signal next_do_tdc_calib_trigger_i : std_logic; + signal do_modeline_calib_trigger_i : std_logic; + signal next_do_modeline_calib_trigger_i : std_logic; + signal reg_calibration_step_mode_line : std_logic_vector(3 downto 0); + signal next_calibration_step_mode_line : std_logic_vector(3 downto 0); + signal reg_calibration_step_tdc_setup : std_logic_vector(3 downto 0); + signal next_calibration_step_tdc_setup : std_logic_vector(3 downto 0); + + signal start_load_tdc_settings_i : std_logic; + + signal do_modeline_begrun_i : std_logic; + signal next_do_modeline_begrun_i : std_logic; + signal state_bits : std_logic_vector(3 downto 0); + signal start_debug_readout_i : std_logic; + + signal next_output_enable : std_logic; + signal output_enable_i : std_logic; + + signal state_load_mode_line_i : std_logic_vector(7 downto 0); + signal state_load_tdc_setup_i : std_logic_vector(7 downto 0); + +begin + + FINISHED_BEGRUN_OUT <= finished_begrun_i; + FINISHED_LOAD_CALIB_OUT <= finished_load_calib_i; + START_DEBUG_READOUT_OUT <= start_debug_readout_i; + OUTPUT_ENABLE <= output_enable_i; + reset_i <= RESET; + + state_load_mode_line_i <= debug_register_load_mode_line_i(7 downto 0); + state_load_tdc_setup_i <= debug_register_load_tdc_setup_i(7 downto 0); + DEBUG_REGISTER_LOAD_MODE <= debug_register_load_mode_line_i; + DEBUG_REGISTER_LOAD_TDC <= debug_register_load_tdc_setup_i; + + MODE_LINE : load_mode_line + generic map( + timecounter_width => 13 + ) + port map( + CLK => CLK, + RESET => reset_i, + --Control + DO_BEGRUN_IN => do_modeline_begrun_i, + DO_CALIB_TRIGGER_IN => do_modeline_calib_trigger_i, + CALIBRATION_STEP_MODE_LINE => reg_calibration_step_mode_line, + TDC_SETTING_LOADED_IN => tdc_setting_loaded_i, + --MBO + GDE => A_GDE, + MODD => A_MOD, + RES => A_RES, + TOK => A_TOK, + WRM => A_WRM, + RDM => A_RDM, + RDO => A_RDO, + --Status + START_LOAD_TDC_SETTINGS_OUT=> start_load_tdc_settings_i, + START_DEBUG_READOUT_OUT => start_debug_readout_i, + TDC_SETTINGS_WRITTEN => finished_begrun_i, + CAL1_WRITTEN => finished_load_calib_i, + --Debug + DEBUG_REGISTER => debug_register_load_mode_line_i + ); + + + TDC_SETUP : load_tdc_setup + generic map ( + timecounter_width => 10 + ) + port map( + CLK => CLK, + RESET => reset_i, + A_ADD => A_ADD(8 downto 0), + A_DST => A_DST, + A_AOD => A_AOD, + TRIGGER_BEGRUN_IN => do_tdc_begrun_i, + TRIGGER_CALIB_IN => do_tdc_calib_trigger_i, + CALIBRATION_STEP_TDC_SETUP => reg_calibration_step_tdc_setup, + TDC_SETTING_LOADED_OUT => tdc_setting_loaded_i, + MOTHERBOARD_TYPE_IN => MOTHERBOARD_TYPE_IN, + RAM_ADDRESS_IN => RAM_ADDRESS_IN, + RAM_DATA_IN => RAM_DATA_IN, + RAM_DATA_OUT => RAM_DATA_OUT, + RAM_READ_ENABLE_IN => RAM_READ_ENABLE_IN, + RAM_WRITE_ENABLE_IN => RAM_WRITE_ENABLE_IN, + + DEBUG_REGISTER => debug_register_load_tdc_setup_i + ); + + + proc_fsm_reg : process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= idle_state; + do_modeline_begrun_i <= '0'; + do_tdc_begrun_i <= '0'; + do_modeline_calib_trigger_i <= '0'; + do_tdc_calib_trigger_i <= '0'; + reg_calibration_step_tdc_setup <= (others => '0'); + reg_calibration_step_mode_line <= (others => '0'); + output_enable_i <= '0'; + else + current_state <= next_state; + do_modeline_begrun_i <= next_do_modeline_begrun_i; + do_tdc_begrun_i <= next_do_tdc_begrun_i; + do_modeline_calib_trigger_i <= next_do_modeline_calib_trigger_i; + do_tdc_calib_trigger_i <= next_do_tdc_calib_trigger_i; + reg_calibration_step_tdc_setup <= next_calibration_step_tdc_setup; + reg_calibration_step_mode_line <= next_calibration_step_mode_line; + output_enable_i <= next_output_enable; + end if; + end if; + end process; + +--purpose: state machine + proc_fsm_comb : process (DO_BEGRUN_IN, DO_CALIB_TRIGGER_IN, current_state, + tdc_setting_loaded_i, + finished_load_calib_i, state_load_tdc_setup_i, finished_begrun_i, + state_load_mode_line_i, start_load_tdc_settings_i) + begin + next_state <= current_state; + next_do_modeline_begrun_i <= '0'; + next_do_tdc_begrun_i <= '0'; + + next_do_modeline_calib_trigger_i <= '0'; + next_do_tdc_calib_trigger_i <= '0'; + next_calibration_step_tdc_setup <= x"0"; + next_calibration_step_mode_line <= x"0"; + next_output_enable <= '0'; + + case current_state is + + when idle_state => + if DO_BEGRUN_IN = '1' then + next_output_enable <= '1'; + next_state <= load_data_mode_state; + next_do_modeline_begrun_i <= '1'; + elsif DO_CALIB_TRIGGER_IN = '1' then + next_output_enable <= '1'; + next_do_modeline_calib_trigger_i <= '1'; + next_state <= calibration_state_0; + end if; +------------------------------------------------------------------------------- +-- Begrun Trigger +------------------------------------------------------------------------------- + when load_data_mode_state => + next_output_enable <= '0'; + if start_load_tdc_settings_i = '1' then + next_state <= load_tdc_data_state; + next_do_tdc_begrun_i <= '1'; + end if; + + when load_tdc_data_state => + next_do_tdc_begrun_i <= '1'; + next_output_enable <= '1'; + if tdc_setting_loaded_i = '1' then + next_state <= read_back_tdc_state; + end if; + + when read_back_tdc_state => + if finished_begrun_i = '1' then + next_state <= idle_state; + end if; +------------------------------------------------------------------------------- +-- Calibration Trigger +------------------------------------------------------------------------------- + when calibration_state_0 => --hex 48 + next_do_modeline_calib_trigger_i <= '1'; + next_output_enable <= '1'; + next_state <= dummy_calibration_state_0; + + when dummy_calibration_state_0 => + next_output_enable <= '1'; + if state_load_mode_line_i = x"10" then + next_state <= calibration_state_1; + end if; + + when calibration_state_1 => --GDE registers + next_output_enable <= '1'; + next_do_tdc_calib_trigger_i <= '1'; + next_state <= dummy_calibration_state_1; + + when dummy_calibration_state_1 => + next_output_enable <= '1'; + if state_load_tdc_setup_i = x"12" then + next_state <= calibration_state_2; + end if; + + when calibration_state_2 => --hex 08 + next_output_enable <= '1'; + next_calibration_step_mode_line <= x"1"; + if state_load_mode_line_i = x"12" then + next_state <= calibration_state_3; + end if; + + when calibration_state_3 => --register 1 "BD" + next_output_enable <= '1'; + next_calibration_step_tdc_setup <= x"1"; + if state_load_tdc_setup_i = x"1D" then + next_state <= calibration_state_4; + end if; + + when calibration_state_4 => --hex 08 and hex 48 + next_output_enable <= '1'; + next_calibration_step_mode_line <= x"2"; + if state_load_mode_line_i = x"16" then + next_state <= calibration_state_5; + end if; + + when calibration_state_5 => --register 1 "99" + GDE + next_output_enable <= '1'; + next_calibration_step_tdc_setup <= x"3"; + if state_load_tdc_setup_i = x"0B" then --calibration terminated + next_state <= calibration_state_6; + end if; + + when calibration_state_6 => --hex 7C + next_output_enable <= '1'; + next_calibration_step_mode_line <= x"3"; + if finished_load_calib_i = '1' then + next_state <= idle_state; + end if; + + when others => + next_state <= idle_state; + + end case; + end process; + +------------------------------------------------------------------------------- +-- Debugging +------------------------------------------------------------------------------- + + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case next_state is + when idle_state => state_bits <= x"0"; + when load_data_mode_state => state_bits <= x"1"; + when load_tdc_data_state => state_bits <= x"2"; + when calibration_state_0 => state_bits <= x"3"; + when dummy_calibration_state_0 => state_bits <= x"4"; + when calibration_state_1 => state_bits <= x"5"; + when dummy_calibration_state_1 => state_bits <= x"6"; + when calibration_state_2 => state_bits <= x"7"; + when calibration_state_3 => state_bits <= x"8"; + when calibration_state_4 => state_bits <= x"9"; + when calibration_state_5 => state_bits <= x"A"; + when calibration_state_6 => state_bits <= x"B"; + when read_back_tdc_state => state_bits <= x"E"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + +DEBUG_REGISTER(31 downto 20) <= (others => '0'); +DEBUG_REGISTER(19 downto 16) <= state_bits; +DEBUG_REGISTER(15) <= start_debug_readout_i; +DEBUG_REGISTER(14) <= tdc_setting_loaded_i; +DEBUG_REGISTER(13) <= finished_begrun_i; +DEBUG_REGISTER(12) <= finished_load_calib_i; +DEBUG_REGISTER(11) <= do_tdc_begrun_i; +DEBUG_REGISTER(10) <= do_modeline_begrun_i; +DEBUG_REGISTER(9) <= do_tdc_calib_trigger_i; +DEBUG_REGISTER(8) <= do_modeline_calib_trigger_i; +DEBUG_REGISTER(7 downto 4) <= next_calibration_step_tdc_setup; +DEBUG_REGISTER(3 downto 0) <= next_calibration_step_mode_line; + +end Behavioral; diff --git a/design2/trigger_handler.vhd b/design2/trigger_handler.vhd new file mode 100644 index 0000000..66fcf05 --- /dev/null +++ b/design2/trigger_handler.vhd @@ -0,0 +1,198 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity trigger_handler is + port( + CLK : in std_logic; + RESET : in std_logic; + + TRG_BEGRUN_IN : in std_logic; + --LVL1 trigger + LVL1_TRG_DATA_VALID_IN : in std_logic; --trigger type, number, code, information are valid + LVL1_VALID_TIMING_TRG_IN : in std_logic; --valid timing trigger has been received + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; --valid trigger within timing trigger has been received + LVL1_INVALID_TRG_IN : in std_logic; --the current trigger is invalid (e.g. no timing trigger, no LVL1...) + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + + LVL1_RELEASE_OUT : out std_logic; + LVL1_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + + DO_BEGIN_RUN_IN : in std_logic; + + --FSM control + START_TRIGGER_OUT : out std_logic; --start normal trigger + START_CALIB_OUT : out std_logic; --start calibration trigger + START_BEGRUN_OUT : out std_logic; --start begrun trigger + START_READOUT_OUT : out std_logic; --begin tdc readout aka send token and read data + FINISHED_READOUT_OUT : out std_logic; --All entities back to idle + + --FSM status + FINISHED_BEGRUN_IN : in std_logic; --loading settings finished + CAL1_LOADED_IN : in std_logic; --calibration settings have been loaded + TOKEN_MISSING_IN : in std_logic; --token timeout - not received back + TOKEN_BACK_IN : in std_logic; --token back, readout finished + + --debug + DEBUG_REGISTER : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture trigger_handle_trg_arch of trigger_handler is + constant WAIT_AFTER_BEGRUN : unsigned(11 downto 0) := x"7D0"; + + type state_type is (IDLE, BEGRUN, TIMING_TRIGGER, CALIB_TRIGGER, DO_READOUT, RELEASE_LVL1); + signal current_state : state_type; + + signal start_trigger_i : std_logic; + signal start_readout_i : std_logic; + signal start_calib_i : std_logic; + signal start_begrun_i : std_logic; + signal finished_readout_i : std_logic; + signal lvl1_release_i : std_logic; + + signal timer : unsigned(11 downto 0); + signal timer_clear : std_logic; + + signal state_bits : std_logic_vector(3 downto 0); + + +begin + + + THE_FSM : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + current_state <= IDLE; + start_trigger_i <= '0'; + start_readout_i <= '0'; + start_calib_i <= '0'; + start_begrun_i <= '0'; + finished_readout_i <= '0'; + lvl1_release_i <= '0'; + else + start_trigger_i <= '0'; + start_readout_i <= '0'; + start_calib_i <= '0'; + start_begrun_i <= '0'; + finished_readout_i <= '0'; + lvl1_release_i <= '0'; + timer_clear <= '0'; + + case current_state is + when IDLE => + if DO_BEGIN_RUN_IN = '1' then + current_state <= BEGRUN; + start_begrun_i <= '1'; + elsif LVL1_VALID_TIMING_TRG_IN = '1' then + current_state <= TIMING_TRIGGER; + timer_clear <= '1'; + start_trigger_i <= '1'; + elsif LVL1_VALID_NOTIMING_TRG_IN = '1' then -- and LVL1_TRG_TYPE_IN = x"9" + current_state <= CALIB_TRIGGER; + start_calib_i <= '1'; + end if; + + when BEGRUN => + if FINISHED_BEGRUN_IN = '1' then + current_state <= IDLE; + finished_readout_i <= '1'; + end if; + + when TIMING_TRIGGER => + if timer = x"3F" then + current_state <= DO_READOUT; + start_readout_i <= '1'; + end if; + + when CALIB_TRIGGER => + if CAL1_LOADED_IN = '1' then + current_state <= DO_READOUT; + start_readout_i <= '1'; + end if; + + when DO_READOUT => + if TOKEN_BACK_IN = '1' then + finished_readout_i <= '1'; + current_state <= RELEASE_LVL1; + elsif TOKEN_MISSING_IN = '1' then + finished_readout_i <= '1'; + current_state <= RELEASE_LVL1; + end if; + + when RELEASE_LVL1 => + lvl1_release_i <= '1'; + if LVL1_TRG_DATA_VALID_IN = '0' then + current_state <= IDLE; + end if; + + when others => + current_state <= IDLE; + + end case; + end if; + end if; + end process; + +------------------------------------------------------------------------------- +-- Timer +------------------------------------------------------------------------------- + proc_timer : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' or timer_clear = '1' then + timer <= (others => '0'); + else + timer <= timer + to_unsigned(1,1); + end if; + end if; + end process; + + + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + START_TRIGGER_OUT <= start_trigger_i; + START_CALIB_OUT <= start_calib_i; + START_BEGRUN_OUT <= start_begrun_i; + START_READOUT_OUT <= start_readout_i; + FINISHED_READOUT_OUT <= finished_readout_i; + + LVL1_RELEASE_OUT <= lvl1_release_i; + LVL1_STATUSBITS_OUT <= (others => '0'); + + +------------------------------------------------------------------------------- +-- Debugging +------------------------------------------------------------------------------- + proc_state_bits : process(CLK) + begin + if rising_edge(CLK) then + case current_state is + when IDLE => state_bits <= x"0"; + when BEGRUN => state_bits <= x"1"; + when TIMING_TRIGGER => state_bits <= x"2"; + when CALIB_TRIGGER => state_bits <= x"3"; + when DO_READOUT => state_bits <= x"4"; + when others => state_bits <= x"F"; + end case; + end if; + end process; + + DEBUG_REGISTER(3 downto 0) <= state_bits; + DEBUG_REGISTER(31 downto 4) <= (others => '0'); + +end architecture; diff --git a/mdc_oepb.prj b/mdc_oepb.prj index bd424b0..7dbdff8 100644 --- a/mdc_oepb.prj +++ b/mdc_oepb.prj @@ -47,42 +47,50 @@ add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualpo add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_fot.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_fot/serdes_fot_0.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../trbnet/optical_link/f_divider.vhd" + +add_file -vhdl -lib work "design2/control_line_handle.vhd" +add_file -vhdl -lib work "design2/data_handler.vhd" +add_file -vhdl -lib work "design2/initialization_RAM.vhd" +add_file -vhdl -lib work "design2/load_mode_line.vhd" +add_file -vhdl -lib work "design2/load_tdc_setup.vhd" +add_file -vhdl -lib work "design2/mdc_control.vhd" +add_file -vhdl -lib work "design2/send_token_to_mb.vhd" +add_file -vhdl -lib work "design2/tdc_readout.vhd" +add_file -vhdl -lib work "design2/trigger_begrun_state.vhd" +add_file -vhdl -lib work "design2/trigger_handler.vhd" + -add_file -vhdl -lib work "design/common_stop_generator.vhd" -add_file -vhdl -lib work "design/counter_12bit.vhd" -add_file -vhdl -lib work "design/counter_4bit.vhd" -add_file -vhdl -lib work "design/counter_8bit.vhd" -add_file -vhdl -lib work "design/edge_to_pulse.vhd" -#add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh.vhd" -#add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width.vhd" -add_file -vhdl -lib work "design/fifo_8192depth_36width_dual_thresh_reg_out.vhd" -#add_file -vhdl -lib work "design/fifo_fall_through_512depth_52width_reg_out.vhd" -add_file -vhdl -lib work "design/fifo_512depth_72width_reg_out.vhd" -add_file -vhdl -lib work "design/initialization_RAM.vhd" -add_file -vhdl -lib work "design/load_mode_line.vhd" -add_file -vhdl -lib work "design/load_ROC1_tdc_setup.vhd" -add_file -vhdl -lib work "design/mdc_addon_daq_bus_0.vhd" -add_file -vhdl -lib work "design/mode_line_multiplexer.vhd" -add_file -vhdl -lib work "design/pulse_to_constant.vhd" -add_file -vhdl -lib work "design/send_token_to_mb.vhd" -add_file -vhdl -lib work "design/tdc_readout_and_trb_interface.vhd" -add_file -vhdl -lib work "design/tdc_readout.vhd" -add_file -vhdl -lib work "design/trigger_begrun_state.vhd" -add_file -vhdl -lib work "design/trigger_distributor.vhd" -add_file -vhdl -lib work "design/trigger_handle_tld.vhd" add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "design/mdc_oepb_pack.vhd" +add_file -vhdl -lib work "design2/mdc_oepb_pack.vhd" add_file -vhdl -lib work "mdc_oepb.vhd" -#test -#add_file -vhdl -lib work "design/oddParityGen.vhd" #implementation: "workdir" impl -add workdir -type fpga diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 2791ff6..586848d 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -21,14 +21,13 @@ use work.version.all; -- 0x20 Bit 0 -> reset internal logic -- 0x20 Bit 15 -> reboot fpga -- 0x20 Bit 16 -> pseudo timing trigger --- 0x20 Bit 24 -> begin run trigger +-- 0x20 Bit 22 -> begin run trigger +-- 0x22 Bit 20 -> select data format (0: compressed, 1: debug) +-- 0x22 Bit 21 -> select dummy data (0: normal data, 1: dummy data) +-- 0x22 Bit 30 -> select debug output (0: off, 1: on) -- -- 0xc0 0x0010 -> select short -- 0xc0 0x0020 -> select long --- 0xc1 0x0C10 -> x"C" set calibration trigger, x"0" normal --- 0xc1 0x0000 -> select verbose mode data --- 0xc1 0x1000 -> select compact mode data --- 0xc1 0x2000 -> select test data -- 0xc1 0x0ABC0000 -> x"ABC" number of test data words -- 0xc1 0x10000000 -> x"1" external cms -- 0xc1 0x00000000 -> x"0" internal generated cms @@ -37,253 +36,232 @@ use work.version.all; entity mdc_oepb is generic( - INCLUDE_READOUT : integer range 0 to 1 := c_YES + REGIO_NUM_STAT_REGS : integer := 4; + REGIO_NUM_CTRL_REGS : integer := 1 ); port( --Clocks - CLK : in std_logic; - --Reset + CLK : in std_logic; --Optical link - TXP : out std_logic; - TXN : out std_logic; - RXP : in std_logic; - RXN : in std_logic; - SD : in std_logic; + TXP : out std_logic; + TXN : out std_logic; + RXP : in std_logic; + RXN : in std_logic; + SD : in std_logic; --LED - D : out std_logic_vector(4 downto 1); - ONEWIRE : inout std_logic; + D : out std_logic_vector(4 downto 1); + ONEWIRE : inout std_logic; --Flash FF, Watchdog - WATCHDOG : out std_logic; - CLK_FF : out std_logic; - DATA_FF : out std_logic; - MRES : out std_logic; - CS : in std_logic_vector(2 downto 1); + WATCHDOG : out std_logic; + CLK_FF : out std_logic; + DATA_FF : out std_logic; + MRES : out std_logic; + CS : in std_logic_vector(2 downto 1); --ADC - ADC_SCK : out std_logic; - ADC_SDI : out std_logic; - ADC_SDO : in std_logic; - ADC_CONVST : out std_logic; + ADC_SCK : out std_logic; + ADC_SDI : out std_logic; + ADC_SDO : in std_logic; + ADC_CONVST : out std_logic; --SPI - SPI_CLK : out std_logic; - SPI_CS : out std_logic; - SPI_DIN : in std_logic; - SPI_DOUT : out std_logic; - --MB - TAOD : inout std_logic; --address or data - TACK : in std_logic; --MB address - CMS : out std_logic; --common stop - COM_STOP_P : in std_logic; --common stop input from transceiver - TDST : inout std_logic; --data strobe - GDE : out std_logic; --global disable - RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM) - TRDYO : in std_logic; --ready FROM first motherboard token in (respect OEP old RDO) - TRSV : in std_logic; --this is 11 bit of dataword (on AddOn A_RESERV) + SPI_CLK : out std_logic; + SPI_CS : out std_logic; + SPI_DIN : in std_logic; + SPI_DOUT : out std_logic; + --MBO + TAOD : inout std_logic; --address or data + TAD : inout std_logic_vector(8 downto 0); --data/address + TDST : inout std_logic; --data strobe + TACK : in std_logic; --acknowledge + CMS : out std_logic; --common stop to MBO + COM_STOP_P : in std_logic; --common stop input + GDE : out std_logic; --global disable + RDYI : out std_logic; --token out to MB + TRDYO : in std_logic; --token in from MB + TRSV : in std_logic; --this is 11 bit of dataword (on AddOn A_RESERV) --mode lines - MODD : out std_logic; -- TDC working mode - RES : out std_logic; -- TDC working mode - TOK : out std_logic; -- TDC working mode - WRM : out std_logic; -- TDC working mode - TAD : inout std_logic_vector(8 downto 0); --TAD 8 downto 0 - J2_P : out std_logic + MODD : out std_logic; -- TDC working mode + RES : out std_logic; -- TDC working mode + TOK : out std_logic; -- TDC working mode + WRM : out std_logic; -- TDC working mode + J2_P : out std_logic -- Fake timing trigger output ); end entity; architecture mdc_oepb_arch of mdc_oepb is - signal CLK_100 : std_logic; - signal pll_locked : std_logic; - signal reset_startup : std_logic; - signal reset_internal : std_logic; - signal reset_counter : unsigned(23 downto 0) := x"000000"; - - - signal MED_DATA_IN, MED_DATA_OUT : std_logic_vector(16-1 downto 0); - signal MED_PACKET_NUM_IN, MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal MED_DATAREADY_IN, MED_DATAREADY_OUT : std_logic; - signal MED_READ_IN, MED_READ_OUT : std_logic; - signal MED_STAT_OP : std_logic_vector(16-1 downto 0); - signal MED_CTRL_OP : std_logic_vector(16-1 downto 0); - signal MED_STAT_DEBUG : std_logic_vector(63 downto 0); - - signal LVL1_TRG_TYPE_OUT : std_logic_vector(3 downto 0); - signal LVL1_TRG_RECEIVED_OUT : std_logic; - signal LVL1_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); - signal LVL1_TRG_CODE_OUT : std_logic_vector(7 downto 0); - signal LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0); - signal LVL1_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); - signal LVL1_TRG_RELEASE_IN : std_logic; - signal LVL1_INT_TRG_NUMBER_OUT : std_logic_vector(15 downto 0); - - signal IPU_NUMBER_OUT : std_logic_vector(15 downto 0); - signal IPU_INFORMATION_OUT : std_logic_vector(7 downto 0); - signal IPU_START_READOUT_OUT : std_logic; - signal IPU_DATA_IN : std_logic_vector(31 downto 0); - signal IPU_DATAREADY_IN : std_logic; - signal IPU_READOUT_FINISHED_IN : std_logic; - signal IPU_READ_OUT : std_logic; - signal IPU_LENGTH_IN : std_logic_vector(15 downto 0); - signal IPU_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); - - signal REGIO_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal REGIO_REGISTERS_IN : std_logic_vector(32*2**(4)-1 downto 0); - signal REGIO_REGISTERS_OUT : std_logic_vector(32*2**(3)-1 downto 0); - signal REGIO_ADDR_OUT : std_logic_vector(15 downto 0); - signal REGIO_READ_ENABLE_OUT : std_logic; - signal REGIO_WRITE_ENABLE_OUT : std_logic; - signal REGIO_DATA_OUT : std_logic_vector(31 downto 0); - signal REGIO_DATA_IN : std_logic_vector(31 downto 0); - signal REGIO_DATAREADY_IN : std_logic; - signal REGIO_NO_MORE_DATA_IN : std_logic; - signal REGIO_WRITE_ACK_IN : std_logic; - signal REGIO_UNKNOWN_ADDR_IN : std_logic; - signal REGIO_TIMEOUT_OUT : std_logic; - signal REGIO_IDRAM_DATA_IN : std_logic_vector(15 downto 0); - signal REGIO_IDRAM_DATA_OUT : std_logic_vector(15 downto 0); - signal REGIO_IDRAM_ADDR_IN : std_logic_vector(2 downto 0); - signal REGIO_IDRAM_WR_IN : std_logic; - - signal adc_addr : std_logic_vector(5 downto 0); - signal adc_read : std_logic; - signal adc_write : std_logic; - signal adc_data_out : std_logic_vector(31 downto 0); - signal adc_data_in : std_logic_vector(31 downto 0); - signal adc_dataready : std_logic; - signal adc_no_more_data : std_logic; - signal adc_write_ack : std_logic; - signal adc_unknown_addr : std_logic; - signal adc_timeout : std_logic; - signal adc_stat : std_logic_vector(31 downto 0); - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal global_time : std_logic_vector(31 downto 0); - signal local_time : std_logic_vector(7 downto 0); - signal time_since_last_trg : std_logic_vector(31 downto 0); - signal timer_microsecond_tick : std_logic; --- signal trigger_monitor : std_logic; - - signal reg_REGIO_ADDR : std_logic_vector(15 downto 0); - signal reg_REGIO_READ : std_logic; - signal last_reg_REGIO_READ : std_logic; - signal very_last_reg_REGIO_READ : std_logic; - signal reg_REGIO_WRITE : std_logic; - - signal thresh_mem_data : std_logic_vector(15 downto 0); - signal thresh_mem_data_out : std_logic_vector(15 downto 0); - signal thresh_mem_write: std_logic; - signal thresh_mem_read : std_logic; - signal thresh_mem_addr : std_logic_vector(8 downto 0); - - signal token_to_mux_out_i : std_logic; - signal init_all_buses_i : std_logic_vector(3 downto 0); - signal roc1_written_i : std_logic; - signal a_add_configuration_i : std_logic_vector(8 downto 0); - signal a_add_data_i : std_logic_vector(8 downto 0); - signal a_dst_configuration_i : std_logic; - signal a_aod_configuration_i : std_logic; - signal a_dst_data_i : std_logic; - signal a_aod_data_i : std_logic; - signal debug_trigger_distributor_i : std_logic_vector(31 downto 0); - signal pulse_pseudo_timing_trigger : std_logic; - signal cal_trigger_register_in_i : std_logic_vector(15 downto 0); - signal direction_data_line_out_i : std_logic_vector(3 downto 0); - signal motherboard_type_in_i : std_logic_vector(3 downto 0); - signal pulse_begin_run_trigger_i : std_logic; - signal timing_trigger_received : std_logic; - signal timing_trigger_in : std_logic; - signal pulse_timing_trigger : std_logic; - - signal data_type_select_in_i : std_logic_vector(15 downto 0); - - signal test_debug_i : std_logic_vector(7 downto 0); --- signal counter_led : unsigned(31 downto 0); --- signal test_pseudo_signal_i : std_logic; - - signal delayed_restart_fpga : std_logic; - signal restart_fpga_counter : unsigned(11 downto 0); - - signal flash_rom_read : std_logic; - signal flash_rom_write : std_logic; - signal next_flash_rom_select : std_logic; - signal flash_rom_select : std_logic; - signal flash_rom_clk : std_logic; - signal next_flash_rom_clk : std_logic; - - signal reg_CS : std_logic_vector(2 downto 1); - signal real_flash_rom_select : std_logic_vector(1 downto 0); - - signal COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0); - --- signal flash_mem_data : std_logic_vector(31 downto 0); --- signal flash_mem_data_out : std_logic_vector(31 downto 0); --- signal flash_mem_write: std_logic; --- signal flash_mem_read : std_logic; --- signal flash_mem_addr : std_logic_vector(8 downto 0); - --- signal cmd_register_in : std_logic_vector(31 downto 0); --- signal ctrl_register : std_logic_vector(31 downto 0); --- signal write_cmd_register_in : std_logic; --- signal write_ctrl_register : std_logic; - - signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic; - - type dummy_state_t is (IDLE, SEND_DHDR, WAIT_FOR_FINISHED); - signal dummy_state : dummy_state_t; - - signal cms_select_in_i: std_logic_vector (3 downto 0); - signal a_cms_i : std_logic; - - signal cms_counter : unsigned(3 downto 0); - signal cms_output : std_logic; - --- signal input_parity_gen : std_logic_vector(9 downto 0); - --- type tt is array (3000 downto 0) of std_logic_vector(3 downto 0); --- signal data_in, data_out : tt; - --- --signal counter_data : unsigned(35 downto 0); --- signal counter_data : std_logic_vector(35 downto 0); --- signal out_shift_reg : tt; --- signal out_shift_reg1 : std_logic_vector(3 downto 0); --- signal temp_led0, temp_led1, temp_led2, temp_led3 : std_logic; - - - + --Clock and Reset + signal clk_100 : std_logic; + signal pll_locked : std_logic; + signal reset_startup : std_logic; + signal reset_internal : std_logic; + signal reset_sync : std_logic; + signal reset_async : std_logic; + signal reset_counter : unsigned(23 downto 0); + + --Media Interface to internal logic + signal med_data_in : std_logic_vector(16-1 downto 0); + signal med_data_out : std_logic_vector(16-1 downto 0); + signal med_packet_num_in : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal med_dataready_in : std_logic; + signal med_dataready_out : std_logic; + signal med_read_in : std_logic; + signal med_read_out : std_logic; + signal med_stat_op : std_logic_vector(16-1 downto 0); + signal med_ctrl_op : std_logic_vector(16-1 downto 0); + signal med_stat_debug : std_logic_vector(63 downto 0); + + --LVL1 channel + signal timing_trg_received_i : std_logic; + signal trg_data_valid_i : std_logic; + signal trg_timing_valid_i : std_logic; + signal trg_notiming_valid_i : std_logic; + signal trg_invalid_i : std_logic; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_code_i : std_logic_vector(7 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + + --Data channel + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + signal fee_data_i : std_logic_vector(31 downto 0); + signal fee_data_write_i : std_logic; + signal fee_data_finished_i : std_logic; + signal fee_almost_full_i : std_logic; + + --Slow Control channel + signal reg_common_stat_reg_in : std_logic_vector(std_COMSTATREG*32-1 downto 0); + signal reg_common_ctrl_reg_out : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + signal reg_registers_in : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); + signal reg_registers_out : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); + signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); + signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); + signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal reg_addr_out : std_logic_vector(15 downto 0); + signal reg_read_enable_out : std_logic; + signal reg_write_enable_out : std_logic; + signal reg_data_out : std_logic_vector(31 downto 0); + signal reg_data_in : std_logic_vector(31 downto 0); + signal reg_dataready_in : std_logic; + signal reg_no_more_data_in : std_logic; + signal reg_write_ack_in : std_logic; + signal reg_unknown_addr_in : std_logic; + signal reg_timeout_out : std_logic; + + + --ADC I/O + signal adc_addr : std_logic_vector(5 downto 0); + signal adc_read : std_logic; + signal adc_write : std_logic; + signal adc_data_out : std_logic_vector(31 downto 0); + signal adc_data_in : std_logic_vector(31 downto 0); + signal adc_dataready : std_logic; + signal adc_no_more_data : std_logic; + signal adc_write_ack : std_logic; + signal adc_unknown_addr : std_logic; + signal adc_timeout : std_logic; + signal adc_stat : std_logic_vector(31 downto 0); + + --SPI + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + --Flash control + signal delayed_restart_fpga : std_logic; + signal restart_fpga_counter : unsigned(11 downto 0); + signal flash_rom_read : std_logic; + signal flash_rom_write : std_logic; + signal next_flash_rom_select : std_logic; + signal flash_rom_select : std_logic; + signal flash_rom_clk : std_logic; + signal next_flash_rom_clk : std_logic; + signal reg_CS : std_logic_vector(2 downto 1); + signal real_flash_rom_select : std_logic_vector(1 downto 0); + + --Timer + signal global_time : std_logic_vector(31 downto 0); + signal local_time : std_logic_vector(7 downto 0); + signal time_since_last_trg : std_logic_vector(31 downto 0); + signal timer_ticks : std_logic_vector(1 downto 0); + + --Config Memory Signals + signal thresh_mem_data : std_logic_vector(15 downto 0); + signal thresh_mem_data_out : std_logic_vector(15 downto 0); + signal thresh_mem_write : std_logic; + signal thresh_mem_read : std_logic; + signal thresh_mem_ready : std_logic; + signal thresh_mem_addr : std_logic_vector(8 downto 0); + + --Read back data from TDC + signal readback_mem_read : std_logic; + signal readback_mem_write : std_logic; + signal readback_mem_empty : std_logic; + signal readback_mem_ready : std_logic; + signal readback_mem_data_out : std_logic_vector(31 downto 0); + + --Status Registers + signal statreg_read : std_logic; + signal statreg_write : std_logic; + signal statreg_ready : std_logic; + signal statreg_addr : std_logic_vector(3 downto 0); + signal statreg_data : std_logic_vector(31 downto 0); + + signal debug_mdc_control_i : std_logic_vector(31 downto 0); begin - --------------------------------------------------------------------- -- PLL: 100 MHz --------------------------------------------------------------------- PLL100 : pll_in25_out100 port map( CLK => CLK, - CLKOP => CLK_100, + CLKOP => clk_100, LOCK => pll_locked ); --- reset <= c_reset or not pll25_lock; --------------------------------------------------------------------- --- Reset process +-- Reset handler --------------------------------------------------------------------- + +-- THE_RESET_HANDLER : trb_net_reset_handler +-- generic map( +-- RESET_DELAY => x"0EEE" +-- ) +-- port map( +-- CLEAR_IN => '0', -- reset input (high active, async) +-- CLEAR_N_IN => '1', -- reset input (low active, async) +-- CLK_IN => CLK, -- raw master clock, NOT from PLL/DLL! +-- SYSCLK_IN => clk_100, -- PLL/DLL remastered clock +-- PLL_LOCKED_IN => pll_locked, -- master PLL lock signal (async) +-- RESET_IN => MED_STAT_OP(13),-- general reset signal (SYSCLK) +-- TRB_RESET_IN => MED_STAT_OP(14),-- TRBnet reset signal (SYSCLK) +-- CLEAR_OUT => reset_async, -- async reset out, USE WITH CARE! +-- RESET_OUT => reset_sync, -- synchronous reset out (SYSCLK) +-- DEBUG_OUT => open +-- ); +-- +-- reset_startup <= reset_async; +-- reset_internal <= reset_sync; + THE_RESET_COUNTER_PROC: process(CLK) begin if rising_edge(CLK) then @@ -305,224 +283,169 @@ begin end if; end if; end process; - - --------------------------------------------------------------------- --- Restart FPGA +-- Unused signals --------------------------------------------------------------------- - - --force watchdog to restart fpga - MRES <= not delayed_restart_fpga; - - --delay restart command to finish trbnet transfer - process (CLK_100) - begin - if rising_edge(CLK_100) then - delayed_restart_fpga <= '0'; - if reset_internal = '1' then - restart_fpga_counter <= x"FFF"; - elsif REGIO_COMMON_CTRL_REG_OUT(15) = '1' then - restart_fpga_counter <= x"000"; - elsif restart_fpga_counter /= x"FFF" then - restart_fpga_counter <= restart_fpga_counter + 1; - if restart_fpga_counter >= x"F00" then - delayed_restart_fpga <= '1'; - end if; - end if; - end if; - end process; - +reg_registers_in <= (others => '0'); --------------------------------------------------------------------- --- Select Flash FF +-- Optical Uplink --------------------------------------------------------------------- + THE_MED_INTERFACE : trb_net16_med_ecp_fot + port map( + CLK => clk_100, + CLK_25 => CLK, + CLK_EN => '1', + RESET => reset_startup, --reset_internal, + CLEAR => reset_startup, - PROC_CONTRL_FLASH_SELECT : process (CLK_100) - begin - if rising_edge(CLK_100) then - flash_rom_clk <= next_flash_rom_clk; - if flash_rom_write = '1' then - flash_rom_select <= next_flash_rom_select; - next_flash_rom_clk <= '1'; - else - next_flash_rom_clk <= '0'; - end if; - end if; - end process PROC_CONTRL_FLASH_SELECT; - - CLK_FF <= flash_rom_clk; - DATA_FF <= flash_rom_select; + --Internal Connection + MED_DATA_IN => MED_DATA_OUT, + MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT, + MED_DATAREADY_IN => MED_DATAREADY_OUT, + MED_READ_OUT => MED_READ_IN, + MED_DATA_OUT => MED_DATA_IN, + MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN, + MED_DATAREADY_OUT => MED_DATAREADY_IN, + MED_READ_IN => MED_READ_OUT, + --SFP Connection + TXP => TXP, + TXN => TXN, + RXP => RXP, + RXN => RXN, + SD => SD, - THE_CS_SYNC : signal_sync - generic map( - DEPTH => 2, - WIDTH => 2 - ) - port map( - RESET => reset_internal, - D_IN => CS, - CLK0 => CLK, - CLK1 => CLK, - D_OUT => reg_CS + -- Status and control port + STAT_OP => MED_STAT_OP, + CTRL_OP => MED_CTRL_OP, + STAT_DEBUG => MED_STAT_DEBUG, + CTRL_DEBUG => (others => '0') ); - real_flash_rom_select <= "00" when reg_CS = "10" else - "01" when reg_CS = "01" else - "10"; - --------------------------------------------------------------------- -- trbnet endpoint --------------------------------------------------------------------- - API: trb_net16_endpoint_hades_full + THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - REGIO_NUM_STAT_REGS => 4,--4, --16 stat reg - REGIO_NUM_CTRL_REGS => 3,--3, --8 cotrol reg - --standard values for output registers - REGIO_INIT_CTRL_REGS => (others => '0'), - --set to 0 for unused ctrl registers to save resources - REGIO_USED_CTRL_REGS => (others => '1'), - REGIO_USED_CTRL_BITMASK => (others => '1'), - ADDRESS_MASK => x"F37F", - BROADCAST_BITMASK => x"FD", - REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - CLOCK_FREQUENCY => 100 + REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,--4, --16 stat reg + REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,--3, --8 cotrol reg + ADDRESS_MASK => x"F37F", + BROADCAST_BITMASK => x"FD", + REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + REGIO_HARDWARE_VERSION => x"23000001", + CLOCK_FREQUENCY => 100, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => 13, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**13-1024, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 ) port map( - CLK => CLK_100, - RESET => reset_internal, - CLK_EN => '1', - MED_DATAREADY_OUT => MED_DATAREADY_OUT, - MED_DATA_OUT => MED_DATA_OUT, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, - MED_READ_IN => MED_READ_IN, - MED_DATAREADY_IN => MED_DATAREADY_IN, - MED_DATA_IN => MED_DATA_IN, - MED_PACKET_NUM_IN => MED_PACKET_NUM_IN, - MED_READ_OUT => MED_READ_OUT, - MED_STAT_OP_IN => MED_STAT_OP, - MED_CTRL_OP_OUT => MED_CTRL_OP, - - -- LVL1 trigger APL - LVL1_TRG_TYPE_OUT => LVL1_TRG_TYPE_OUT, - LVL1_TRG_RECEIVED_OUT => LVL1_TRG_RECEIVED_OUT, - LVL1_TRG_NUMBER_OUT => LVL1_TRG_NUMBER_OUT, - LVL1_TRG_CODE_OUT => LVL1_TRG_CODE_OUT, - LVL1_TRG_INFORMATION_OUT => LVL1_TRG_INFORMATION_OUT, - LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, - LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, - LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT, - - --Data Port - IPU_NUMBER_OUT => IPU_NUMBER_OUT, - IPU_INFORMATION_OUT => IPU_INFORMATION_OUT, - IPU_START_READOUT_OUT => IPU_START_READOUT_OUT, - IPU_DATA_IN => IPU_DATA_IN, - IPU_DATAREADY_IN => IPU_DATAREADY_IN, - IPU_READOUT_FINISHED_IN => IPU_READOUT_FINISHED_IN, - IPU_READ_OUT => IPU_READ_OUT, - IPU_LENGTH_IN => IPU_LENGTH_IN, - IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN, + CLK => clk_100, + RESET => reset_internal, + CLK_EN => '1', + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => med_ctrl_op, + + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i, + --LVL1 trigger to FEE + LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i, + LVL1_INVALID_TRG_OUT => trg_invalid_i, + + LVL1_TRG_TYPE_OUT => trg_type_i, + LVL1_TRG_NUMBER_OUT => trg_number_i, + LVL1_TRG_CODE_OUT => trg_code_i, + LVL1_TRG_INFORMATION_OUT => trg_information_i, + LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i, + + --Response from FEE + FEE_TRG_RELEASE_IN(0) => fee_trg_release_i, + FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i, + FEE_DATA_IN => fee_data_i, + FEE_DATA_WRITE_IN(0) => fee_data_write_i, + FEE_DATA_FINISHED_IN(0) => fee_data_finished_i, + FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i, -- Slow Control Data Port - REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN, --0x00 - REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, --0x20 - REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, --start 0x80 - REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, --start 0xc0 - - COMMON_CTRL_REG_STROBE => COMMON_CTRL_REG_STROBE, - - --following ports only used when using internal data port - REGIO_ADDR_OUT => REGIO_ADDR_OUT, - REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, - REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, - REGIO_DATA_OUT => REGIO_DATA_OUT, - REGIO_DATA_IN => REGIO_DATA_IN, - REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, - REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, - REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, - REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, - REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, - --IDRAM is used if no 1-wire interface, onewire used otherwise - REGIO_IDRAM_DATA_IN => REGIO_IDRAM_DATA_IN, - REGIO_IDRAM_DATA_OUT => REGIO_IDRAM_DATA_OUT, - REGIO_IDRAM_ADDR_IN => REGIO_IDRAM_ADDR_IN, - REGIO_IDRAM_WR_IN => REGIO_IDRAM_WR_IN, - REGIO_ONEWIRE_INOUT => ONEWIRE, - REGIO_ONEWIRE_MONITOR_IN => '0', - REGIO_ONEWIRE_MONITOR_OUT => open, - - TRIGGER_MONITOR_IN => timing_trigger_received, - GLOBAL_TIME_OUT => global_time, - LOCAL_TIME_OUT => local_time, - TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, - TIMER_US_TICK_OUT => timer_microsecond_tick, - - STAT_DEBUG_IPU => open, - STAT_DEBUG_1 => open, - STAT_DEBUG_2 => open, - MED_STAT_OP => open, - CTRL_MPLEX => (others => '0'), - IOBUF_CTRL_GEN => (others => '0'), - STAT_ONEWIRE => open, - STAT_ADDR_DEBUG => open + REGIO_COMMON_STAT_REG_IN => reg_common_stat_reg_in, --0x00 + REGIO_COMMON_CTRL_REG_OUT => reg_common_ctrl_reg_out, --0x20 + REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe, + REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe, + REGIO_STAT_REG_IN => reg_registers_in, --start 0x80 + REGIO_CTRL_REG_OUT => reg_registers_out, --start 0xc0 + REGIO_STAT_STROBE_OUT => stat_reg_strobe, + REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe, + + BUS_ADDR_OUT => reg_addr_out, + BUS_READ_ENABLE_OUT => reg_read_enable_out, + BUS_WRITE_ENABLE_OUT => reg_write_enable_out, + BUS_DATA_OUT => reg_data_out, + BUS_DATA_IN => reg_data_in, + BUS_DATAREADY_IN => reg_dataready_in, + BUS_NO_MORE_DATA_IN => reg_no_more_data_in, + BUS_WRITE_ACK_IN => reg_write_ack_in, + BUS_UNKNOWN_ADDR_IN => reg_unknown_addr_in, + BUS_TIMEOUT_OUT => reg_timeout_out, + ONEWIRE_INOUT => ONEWIRE, + ONEWIRE_MONITOR_OUT => open, + + TIME_GLOBAL_OUT => global_time, + TIME_LOCAL_OUT => local_time, + TIME_SINCE_LAST_TRG_OUT => time_since_last_trg, + TIME_TICKS_OUT => timer_ticks, + + STAT_DEBUG_IPU => open, + STAT_DEBUG_1 => open, + STAT_DEBUG_2 => open, + STAT_DEBUG_DATA_HANDLER_OUT=> open, + STAT_DEBUG_IPU_HANDLER_OUT => open, + CTRL_MPLEX => (others => '0'), + IOBUF_CTRL_GEN => (others => '0'), + STAT_ONEWIRE => open, + STAT_ADDR_DEBUG => open ); - - --------------------------------------------------------------------- -- SlowControl Handler --------------------------------------------------------------------- - - REGIO_COMMON_STAT_REG_IN(REGIO_COMMON_STAT_REG_IN'left downto 0) <= (others => '0'); - ---These are your registers: - REGIO_REGISTERS_IN <= (others => '0'); - --REGIO_REGISTERS_OUT; - - REGIO_IDRAM_DATA_IN <= (others => '0'); - REGIO_IDRAM_ADDR_IN <= (others => '0'); - REGIO_IDRAM_WR_IN <= '0'; - - - - THE_REG_DAT_ADDR : process(CLK_100) - begin - if rising_edge(CLK_100) then - if (REGIO_READ_ENABLE_OUT = '1' or REGIO_WRITE_ENABLE_OUT = '1') then - reg_REGIO_ADDR <= REGIO_ADDR_OUT; - end if; - reg_REGIO_READ <= REGIO_READ_ENABLE_OUT; - reg_REGIO_WRITE <= REGIO_WRITE_ENABLE_OUT; - - last_reg_REGIO_READ <= reg_REGIO_READ; - very_last_reg_REGIO_READ <= last_reg_REGIO_READ; - end if; - end process; - - THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler + THE_REG_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 5, - PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", others => x"0000"), - PORT_ADDR_MASK => (0 => 8, 1 => 6, 2 => 1, 3 => 6, 4 => 0, others => 0) + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", 2 => x"d000", 3 => x"d100", 4 => x"d200", 5 => x"e000", 6 => x"9000", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 6, 2 => 1, 3 => 6, 4 => 0, 5 => 0, 6 => 4, others => 0) ) port map( - CLK => CLK_100, + CLK => clk_100, RESET => reset_internal, - --I/O to RegIO - DAT_ADDR_IN => REGIO_ADDR_OUT, - DAT_DATA_IN => REGIO_DATA_OUT, - DAT_DATA_OUT => REGIO_DATA_IN, - DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_OUT, - DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_OUT, - DAT_TIMEOUT_IN => REGIO_TIMEOUT_OUT, - DAT_DATAREADY_OUT => REGIO_DATAREADY_IN, - DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_IN, - DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_IN, - DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_IN, + --I/O to REG + DAT_ADDR_IN => reg_addr_out, + DAT_DATA_IN => reg_data_out, + DAT_DATA_OUT => reg_data_in, + DAT_READ_ENABLE_IN => reg_read_enable_out, + DAT_WRITE_ENABLE_IN => reg_write_enable_out, + DAT_TIMEOUT_IN => reg_timeout_out, + DAT_DATAREADY_OUT => reg_dataready_in, + DAT_WRITE_ACK_OUT => reg_write_ack_in, + DAT_NO_MORE_DATA_OUT => reg_no_more_data_in, + DAT_UNKNOWN_ADDR_OUT => reg_unknown_addr_in, --Bus Handler (Threshold memory) BUS_READ_ENABLE_OUT(0) => thresh_mem_read, BUS_WRITE_ENABLE_OUT(0) => thresh_mem_write, @@ -533,8 +456,8 @@ begin BUS_TIMEOUT_OUT(0) => open, BUS_DATA_IN(0*32+15 downto 0*32) => thresh_mem_data_out, BUS_DATA_IN(0*32+31 downto 0*32+16) => x"0000", - BUS_DATAREADY_IN(0) => very_last_reg_REGIO_READ, - BUS_WRITE_ACK_IN(0) => reg_REGIO_WRITE, + BUS_DATAREADY_IN(0) => thresh_mem_ready, + BUS_WRITE_ACK_IN(0) => thresh_mem_ready, BUS_NO_MORE_DATA_IN(0) => '0', BUS_UNKNOWN_ADDR_IN(0) => '0', --Bus Handler (ADC) @@ -586,19 +509,41 @@ begin BUS_WRITE_ACK_IN(4) => flash_rom_write, BUS_NO_MORE_DATA_IN(4) => '0', BUS_UNKNOWN_ADDR_IN(4) => '0', + --Debugging memory + BUS_READ_ENABLE_OUT(5) => readback_mem_read, + BUS_WRITE_ENABLE_OUT(5) => readback_mem_write, + BUS_DATA_OUT(5*32+31 downto 5*32) => open, + BUS_ADDR_OUT(5*16+15 downto 5*16) => open, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(5*32+31 downto 5*32) => readback_mem_data_out, + BUS_DATAREADY_IN(5) => readback_mem_ready, + BUS_WRITE_ACK_IN(5) => '0', + BUS_NO_MORE_DATA_IN(5) => readback_mem_empty, + BUS_UNKNOWN_ADDR_IN(5) => readback_mem_write, + --Status Registers + BUS_READ_ENABLE_OUT(6) => statreg_read, + BUS_WRITE_ENABLE_OUT(6) => statreg_write, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+3 downto 6*16) => statreg_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+4) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => statreg_data, + BUS_DATAREADY_IN(6) => statreg_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => statreg_write, --Debugging - STAT_DEBUG => open + STAT_DEBUG => open ); - ------------------------------------------------------------------------------- -- SPI ------------------------------------------------------------------------------- THE_SPI_MASTER: spi_master port map( - CLK_IN => CLK_100, + CLK_IN => clk_100, RESET_IN => reset_internal, -- Slave bus BUS_READ_IN => spictrl_read_en, @@ -625,7 +570,7 @@ begin -- data memory for SPI accesses THE_SPI_MEMORY: spi_databus_memory port map( - CLK_IN => CLK_100, + CLK_IN => clk_100, RESET_IN => reset_internal, -- Slave bus BUS_ADDR_IN => spimem_addr, @@ -650,7 +595,7 @@ begin --------------------------------------------------------------------- THE_ADC : adc_ltc2308_readout port map( - CLK => CLK_100, + CLK => clk_100, RESET => reset_internal, CLK_EN => '1', @@ -675,473 +620,146 @@ begin --------------------------------------------------------------------- --- Optical Uplink +-- Restart FPGA --------------------------------------------------------------------- - THE_MED_INTERFACE : trb_net16_med_ecp_fot - port map( - CLK => CLK_100, - CLK_25 => CLK, - CLK_EN => '1', - RESET => reset_startup, --reset_internal, - --Internal Connection - MED_DATA_IN => MED_DATA_OUT, - MED_PACKET_NUM_IN => MED_PACKET_NUM_OUT, - MED_DATAREADY_IN => MED_DATAREADY_OUT, - MED_READ_OUT => MED_READ_IN, - MED_DATA_OUT => MED_DATA_IN, - MED_PACKET_NUM_OUT => MED_PACKET_NUM_IN, - MED_DATAREADY_OUT => MED_DATAREADY_IN, - MED_READ_IN => MED_READ_OUT, - --SFP Connection - TXP => TXP, - TXN => TXN, - RXP => RXP, - RXN => RXN, - SD => SD, + --force watchdog to restart fpga + MRES <= not delayed_restart_fpga; - -- Status and control port - STAT_OP => MED_STAT_OP, - CTRL_OP => MED_CTRL_OP, - STAT_DEBUG => MED_STAT_DEBUG, - CTRL_DEBUG => (others => '0') - ); + --delay restart command to finish trbnet transfer + process (clk_100) + begin + if rising_edge(clk_100) then + delayed_restart_fpga <= '0'; + if reset_internal = '1' then + restart_fpga_counter <= x"FFF"; + elsif REG_COMMON_CTRL_REG_OUT(15) = '1' then + restart_fpga_counter <= x"000"; + elsif restart_fpga_counter /= x"FFF" then + restart_fpga_counter <= restart_fpga_counter + 1; + if restart_fpga_counter >= x"F00" then + delayed_restart_fpga <= '1'; + end if; + end if; + end if; + end process; -------------------------------------------------------------------------------- --- dummy answers without trigger & readout logic -------------------------------------------------------------------------------- +--------------------------------------------------------------------- +-- Select Flash FF +--------------------------------------------------------------------- - GEN_NO_READOUT_LOGIC : if INCLUDE_READOUT = c_NO generate + PROC_CONTRL_FLASH_SELECT : process (clk_100) + begin + if rising_edge(clk_100) then + flash_rom_clk <= next_flash_rom_clk; + if flash_rom_write = '1' then + flash_rom_select <= next_flash_rom_select; + next_flash_rom_clk <= '1'; + else + next_flash_rom_clk <= '0'; + end if; + end if; + end process PROC_CONTRL_FLASH_SELECT; - -- LVL1 trigger APL - LVL1_ERROR_PATTERN_IN <= x"00400000"; - IPU_DATA_IN <= x"0000BEAF"; - IPU_LENGTH_IN <= x"0000"; - IPU_ERROR_PATTERN_IN <= x"00500000"; + CLK_FF <= flash_rom_clk; + DATA_FF <= flash_rom_select; - THE_TRG_RELEASE_DELAY : signal_sync + THE_CS_SYNC : signal_sync generic map( - DEPTH => 4, - WIDTH => 1 + DEPTH => 2, + WIDTH => 2 ) port map( RESET => reset_internal, - D_IN(0) => LVL1_TRG_RECEIVED_OUT, - CLK0 => CLK_100, - CLK1 => CLK_100, - D_OUT(0) => LVL1_TRG_RELEASE_IN + D_IN => CS, + CLK0 => CLK, + CLK1 => CLK, + D_OUT => reg_CS ); - - PROC_DUMMY_IPU : process(CLK_100) - begin - if rising_edge(CLK_100) then - IPU_READOUT_FINISHED_IN <= '0'; - IPU_DATAREADY_IN <= '0'; - case dummy_state is - when IDLE => - if IPU_START_READOUT_OUT = '1' then - dummy_state <= SEND_DHDR; - IPU_DATAREADY_IN <= '1'; - end if; - when SEND_DHDR => - IPU_DATAREADY_IN <= '1'; - if IPU_READ_OUT = '1' then - dummy_state <= WAIT_FOR_FINISHED; - IPU_DATAREADY_IN <= '0'; - end if; - when WAIT_FOR_FINISHED => - IPU_READOUT_FINISHED_IN <= '1'; - if IPU_START_READOUT_OUT = '0' then - dummy_state <= IDLE; - end if; - end case; - end if; - end process; - --- D(1) <= pulse_pseudo_timing_trigger; --- D(2) <= LVL1_TRG_RELEASE_IN; --- D(3) <= timing_trigger_received; --- D(4) <= COMMON_CTRL_REG_STROBE(1); - D <= not (LVL1_INT_TRG_NUMBER_OUT(1 downto 0) & LVL1_TRG_NUMBER_OUT(1 downto 0)); - end generate; - - -------------------------------------------------------------------------------- --- Select Internal or external common stop -------------------------------------------------------------------------------- - CMS <= COM_STOP_P when (cms_select_in_i = x"1") else a_cms_i; - timing_trigger_received <= pulse_timing_trigger when (cms_select_in_i = x"1") else pulse_pseudo_timing_trigger; - - pulse_pseudo_timing_trigger <= REGIO_COMMON_CTRL_REG_OUT(16); - pulse_reset_internal_logic <= REGIO_COMMON_CTRL_REG_OUT(0); - pulse_begin_run_trigger_i <= REGIO_COMMON_CTRL_REG_OUT(24); - - reset_mdc_addon_daq_bus_0 <= reset_internal or pulse_reset_internal_logic; - - PROC_REG_SETTINGS : process(CLK_100) - begin - if rising_edge(CLK_100) then - motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4); - cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(43 downto 40); - data_type_select_in_i <= REGIO_REGISTERS_OUT(59 downto 44); - cms_select_in_i <= REGIO_REGISTERS_OUT(63 downto 60); - end if; - end process; - - THE_CMS_SYNC : signal_sync - generic map( - DEPTH => 2, - WIDTH => 1 - ) - port map( - RESET => reset_internal, - D_IN(0) => COM_STOP_P, - CLK0 => CLK_100, - CLK1 => CLK_100, - D_OUT(0) => timing_trigger_in - ); - - PULSE_TIMING_TRIGGER : edge_to_pulse - port map ( - CLOCK => CLK_100, - ENABLE_CLK_IN => '1', - SIGNAL_IN => timing_trigger_in, - PULSE_OUT => pulse_timing_trigger - ); - - proc_gen_cms : process(CLK_100) - begin - if rising_edge(CLK_100) then - if reset_internal = '1' then - cms_counter <= x"0"; - cms_output <= '0'; - elsif cms_counter = x"0" then - if pulse_pseudo_timing_trigger = '1' then - cms_counter <= x"1"; - cms_output <= '1'; - end if; - elsif cms_counter = x"5" then - cms_output <= '0'; - cms_counter <= x"0"; - else - cms_counter <= cms_counter + to_unsigned(1,4); - end if; - end if; - end process; - - J2_P <= cms_output; - - - -------------------------------------------------------------------------------- --- trigger and readout logic -------------------------------------------------------------------------------- - - GEN_READOUT_LOGIC : if INCLUDE_READOUT = c_YES generate - - THE_TRIG_DISTR : trigger_distributor - port map ( - CLK => CLK_100, - RESET => reset_internal, - INTERNAL_RESET_IN => pulse_begin_run_trigger_i, - A_RDO_IN => token_to_mux_out_i, - TRIGGER_IN => timing_trigger_received, --pulse_pseudo_timing_trigger, - TRIGGER_TYPE_IN => LVL1_TRG_TYPE_OUT, - INIT_ALL_BUSES_OUT => init_all_buses_i, - ROC1_WRITTEN_IN => roc1_written_i, - TOKEN_TO_TRB_OUT => open,--LVL1_TRG_RELEASE_IN, - CAL_TRIGGER_REGISTER_IN => cal_trigger_register_in_i, - DEBUG_REGISTER_OUT => debug_trigger_distributor_i, - LED_CNT_1_OUT => D(4), - LED_CNT_2_OUT => D(3), - LED_ERROR_OUT => D(2), - LED_GOOD_OUT => D(1) - ); + real_flash_rom_select <= "00" when reg_CS = "10" else + "01" when reg_CS = "01" else + "10"; --------------------------------------------------------------------- --- FEE Readout +-- FEE Control --------------------------------------------------------------------- - THE_MDC_OEP_READOUT : mdc_addon_daq_bus_0 - --generic map (bus_number => bus_number) - port map ( - CLK => CLK_100, - RESET => reset_mdc_addon_daq_bus_0,--reset_internal, - A_ADS_0 => '0', - A_ADS_1 => '0', - A_ADS_2 => '0', - A_ACK => TACK, - A_CMS => a_cms_i, --CMS, - A_RDM => RDYI,--out to MB - A_GDE => GDE, - A_RDO => TRDYO,--in - A_RESERV => TRSV, - A_DRA => open, - A_DRB_1 => open, - A_DRB_2 => open, - A_DRE => open, - A_ENB_1 => open, - A_ENB_2 => open, - A_ENR_1 => open, - A_ENR_2 => open, - A_FET_ENABLE => open, - A_REN => open, - A_MOD => MODD, - A_RES => RES, - A_TOK => TOK, - A_WRM => WRM, - TOKEN_TO_MUX_OUT => token_to_mux_out_i, - TRIGGER_TYPE_IN => init_all_buses_i, - LA => open, - D => open, - A_RDO_OUT => open, - ROC1_WRITTEN_OUT => roc1_written_i, - DATA_TYPE_SELECT_IN => data_type_select_in_i, - DIRECTION_DATA_LINE_OUT => direction_data_line_out_i, - MOTHERBOARD_TYPE_IN => motherboard_type_in_i, - - ACKNOWLEDGE_TRB_INTERFACE_IN => x"1", - INIT_TRB_INTERFACE_OUT => open, - DATA_OUT => open, - READ_FIFO_IN => '0', - DEBUG_REGISTER_TRB_INTERFACE => (others => '0'), - - RAM_ADDRESS_IN => thresh_mem_addr,-- (others => '0'), --8 to 0 - RAM_DATA_IN => thresh_mem_data,--15 to 0 - RAM_DATA_OUT => thresh_mem_data_out, - RAM_READ_ENABLE_IN => '0', - RAM_WRITE_ENABLE_IN => thresh_mem_write, - - A_ADD_CONFIGURATION_OUT => a_add_configuration_i, - A_DST_CONFIGURATION_OUT => a_dst_configuration_i, - A_AOD_CONFIGURATION_OUT => a_aod_configuration_i, - - A_ADD_DATA_IN => a_add_data_i, - A_DST_DATA_IN => a_dst_data_i, - A_AOD_DATA_IN => a_aod_data_i, - - DEBUG_REGISTER_0_BUS_0 => test_debug_i, - DEBUG_REGISTER_1_BUS_0 => open, - DEBUG_REGISTER_2_BUS_0 => open, - DEBUG_REGISTER_3_BUS_0 => open, - DEBUG_REGISTER_4_BUS_0 => open, - DEBUG_REGISTER_5_BUS_0 => open, - DEBUG_REGISTER_6_BUS_0 => open, - DEBUG_REGISTER_7_BUS_0 => open, - - LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_OUT, - LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_OUT, - LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_OUT, - LVL1_TRG_CODE_IN => LVL1_TRG_CODE_OUT, - LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_OUT, - LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_IN, - LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_IN, - LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT, - - --Data Port - IPU_NUMBER_IN => IPU_NUMBER_OUT, - IPU_INFORMATION_IN => IPU_INFORMATION_OUT, - --start strobe - IPU_START_READOUT_IN => IPU_START_READOUT_OUT, - --detector data, equipped with DHDR - IPU_DATA_OUT => IPU_DATA_IN, - IPU_DATAREADY_OUT => IPU_DATAREADY_IN, - --no more data, end transfer, send TRM - IPU_READOUT_FINISHED_OUT => IPU_READOUT_FINISHED_IN, - --will be low every second cycle due to 32bit -> 16bit conversion - IPU_LENGTH_OUT => IPU_LENGTH_IN, - IPU_ERROR_PATTERN_OUT => IPU_ERROR_PATTERN_IN, - IPU_READ_IN => IPU_READ_OUT - ); - -------------------------------------------------------------------------------- --- DATA MULTIPLEXER for INOUT DST, AOD,TAD -------------------------------------------------------------------------------- - process(direction_data_line_out_i, - a_add_configuration_i, a_aod_configuration_i, - a_dst_configuration_i) - begin - --CONFIGURATION or CALIBRATION - if (direction_data_line_out_i = x"D") then - TAOD <= a_aod_configuration_i; - TDST <= a_dst_configuration_i; - TAD <= a_add_configuration_i; - --DATA TAKING - else - TAOD <= 'Z'; - TDST <= 'Z'; - TAD <= (others => 'Z'); - end if; - end process; - - - process(CLK_100) - begin - if rising_edge(CLK_100) then - if (direction_data_line_out_i = x"D") then - a_add_data_i <= (others => '0'); - a_aod_data_i <= '0'; - a_dst_data_i <= '0'; - else - a_add_data_i <= TAD; - a_aod_data_i <= TAOD; - a_dst_data_i <= TDST; - end if; - end if; - end process; - end generate; - - + THE_MDC_CONTROL : mdc_control + port map( + CLK => clk_100, + RESET => reset_internal, + + A_ADD => TAD, + A_AOD => TAOD, + A_DST => TDST, + A_RDM => RDYI, + A_GDE => GDE, + A_RDO => TRDYO, + A_MOD => MODD, + A_RES => RES, + A_TOK => TOK, + A_WRM => WRM, + A_RESERVE => TRSV, + + TRIGGER_IN => COM_STOP_P, + TRIGGER_OUT => CMS, + TRIGGER_MONITOR_OUT => timing_trg_received_i, + + LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, + LVL1_INVALID_TRG_IN => trg_invalid_i, + LVL1_TRG_TYPE_IN => trg_type_i, + LVL1_TRG_NUMBER_IN => trg_number_i, + LVL1_TRG_INFORMATION_IN => trg_information_i, + LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, + LVL1_RELEASE_OUT => fee_trg_release_i, + LVL1_STATUSBITS_OUT => fee_trg_statusbits_i, + + FEE_DATA_OUT => fee_data_i, + FEE_DATA_WRITE_OUT => fee_data_write_i, + FEE_DATA_FINISHED_OUT => fee_data_finished_i, + + RAM_ADDRESS_IN => thresh_mem_addr, + RAM_DATA_IN => thresh_mem_data, + RAM_DATA_OUT => thresh_mem_data_out, + RAM_READ_ENABLE_IN => thresh_mem_read, + RAM_WRITE_ENABLE_IN => thresh_mem_write, + RAM_READY_OUT => thresh_mem_ready, + + STAT_ADDRESS_IN => statreg_addr, + STAT_DATA_OUT => statreg_data, + STAT_READ_ENABLE_IN => statreg_read, + STAT_READY_OUT => statreg_ready, + + RB_DATA_OUT => readback_mem_data_out, + RB_READ_ENABLE_IN => readback_mem_read, + RB_READY_OUT => readback_mem_ready, + RB_EMPTY_OUT => readback_mem_empty, + + COMMON_STAT_REG_OUT => reg_common_stat_reg_in, + COMMON_CTRL_REG_IN => reg_common_ctrl_reg_out, + CTRL_REG_IN => reg_registers_out, + + DEBUG_OUT => debug_mdc_control_i + ); ------------------------------------------------------------------------------- --- pin not used input for fpga -------------------------------------------------------------------------------- --- TENR <= 'Z'; --- TDRB <= 'Z'; --- TENB <= 'Z'; --- TDRE <= 'Z'; --- TCDE_0 <= 'Z'; --- TADS0 <= 'Z'; --- TADS_1 <= 'Z'; --- TOR <= 'Z'; --- TDRA <= 'Z'; - --- ADI_0 <= 'Z'; --- ADI_1 <= 'Z'; ---------------------------------------------------------------------- -- LED ---------------------------------------------------------------------- - --- TAD(0) <= CLK; --- TAD(8 downto 1) <= LVL1_INT_TRG_NUMBER_OUT(1 downto 0) & LVL1_TRG_RELEASE_IN & LVL1_TRG_RECEIVED_OUT & LVL1_TRG_NUMBER_OUT(3 downto 0); - ---------------------------------------------------------------------- --- List of debugging signals ---------------------------------------------------------------------- +------------------------------------------------------------------------------- + D(4) <= '1'; + D(3) <= '1'; + D(2) <= '1'; + D(1) <= '1'; --- TAD(0) <= CLK; --- TAD(8 downto 1) <= MED_STAT_DEBUG(39 downto 32); - - --- STAT_OP(2 downto 0) <= med_error; --- STAT_OP(8 downto 3) <= (others => '0'); --- STAT_OP(9) <= link_led; --- STAT_OP(10) <= rx_led; --- STAT_OP(11) <= tx_led; --- STAT_OP(12) <= '0'; --- STAT_OP(13) <= buf_RESET_TRBNET_OUT; --- STAT_OP(14) <= reset_me; -- reset out --- STAT_OP(15) <= buf_RESET_TRBNET_OUT; - --- STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32); --- stat_debug(3 downto 0) <= state_bits; --- stat_debug(4) <= align_me; --- stat_debug(5) <= buf_swap_bytes; --- stat_debug(6) <= resync; --- stat_debug(7) <= sfp_missing_in; --- stat_debug(8) <= sfp_los_in; --- stat_debug(31 downto 9) <= (others => '0'); --- STAT_DEBUG(39 downto 32) <= buf_rx_data_reg(7 downto 0); --- STAT_DEBUG(40) <= rx_fifo_write_en; --- STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout; --- STAT_DEBUG(63 downto 49) <= (others => '0'); ------------------------------------------------------------------------------- --- test power consumption +-- pins not used ------------------------------------------------------------------------------- --- PARITYGEN : oddParityGen --- generic map(width => 10) --- port map ( --- CLK => CLK_100, --- ad => input_parity_gen, --- oddParity => D(4) --- ); - --- input_parity_gen(9 downto 8) <= (others => '1'); --- input_parity_gen(7 downto 4) <= direction_data_line_out_i; --- input_parity_gen(3 downto 0) <= x"a"; - --- parallel_FIFO : for i in 1 to 2 generate - - --- DATA : fifo_8192depth_36width_dual_thresh_reg_out --- port map ( --- Data => (others => '1'),--counter_data, --- Clock => CLK, --- WrEn => counter_data(0), --- RdEn => counter_data(5), --- Reset => reset_internal, --- AmEmptyThresh => "0000000000100", --- AmFullThresh => "1110000000000", --- Q => data_out(i), --- WCNT => open, --- Empty => open, --- Full => open, --- AlmostEmpty => open, --- AlmostFull => open); - --- end generate; - ---counter_data_conv <= conv_std_logic_vector(counter_data); - --- D(4) <= data_out(1)(5) and data_out(2)(15);-- and data_out(3)(16); - --- process(CLK_100, reset_internal) --- begin --- if rising_edge(CLK_100) then --- if (reset_internal = '1' or counter_data = x"00fff4E20" ) then --- counter_data <= (others => '0'); --- elsif (counter_data < x"0ffff4E20") then --- counter_data <= counter_data + 1; --- else --- counter_data <= counter_data; --- end if; --- end if; --- end process; - --- SHIFT_TEST : for i in 1 to 2999 generate - --- TEST: xor2test --- port map ( --- Clock => CLK_100, --- L => motherboard_type_in_i(0), --- w => motherboard_type_in_i(0), --- Output => out_shift_reg(i), --- Input => motherboard_type_in_i(3 downto 0)); - --- end generate; - - --- TEST1: xor2test --- port map ( --- Clock => CLK_100, --- L => motherboard_type_in_i(2), --- w => motherboard_type_in_i(3), --- Output => out_shift_reg1, --- Input => cal_trigger_register_in_i(3 downto 0)); - - --- process(CLK_100) --- begin --- if rising_edge(CLK_100) then --- for i in 1 to 2999 loop --- temp_led0 <= out_shift_reg(i)(3) or out_shift_reg(i+1)(0) or out_shift_reg1(1); --- temp_led1 <= out_shift_reg(i)(2) and out_shift_reg(i+1)(1) and out_shift_reg1(2); --- temp_led2 <= out_shift_reg(i)(1) or out_shift_reg(i+1)(2) or out_shift_reg1(3); --- temp_led3 <= out_shift_reg(i)(0) and out_shift_reg(i+1)(3) and out_shift_reg1(0); --- end loop; --- end if; --- end process; - --- D(4) <= temp_led0; --- D(3) <= temp_led1; --- D(2) <= temp_led2; --- D(1) <= temp_led3; - end architecture; diff --git a/mdc_oepb_testbench.vhd b/mdc_oepb_testbench.vhd new file mode 100644 index 0000000..4b50e18 --- /dev/null +++ b/mdc_oepb_testbench.vhd @@ -0,0 +1,249 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.mdc_oepb_pack.all; +use work.trb_net_components.all; + +entity tb is +end entity; + +architecture arch of tb is + + signal CLK : std_logic := '1'; + signal reset_internal : std_logic := '1'; + + signal TAD : std_logic_vector(8 downto 0) := (others => 'Z'); + signal TAOD : std_logic := 'Z'; + signal TDST : std_logic := 'Z'; + signal RDYI : std_logic; + signal GDE : std_logic; + signal TRDYO : std_logic; + signal MODD : std_logic; + signal RES : std_logic; + signal TOK : std_logic; + signal WRM : std_logic; + signal TRSV : std_logic; + + signal COM_STOP_P : std_logic := '0'; + signal CMS : std_logic; + signal timing_trg_received_i : std_logic := '0'; + signal trg_data_valid_i : std_logic := '0'; + signal trg_timing_valid_i : std_logic := '0'; + signal trg_notiming_valid_i : std_logic := '0'; + signal trg_invalid_i : std_logic := '0'; + signal trg_type_i : std_logic_vector(3 downto 0); + signal trg_number_i : std_logic_vector(15 downto 0); + signal trg_information_i : std_logic_vector(23 downto 0); + signal trg_int_number_i : std_logic_vector(15 downto 0); + signal fee_trg_release_i : std_logic; + signal fee_trg_statusbits_i : std_logic_vector(31 downto 0); + + signal common_ctrl_reg : std_logic_vector(95 downto 0); + signal ctrl_reg : std_logic_vector(63 downto 0); + signal token_back_i : std_logic; + + signal ram_address : std_logic_vector(8 downto 0); + signal ram_din : std_logic_vector(15 downto 0); + signal ram_read : std_logic; + signal ram_write : std_logic; + + + +begin + reset_internal <= '0' after 100 ns; + CLK <= not CLK after 5 ns; + + ctrl_reg <= x"0000000000000010"; + + TRSV <= '0'; + +--RAM + process + begin + ram_address <= (others => '0'); + ram_din <= (others => '0'); + ram_read <= '0'; + ram_write <= '0'; + wait for 500 ns; + wait until rising_edge(CLK); + ram_address <= "000000010"; + ram_read <= '1'; + wait until rising_edge(CLK); + ram_read <= '0'; + wait; + end process; + + +--Common Stop + process + begin + COM_STOP_P <= '0'; + trg_timing_valid_i <= '0'; + trg_notiming_valid_i <= '0'; + trg_int_number_i <= (others => '0'); + trg_number_i <= (others => '0'); + trg_type_i <= x"1"; + trg_information_i<= (others => '0'); + wait for 4 ms; + COM_STOP_P <= '1'; + wait for 100 ns; + COM_STOP_P <= '0'; + wait for 50 ns; + wait until rising_edge(CLK); + trg_timing_valid_i <= '1'; + wait until rising_edge(CLK); + trg_timing_valid_i <= '0'; + wait for 400 us; + wait until rising_edge(CLK); + trg_type_i <= x"9"; + trg_data_valid_i <= '1'; + trg_notiming_valid_i <= '1'; + wait for 50 ns; + wait until rising_edge(CLK); + trg_notiming_valid_i <= '0'; + wait until fee_trg_release_i = '1'; + wait until rising_edge(CLK); + trg_data_valid_i <= '0'; + wait; + end process; + + +--Begrun trigger + process + begin + common_ctrl_reg <= (95 => '1', others => '0'); + wait for 200 ns; + wait until rising_edge(CLK); + common_ctrl_reg(22) <= '1'; + wait until rising_edge(CLK); + common_ctrl_reg(22) <= '0'; + wait; + end process; + +--Token Back + process + begin + TRDYO <= '0'; + wait for 500 us; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + wait for 340 us; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + wait for 2500 us; + for i in 0 to 100 loop + wait until token_back_i = '1'; + TRDYO <= '1'; + wait for 50 ns; + TRDYO <= '0'; + end loop; + wait; + end process; + +-- Data I/O + process + begin + TAD <= (others => 'Z'); + TAOD <= 'Z'; + TDST <= 'Z'; + token_back_i <= '0'; + wait for 3000 us; + wait for 1 ns; + for j in 0 to 300 loop + wait until RDYI = '1'; + wait for 200 ns; + for i in 0 to 30 loop + TAD <= std_logic_vector(to_unsigned(i*2,9)); + TAOD <= '0'; + TDST <= '0'; + wait for 10 ns; + TDST <= '1'; + wait for 40 ns; + TDST <= '0'; + wait for 20 ns; + TAD <= std_logic_vector(to_unsigned(i*2+1,9)); + TAOD <= '1'; + TDST <= '0'; + wait for 10 ns; + TDST <= '1'; + wait for 40 ns; + TDST <= '0'; + wait for 20 ns; + end loop; + token_back_i <= '1'; + wait for 30 ns; + token_back_i <= '0'; + TAD <= (others => 'Z'); + TAOD <= 'Z'; + TDST <= 'Z'; + end loop; + wait; + end process; + + + THE_MDC_CONTROL : mdc_control + port map( + CLK => CLK, + RESET => reset_internal, + + A_ADD => TAD, + A_AOD => TAOD, + A_DST => TDST, + A_RDM => RDYI, + A_GDE => GDE, + A_RDO => TRDYO, + A_MOD => MODD, + A_RES => RES, + A_TOK => TOK, + A_WRM => WRM, + A_RESERVE => TRSV, + + TRIGGER_IN => COM_STOP_P, + TRIGGER_OUT => CMS, + TRIGGER_MONITOR_OUT => timing_trg_received_i, + + LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, + LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i, + LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, + LVL1_INVALID_TRG_IN => trg_invalid_i, + LVL1_TRG_TYPE_IN => trg_type_i, + LVL1_TRG_NUMBER_IN => trg_number_i, + LVL1_TRG_INFORMATION_IN => trg_information_i, + LVL1_INT_TRG_NUMBER_IN => trg_int_number_i, + LVL1_RELEASE_OUT => fee_trg_release_i, + LVL1_STATUSBITS_OUT => fee_trg_statusbits_i, + + FEE_DATA_OUT => open, + FEE_DATA_WRITE_OUT => open, + FEE_DATA_FINISHED_OUT => open, + + RAM_ADDRESS_IN => ram_address, + RAM_DATA_IN => ram_din, + RAM_DATA_OUT => open, + RAM_READ_ENABLE_IN => ram_read, + RAM_WRITE_ENABLE_IN => ram_write, + RAM_READY_OUT => open, + + STAT_ADDRESS_IN => (others => '0'), + STAT_DATA_OUT => open, + STAT_READ_ENABLE_IN => '0', + STAT_READY_OUT => open, + + RB_DATA_OUT => open, + RB_READ_ENABLE_IN => '0', + RB_READY_OUT => open, + RB_EMPTY_OUT => open, + + COMMON_STAT_REG_OUT => open, + COMMON_CTRL_REG_IN => common_ctrl_reg, + CTRL_REG_IN => ctrl_reg, + + DEBUG_OUT => open + ); + +end architecture; \ No newline at end of file -- 2.43.0