From 87ae436e4bca0f31f29d65d1ee5bb811f72d314d Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 5 Dec 2021 21:43:11 +0100 Subject: [PATCH] debug pins unified --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 23 +- media_interfaces/sync/med_sync_control_RS.vhd | 27 ++- media_interfaces/sync/rx_rsl.vhd | 40 ++-- media_interfaces/sync/rx_rsl_ORIG.vhd | 224 ++++++++++++++++++ 4 files changed, 270 insertions(+), 44 deletions(-) create mode 100644 media_interfaces/sync/rx_rsl_ORIG.vhd diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index ced1d90..03de147 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -26,12 +26,12 @@ entity med_ecp3_sfp_sync_all_RS is MEDIA_MED2INT : out med2int_array_t(0 to 3); MEDIA_INT2MED : in int2med_array_t(0 to 3); -- komma operation - RX_DLM_OUT : out std_logic_vector(3 downto 0); -- DLM received - RX_DLM_WORD_OUT : out std_logic_vector(4*8-1 downto 0); + RX_DLM_OUT : out std_logic_vector(3 downto 0); -- DLM received, one clock cycle active + RX_DLM_WORD_OUT : out std_logic_vector(4*8-1 downto 0); -- DLM data byte, registered TX_DLM_IN : in std_logic; TX_DLM_WORD_IN : in std_logic_vector(7 downto 0); - RX_RST_OUT : out std_logic; -- RST received - RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); + RX_RST_OUT : out std_logic; -- RST received, one clock cycle active + RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- RST data byte, registered TX_RST_IN : in std_logic; TX_RST_WORD_IN : in std_logic_vector(7 downto 0); -- sync operation @@ -477,8 +477,8 @@ end generate; BUS_RX => BUS_RX, BUS_TX => BUS_TX, -- - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), MEDIA_STATUS_REG_IN(191 downto 64) => stat_fsm_reset_i(127 downto 0), MEDIA_STATUS_REG_IN(199 downto 192) => cv_cnt_sys(0), MEDIA_STATUS_REG_IN(207 downto 200) => cv_cnt_sys(1), @@ -493,11 +493,12 @@ end generate; STAT_DEBUG(63 downto 0) <= (others => '0'); -- DEBUG_OUT <= debug_i(3*32+31 downto 3*32); - DEBUG_OUT(8 downto 0) <= debug_i(3*32+8 downto 3*32); - DEBUG_OUT(9) <= wa_read_i; - DEBUG_OUT(10) <= tx_clk_avail_sel; - DEBUG_OUT(11) <= GLOBAL_RESET_IN; - DEBUG_OUT(31 downto 12) <= debug_i(3*32+31 downto 3*32+12); + DEBUG_OUT(11 downto 0) <= debug_i(3*32+11 downto 3*32); + DEBUG_OUT(12) <= wa_read_i; + DEBUG_OUT(13) <= tx_clk_avail_sel; + DEBUG_OUT(14) <= GLOBAL_RESET_IN; + DEBUG_OUT(15) <= '0'; + DEBUG_OUT(31 downto 16) <= debug_i(3*32+31 downto 3*32+16); end architecture; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index e28b7f8..a46bdef 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -289,19 +289,20 @@ begin else x"7"; -- TEST_LINE signals - DEBUG_OUT(0) <= SFP_LOS_IN; - DEBUG_OUT(1) <= RX_LOS_IN; - DEBUG_OUT(2) <= RX_CDR_LOL_IN; - DEBUG_OUT(3) <= rx_pcs_rst_i; - DEBUG_OUT(4) <= rx_serdes_rst_i; - DEBUG_OUT(5) <= TX_PLL_LOL_IN; - DEBUG_OUT(6) <= is_wap_zero_i; - DEBUG_OUT(7) <= link_rx_ready_i; - DEBUG_OUT(8) <= LINK_TX_READY_IN; - DEBUG_OUT(9) <= '0'; - DEBUG_OUT(10) <= '0'; - DEBUG_OUT(11) <= '0'; - DEBUG_OUT(15 downto 12) <= rx_fsm_state; + DEBUG_OUT(3 downto 0) <= rx_fsm_state; + DEBUG_OUT(4) <= RX_LOS_IN; + DEBUG_OUT(5) <= RX_CDR_LOL_IN; + DEBUG_OUT(6) <= TX_PLL_LOL_IN; + DEBUG_OUT(7) <= LINK_TX_READY_IN; + DEBUG_OUT(8) <= link_rx_ready_i; + DEBUG_OUT(9) <= is_wap_zero_i; + DEBUG_OUT(10) <= link_half_done_i; + DEBUG_OUT(11) <= link_full_done_i; + DEBUG_OUT(12) <= '0'; + DEBUG_OUT(13) <= '0'; + DEBUG_OUT(14) <= '0'; + DEBUG_OUT(15) <= '0'; +-- 16 pin debug connector ends here DEBUG_OUT(21 downto 16) <= debug_tx_control_i(5 downto 0); DEBUG_OUT(31 downto 22) <= (others => '0'); -- DEBUG_OUT <= (others => '0'); diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd index 0e3cabf..019a903 100644 --- a/media_interfaces/sync/rx_rsl.vhd +++ b/media_interfaces/sync/rx_rsl.vhd @@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is signal cnt : unsigned(31 downto 0); type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, - APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, - CHECK_WAP, TX_SYNC, NORMAL_OP); + CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, + TEST_RXPCS, NORMAL_OP); signal rx_sm : rx_sm_state; @@ -131,15 +131,28 @@ begin else if( cnt = Tcdr ) then cnt <= (others => '0'); - rx_sm <= APPLY_RXPCS_RST; + rx_sm <= CHECK_WAP; else cnt <= cnt + 1; end if; end if; - when APPLY_RXPCS_RST => + -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR + when CHECK_WAP => STATE_OUT <= x"4"; RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; -- really? + LINK_RX_READY_OUT <= '0'; + cnt <= (others => '0'); + if( WAP_ZERO_IN = '1' ) then + rx_sm <= NORMAL_OP; + else + rx_sm <= APPLY_CDR_RST; + end if; + + when APPLY_RXPCS_RST => + STATE_OUT <= x"5"; + RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; if( cnt = Tshort ) then @@ -150,7 +163,7 @@ begin end if; when WAIT_RXPCS_LOCK => - STATE_OUT <= x"5"; + STATE_OUT <= x"6"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -162,7 +175,7 @@ begin end if; when TEST_RXPCS => - STATE_OUT <= x"6"; + STATE_OUT <= x"7"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; @@ -172,24 +185,11 @@ begin else if( cnt = Tviol ) then cnt <= (others => '0'); - rx_sm <= CHECK_WAP; + rx_sm <= NORMAL_OP; else cnt <= cnt + 1; end if; end if; - - when CHECK_WAP => - STATE_OUT <= x"7"; - RX_SERDES_RST_OUT <= '0'; - RX_PCS_RST_OUT <= '0'; - LINK_RX_READY_OUT <= '0'; - cnt <= (others => '0'); - if( WAP_ZERO_IN = '1' ) then - rx_sm <= NORMAL_OP; - else --- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK - rx_sm <= APPLY_CDR_RST; - end if; when NORMAL_OP => STATE_OUT <= x"8"; diff --git a/media_interfaces/sync/rx_rsl_ORIG.vhd b/media_interfaces/sync/rx_rsl_ORIG.vhd new file mode 100644 index 0000000..0e3cabf --- /dev/null +++ b/media_interfaces/sync/rx_rsl_ORIG.vhd @@ -0,0 +1,224 @@ +library ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.all; + +entity rx_rsl is + port ( + CLEAR : in std_logic; + CLK_REF : in std_logic; + PLL_LOL_IN : in std_logic; + CDR_LOL_IN : in std_logic; + CV_IN : in std_logic; + LSM_IN : in std_logic; + LOS_IN : in std_logic; + WAP_ZERO_IN : in std_logic; + -- outputs + RX_SERDES_RST_OUT : out std_logic; + RX_PCS_RST_OUT : out std_logic; + LINK_RX_READY_OUT : out std_logic; + STATE_OUT : out std_logic_vector(3 downto 0) + ); +end rx_rsl; + +architecture rx_rsl_arc of rx_rsl is + + attribute syn_keep : boolean; + +-- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3. +-- Without this piece of code, many things would have been a real pain. + + constant Tshort : unsigned(31 downto 0) := x"0000000a"; +-- @200MHz 100ms + constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + + signal pll_lol_s : std_logic; + signal cdr_lol_s : std_logic; + signal cv_s : std_logic; + signal lsm_s : std_logic; + signal los_s : std_logic; + + signal cnt : unsigned(31 downto 0); + + type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, + APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, + CHECK_WAP, TX_SYNC, NORMAL_OP); + + signal rx_sm : rx_sm_state; + + attribute syn_keep of rx_sm : signal is true; + +begin + +-- Remark: on ECP3, rx_serdes_rst sets RX_CDR_LOL. Deadlocks on POWERUP. +-- Remark: RX_LOS is not necessary, as SFP_LOS keeps us safely in reset. +-- Remark: syncing is done here by one FF only. Might be dangerous. + +------------------------------------------------------------------ +RX_RESET_PROC : process( CLEAR, CLK_REF ) +begin + if( CLEAR = '1' ) then + pll_lol_s <= '1'; + cdr_lol_s <= '1'; + cv_s <= '1'; + lsm_s <= '0'; + los_s <= '1'; + + RX_SERDES_RST_OUT <= '1'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + + rx_sm <= powerup; + STATE_OUT <= x"f"; + cnt <= (others => '0'); + elsif( rising_edge(CLK_REF) ) then + pll_lol_s <= PLL_LOL_IN; + cdr_lol_s <= CDR_LOL_IN; + cv_s <= CV_IN; + lsm_s <= LSM_IN; + los_s <= LOS_IN; + + case rx_sm is + when POWERUP => + STATE_OUT <= x"0"; + RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + if( (pll_lol_s = '1') or (los_s = '1') ) then + cnt <= (others => '0'); + else + if( cnt = Tplol ) then + cnt <= (others => '0'); + rx_sm <= APPLY_CDR_RST; + else + cnt <= cnt + 1; + end if; + end if; + + when APPLY_CDR_RST => + STATE_OUT <= x"1"; + RX_SERDES_RST_OUT <= '1'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + if( cnt = Tshort ) then + cnt <= (others => '0'); + rx_sm <= WAIT_CDR_LOCK; + else + cnt <= cnt + 1; + end if; + + when WAIT_CDR_LOCK => + STATE_OUT <= x"2"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + if( cnt = Tcdr ) then + cnt <= (others => '0'); + rx_sm <= TEST_CDR; + else + cnt <= cnt + 1; + end if; + + when TEST_CDR => + STATE_OUT <= x"3"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + if( cdr_lol_s = '1' ) then + cnt <= (others => '0'); + rx_sm <= APPLY_CDR_RST; + else + if( cnt = Tcdr ) then + cnt <= (others => '0'); + rx_sm <= APPLY_RXPCS_RST; + else + cnt <= cnt + 1; + end if; + end if; + + when APPLY_RXPCS_RST => + STATE_OUT <= x"4"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '1'; + LINK_RX_READY_OUT <= '0'; + if( cnt = Tshort ) then + cnt <= (others => '0'); + rx_sm <= WAIT_RXPCS_LOCK; + else + cnt <= cnt + 1; + end if; + + when WAIT_RXPCS_LOCK => + STATE_OUT <= x"5"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + if( cnt = Tviol ) then + cnt <= (others => '0'); + rx_sm <= TEST_RXPCS; + else + cnt <= cnt + 1; + end if; + + when TEST_RXPCS => + STATE_OUT <= x"6"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + if( (lsm_s = '0') or (cv_s = '1') ) then + cnt <= (others => '0'); + rx_sm <= APPLY_RXPCS_RST; + else + if( cnt = Tviol ) then + cnt <= (others => '0'); + rx_sm <= CHECK_WAP; + else + cnt <= cnt + 1; + end if; + end if; + + when CHECK_WAP => + STATE_OUT <= x"7"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + cnt <= (others => '0'); + if( WAP_ZERO_IN = '1' ) then + rx_sm <= NORMAL_OP; + else +-- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK + rx_sm <= APPLY_CDR_RST; + end if; + + when NORMAL_OP => + STATE_OUT <= x"8"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '1'; + cnt <= (others => '0'); + if( (lsm_s = '0') or (cv_s = '1') ) then + rx_sm <= APPLY_RXPCS_RST; + end if; + + when others => + -- just in case + STATE_OUT <= x"f"; + RX_SERDES_RST_OUT <= '0'; + RX_PCS_RST_OUT <= '0'; + LINK_RX_READY_OUT <= '0'; + rx_sm <= POWERUP; + + end case; + +------------------------------------------------ +-- if (pll_lol_s = '1') or (los_s = '1') then + if( pll_lol_s = '1' ) then + rx_sm <= POWERUP; + cnt <= (others => '0'); + end if; + + end if; +end process rx_reset_proc; + +end rx_rsl_arc; -- 2.43.0