From 87c2814c7c1a6c3faefd7646f49fad3d7cce63b9 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Sun, 14 Jul 2013 00:04:41 +0200 Subject: [PATCH] new port handler, nxyter_histo is new --- nxyter/source/nx_data_validate.vhd | 2 +- nxyter/source/nx_event_buffer.vhd | 1 + nxyter/source/nx_histograms.vhd | 123 ++++++++++++++ nxyter/source/nx_trigger_handler.vhd | 12 +- nxyter/source/nx_trigger_validate.vhd | 194 +++++++++++---------- nxyter/source/nxyter_components.vhd | 24 +++ nxyter/source/nxyter_fee_board.vhd | 234 ++++++++------------------ nxyter/source/registers.txt | 8 +- nxyter/trb3_periph.prj | 1 + 9 files changed, 345 insertions(+), 254 deletions(-) create mode 100644 nxyter/source/nx_histograms.vhd diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index ae024b4..1bc8d71 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -102,7 +102,7 @@ begin --DEBUG_OUT(15 downto 9) <= channel_o; ----------------------------------------------------------------------------- - -- Gray Decoder for Timestamp and Chgannel Id + -- Gray Decoder for Timestamp and Channel Id ----------------------------------------------------------------------------- Gray_Decoder_1: Gray_Decoder -- Decode nx_timestamp diff --git a/nxyter/source/nx_event_buffer.vhd b/nxyter/source/nx_event_buffer.vhd index 0d38c1e..8abae5e 100644 --- a/nxyter/source/nx_event_buffer.vhd +++ b/nxyter/source/nx_event_buffer.vhd @@ -4,6 +4,7 @@ use ieee.numeric_std.all; library work; use work.nxyter_components.all; +use work.trb3_components.all; entity nx_event_buffer is generic ( diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd new file mode 100644 index 0000000..e998cb1 --- /dev/null +++ b/nxyter/source/nx_histograms.vhd @@ -0,0 +1,123 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity nx_histograms is + generic ( + NUM_BINS : integer := 7 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + RESET_HISTS_IN : in std_logic; + + CHANNEL_STAT_FILL_IN : in std_logic; + CHANNEL_ID_IN : in std_logic_vector(NUM_BINS - 1 downto 0); + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + +end entity; + +architecture nx_histograms of nx_histograms is + + type histogram_t is array(0 to 127) of unsigned(31 downto 0); + signal hist_channel_stat : histogram_t; + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal reset_hists_r : std_logic; + +begin + + PROC_CHANNEL_HIST : process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then + for I in (NUM_BINS - 1) downto 0 loop + hist_channel_stat(I) <= (others => '0'); + end loop; + else + if (CHANNEL_STAT_FILL_IN = '1') then + hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <= + hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1; + end if; + end if; + end if; + end process PROC_CHANNEL_HIST; + + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + -- Give status info to the TRB Slow Control Channel + PROC_HISTOGRAMS_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + reset_hists_r <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_ack_o <= '0'; + + reset_hists_r <= '0'; + + if (SLV_READ_IN = '1') then + if (unsigned(SLV_ADDR_IN) >= x"0000" and + unsigned(SLV_ADDR_IN) < x"0080") then + slv_data_out_o <= std_logic_vector( + hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) + ); + slv_ack_o <= '1'; + else + slv_unknown_addr_o <= '1'; + end if; + + elsif (SLV_WRITE_IN = '1') then + + case SLV_ADDR_IN is + + when x"0000" => + reset_hists_r <= '1'; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + + end case; + end if; + end if; + end if; + end process PROC_HISTOGRAMS_READ; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- Slave + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + + end nx_histograms; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index 4bb25b0..9cd632e 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -157,7 +157,15 @@ begin case STATE is when S_IDLE => - if (LVL1_VALID_TIMING_TRG_IN = '1') then + + if (LVL1_VALID_NOTIMING_TRG_IN = '1') then + STATE <= S_WAIT_TRG_DATA_VALID; + + elsif (LVL1_INVALID_TRG_IN = '1') then + fee_trg_release_o <= '1'; + STATE <= S_IDLE; + + elsif (LVL1_VALID_TIMING_TRG_IN = '1') then if (NXYTER_OFFLINE_IN = '1') then STATE <= S_WAIT_TRG_DATA_VALID; else @@ -276,7 +284,7 @@ begin slv_no_more_data_o <= '0'; slv_unknown_addr_o <= '0'; slv_ack_o <= '0'; - reg_timestamp_hold_delay <= x"3f"; + reg_timestamp_hold_delay <= x"01"; else slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 565d00a..5915259 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -3,7 +3,6 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; -use work.trb_net_std.all; use work.nxyter_components.all; entity nx_trigger_validate is @@ -29,6 +28,10 @@ entity nx_trigger_validate is DATA_OUT : out std_logic_vector(31 downto 0); DATA_CLK_OUT : out std_logic; NOMORE_DATA_OUT : out std_logic; + + -- Histogram + HISTOGRAM_FILL_OUT : out std_logic; + HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); -- Slave bus SLV_READ_IN : in std_logic; @@ -97,7 +100,11 @@ architecture Behavioral of nx_trigger_validate is -- Timer signal wait_timer_done : std_logic; - + + -- Histogram + signal histogram_fill_o : std_logic; + signal histogram_bin_o : std_logic_vector(6 downto 0); + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -111,21 +118,21 @@ architecture Behavioral of nx_trigger_validate is signal window_lower_thr_r : std_logic_vector(11 downto 0); signal window_upper_thr_r : std_logic_vector(11 downto 0); - + begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(2) <= trigger_busy_o; - DEBUG_OUT(3) <= channel_all_done; - DEBUG_OUT(4) <= data_clk_o; - DEBUG_OUT(5) <= t_data_clk_o; - DEBUG_OUT(6) <= out_of_window_l; - DEBUG_OUT(7) <= out_of_window_h; - DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN; - DEBUG_OUT(9) <= NX_NOMORE_DATA_IN; - DEBUG_OUT(10) <= store_to_fifo; - DEBUG_OUT(15 downto 11) <= (others => '0'); +-- DEBUG_OUT(2) <= trigger_busy_o; +-- DEBUG_OUT(3) <= channel_all_done; +-- DEBUG_OUT(4) <= data_clk_o; +-- DEBUG_OUT(5) <= t_data_clk_o; +-- DEBUG_OUT(6) <= out_of_window_l; + --DEBUG_OUT(7) <= out_of_window_h; + --DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN; + --DEBUG_OUT(9) <= NX_NOMORE_DATA_IN; + --DEBUG_OUT(10) <= store_to_fifo; + DEBUG_OUT(15 downto 1) <= SLV_ADDR_IN(15 downto 1); -- Timer nx_timer_1: nx_timer @@ -178,83 +185,92 @@ begin out_of_window_l <= '0'; out_of_window_h <= '0'; ch_status_cmd_pr <= CS_NONE; + + histogram_fill_o <= '0'; + histogram_bin_o <= (others => '0'); - if (DATA_CLK_IN = '1' and store_to_fifo = '1') then - ts_ref := timestamp_ref - x"010"; - window_lower_thr := trigger_window_delay; - window_upper_thr := window_lower_thr + trigger_window_width; - deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref; - - window_lower_thr_r <= window_lower_thr; - window_upper_thr_r <= window_upper_thr; - - case readout_mode is - - when x"0" => -- RefValue + valid and window filter - if (TIMESTAMP_STATUS_IN(1) = '0') then - if (deltaT < window_lower_thr) then - out_of_window_l <= '1'; - data_clk_o <= '0'; - -- IN LUT-Data bit setzten. - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_WAIT; - elsif (deltaT > window_upper_thr) then - out_of_window_h <= '1'; - data_clk_o <= '0'; - -- In LUT-Done Bit setzten - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_DONE; - else - -- IN LUT-Data bit setzten. - channel_index <= CHANNEL_IN; - ch_status_cmd_pr <= CS_SET_WAIT; - - data_o(11 downto 0) <= deltaT; - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= '0'; + if (DATA_CLK_IN = '1') then + if (store_to_fifo = '1') then + ts_ref := timestamp_ref - x"010"; + window_lower_thr := trigger_window_delay; + window_upper_thr := window_lower_thr + trigger_window_width; + deltaT := unsigned(TIMESTAMP_IN(13 downto 2)) - ts_ref; + + window_lower_thr_r <= window_lower_thr; + window_upper_thr_r <= window_upper_thr; + + case readout_mode is + + when x"0" => -- RefValue + valid and window filter + if (TIMESTAMP_STATUS_IN(1) = '0') then + if (deltaT < window_lower_thr) then + out_of_window_l <= '1'; + data_clk_o <= '0'; + -- IN LUT-Data bit setzten. + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_WAIT; + elsif (deltaT > window_upper_thr) then + out_of_window_h <= '1'; + data_clk_o <= '0'; + -- In LUT-Done Bit setzten + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_DONE; + else + -- IN LUT-Data bit setzten. + channel_index <= CHANNEL_IN; + ch_status_cmd_pr <= CS_SET_WAIT; + + data_o(11 downto 0) <= deltaT; + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= '0'; + data_clk_o <= '1'; + end if; + end if; + + when x"1" => -- RefValue + valid filter + if (TIMESTAMP_STATUS_IN(1) = '0') then + data_o(11 downto 0) <= deltaT; + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= '0'; + data_clk_o <= '1'; + end if; + + when x"3" => -- RefValue + valid filter + if (TIMESTAMP_STATUS_IN(1) = '0') then + data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= '0'; data_clk_o <= '1'; end if; - end if; - - when x"1" => -- RefValue + valid filter - if (TIMESTAMP_STATUS_IN(1) = '0') then - data_o(11 downto 0) <= deltaT; - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= '0'; - data_clk_o <= '1'; - end if; + + when x"4" => -- RawValue + data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= '0'; + data_clk_o <= '1'; + + when x"5" => -- RawValue + valid filter + if (TIMESTAMP_STATUS_IN(1) = '0') then + data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); + data_o(23 downto 12) <= ADC_DATA_IN; + data_o(30 downto 24) <= CHANNEL_IN; + data_o(31) <= '0'; + data_clk_o <= '1'; + end if; - when x"3" => -- RefValue + valid filter - if (TIMESTAMP_STATUS_IN(1) = '0') then - data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= '0'; - data_clk_o <= '1'; - end if; - - when x"4" => -- RawValue - data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= '0'; - data_clk_o <= '1'; - - when x"5" => -- RawValue + valid filter - if (TIMESTAMP_STATUS_IN(1) = '0') then - data_o(11 downto 0) <= TIMESTAMP_IN(13 downto 2); - data_o(23 downto 12) <= ADC_DATA_IN; - data_o(30 downto 24) <= CHANNEL_IN; - data_o(31) <= '0'; - data_clk_o <= '1'; - end if; + when others => null; - when others => null; + end case; - end case; - + end if; + + -- Fill Histogram + histogram_fill_o <= '1'; + histogram_bin_o <= CHANNEL_IN; end if; end if; end if; @@ -431,6 +447,7 @@ begin -- Give status info to the TRB Slow Control Channel PROC_FIFO_REGISTERS: process(CLK_IN) + begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then @@ -492,7 +509,7 @@ begin slv_data_out_o(11 downto 0) <= window_upper_thr_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - + when x"0008" => slv_data_out_o <= std_logic_vector(channel_done(31 downto 0)); @@ -512,7 +529,7 @@ begin slv_data_out_o <= std_logic_vector(channel_done(127 downto 96)); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -544,7 +561,7 @@ begin slv_ack_o <= '0'; end case; else - slv_ack_o <= '0'; + slv_ack_o <= '0'; end if; end if; end if; @@ -558,6 +575,9 @@ begin DATA_OUT <= data_o or t_data_o; DATA_CLK_OUT <= data_clk_o or t_data_clk_o; NOMORE_DATA_OUT <= nomore_data_o; + + HISTOGRAM_FILL_OUT <= histogram_fill_o; + HISTOGRAM_BIN_OUT <= histogram_bin_o; -- Slave SLV_DATA_OUT <= slv_data_out_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 35743fa..1e00309 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -370,6 +370,8 @@ component nx_trigger_validate DATA_OUT : out std_logic_vector(31 downto 0); DATA_CLK_OUT : out std_logic; NOMORE_DATA_OUT : out std_logic; + HISTOGRAM_FILL_OUT : out std_logic; + HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -414,6 +416,28 @@ end component; ------------------------------------------------------------------------------- +component nx_histograms + generic ( + NUM_BINS : integer); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + RESET_HISTS_IN : in std_logic; + CHANNEL_STAT_FILL_IN : in std_logic; + CHANNEL_ID_IN : in std_logic_vector(NUM_BINS - 1 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0)); +end component; + +------------------------------------------------------------------------------- + component level_to_pulse port ( CLK_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 18819ee..8758144 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -97,15 +97,17 @@ architecture Behavioral of nXyter_FEE_board is -- Clock 256 signal clk_250_o : std_logic; - -- Bus Handler - signal slv_read : std_logic_vector(16-1 downto 0); - signal slv_write : std_logic_vector(16-1 downto 0); - signal slv_no_more_data : std_logic_vector(16-1 downto 0); - signal slv_ack : std_logic_vector(16-1 downto 0); - signal slv_addr : std_logic_vector(16*16-1 downto 0); - signal slv_data_rd : std_logic_vector(16*32-1 downto 0); - signal slv_data_wr : std_logic_vector(16*32-1 downto 0); - signal slv_unknown_addr : std_logic_vector(16-1 downto 0); + -- Bus Handler + constant NUM_PORTS : integer := 11; + + signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0); + signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0); + signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0); + signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); -- TRB Register signal i2c_sm_reset_o : std_logic; @@ -153,6 +155,9 @@ architecture Behavioral of nXyter_FEE_board is signal trigger_validate_busy : std_logic; signal validate_nomore_data : std_logic; + signal trigger_validate_fill : std_logic; + signal trigger_validate_bin : std_logic_vector(6 downto 0); + -- Event Buffer signal trigger_evt_busy : std_logic; signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); @@ -236,7 +241,7 @@ begin THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 10, + PORT_NUMBER => NUM_PORTS, PORT_ADDRESSES => ( 0 => x"0100", -- Control Register Handler 1 => x"0040", -- I2C Master @@ -248,7 +253,7 @@ begin 7 => x"0160", -- Trigger Handler 8 => x"0180", -- Trigger Validate 9 => x"0200", -- NX Register Setup - + 10 => x"0800", -- NX Histograms others => x"0000"), PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler @@ -261,152 +266,39 @@ begin 7 => 1, -- Trigger Handler 8 => 4, -- Trigger Validate 9 => 8, -- NX Register Setup + 10 => 8, -- NX Histograms others => 0) + + PORT_MASK_ENABLE => 1 ) port map( - CLK => CLK_IN, - RESET => RESET_IN, - - DAT_ADDR_IN => REGIO_ADDR_IN, - DAT_DATA_IN => REGIO_DATA_IN, - DAT_DATA_OUT => REGIO_DATA_OUT, - DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN, - DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN, - DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN, - DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT, - DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, - DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, - DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, - - -- Control Registers - BUS_READ_ENABLE_OUT(0) => slv_read(0), - BUS_WRITE_ENABLE_OUT(0) => slv_write(0), - BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), - BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), - BUS_ADDR_OUT(0*16+2 downto 0*16) => slv_addr(0*16+2 downto 0*16), - BUS_ADDR_OUT(0*16+15 downto 0*16+3) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATAREADY_IN(0) => slv_ack(0), - BUS_WRITE_ACK_IN(0) => slv_ack(0), - BUS_NO_MORE_DATA_IN(0) => slv_no_more_data(0), - BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0), - - -- I2C master - BUS_READ_ENABLE_OUT(1) => slv_read(1), - BUS_WRITE_ENABLE_OUT(1) => slv_write(1), - BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), - BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), - BUS_ADDR_OUT(1*16+15 downto 1*16) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATAREADY_IN(1) => slv_ack(1), - BUS_WRITE_ACK_IN(1) => slv_ack(1), - BUS_NO_MORE_DATA_IN(1) => slv_no_more_data(1), - BUS_UNKNOWN_ADDR_IN(1) => slv_unknown_addr(1), - - -- Data Receiver - BUS_READ_ENABLE_OUT(2) => slv_read(2), - BUS_WRITE_ENABLE_OUT(2) => slv_write(2), - BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), - BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+2 downto 2*16) => slv_addr(2*16+2 downto 2*16), - BUS_ADDR_OUT(2*16+15 downto 2*16+3) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATAREADY_IN(2) => slv_ack(2), - BUS_WRITE_ACK_IN(2) => slv_ack(2), - BUS_NO_MORE_DATA_IN(2) => slv_no_more_data(2), - BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2), - - -- DataBuffer - BUS_READ_ENABLE_OUT(3) => slv_read(3), - BUS_WRITE_ENABLE_OUT(3) => slv_write(3), - BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), - BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), - BUS_ADDR_OUT(3*16+2 downto 3*16) => slv_addr(3*16+2 downto 3*16), - BUS_ADDR_OUT(3*16+15 downto 3*16+3) => open, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATAREADY_IN(3) => slv_ack(3), - BUS_WRITE_ACK_IN(3) => slv_ack(3), - BUS_NO_MORE_DATA_IN(3) => slv_no_more_data(3), - BUS_UNKNOWN_ADDR_IN(3) => slv_unknown_addr(3), - - -- SPI master - BUS_READ_ENABLE_OUT(4) => slv_read(4), - BUS_WRITE_ENABLE_OUT(4) => slv_write(4), - BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), - BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), - BUS_ADDR_OUT(4*16+15 downto 4*16) => open, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATAREADY_IN(4) => slv_ack(4), - BUS_WRITE_ACK_IN(4) => slv_ack(4), - BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4), - BUS_UNKNOWN_ADDR_IN(4) => slv_unknown_addr(4), - - -- Trigger Generator - BUS_READ_ENABLE_OUT(5) => slv_read(5), - BUS_WRITE_ENABLE_OUT(5) => slv_write(5), - BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), - BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), - BUS_ADDR_OUT(5*16+2 downto 5*16) => slv_addr(5*16+2 downto 5*16), - BUS_ADDR_OUT(5*16+15 downto 5*16+3) => open, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATAREADY_IN(5) => slv_ack(5), - BUS_WRITE_ACK_IN(5) => slv_ack(5), - BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5), - BUS_UNKNOWN_ADDR_IN(5) => slv_unknown_addr(5), - - -- Data Validate - BUS_READ_ENABLE_OUT(6) => slv_read(6), - BUS_WRITE_ENABLE_OUT(6) => slv_write(6), - BUS_DATA_OUT(6*32+31 downto 6*32) => slv_data_wr(6*32+31 downto 6*32), - BUS_DATA_IN(6*32+31 downto 6*32) => slv_data_rd(6*32+31 downto 6*32), - BUS_ADDR_OUT(6*16+4 downto 6*16) => slv_addr(6*16+4 downto 6*16), - BUS_ADDR_OUT(6*16+15 downto 6*16+5) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATAREADY_IN(6) => slv_ack(6), - BUS_WRITE_ACK_IN(6) => slv_ack(6), - BUS_NO_MORE_DATA_IN(6) => slv_no_more_data(6), - BUS_UNKNOWN_ADDR_IN(6) => slv_unknown_addr(6), - - -- Trigger Handler - BUS_READ_ENABLE_OUT(7) => slv_read(7), - BUS_WRITE_ENABLE_OUT(7) => slv_write(7), - BUS_DATA_OUT(7*32+31 downto 7*32) => slv_data_wr(7*32+31 downto 7*32), - BUS_DATA_IN(7*32+31 downto 7*32) => slv_data_rd(7*32+31 downto 7*32), - BUS_ADDR_OUT(7*16+0) => slv_addr(7*16+0), - BUS_ADDR_OUT(7*16+15 downto 7*16+1) => open, - BUS_TIMEOUT_OUT(7) => open, - BUS_DATAREADY_IN(7) => slv_ack(7), - BUS_WRITE_ACK_IN(7) => slv_ack(7), - BUS_NO_MORE_DATA_IN(7) => slv_no_more_data(7), - BUS_UNKNOWN_ADDR_IN(7) => slv_unknown_addr(7), - - -- Timestamp Process - BUS_READ_ENABLE_OUT(8) => slv_read(8), - BUS_WRITE_ENABLE_OUT(8) => slv_write(8), - BUS_DATA_OUT(8*32+31 downto 8*32) => slv_data_wr(8*32+31 downto 8*32), - BUS_DATA_IN(8*32+31 downto 8*32) => slv_data_rd(8*32+31 downto 8*32), - BUS_ADDR_OUT(8*16+3 downto 8*16) => slv_addr(8*16+3 downto 8*16), - BUS_ADDR_OUT(8*16+15 downto 8*16+4) => open, - BUS_TIMEOUT_OUT(8) => open, - BUS_DATAREADY_IN(8) => slv_ack(8), - BUS_WRITE_ACK_IN(8) => slv_ack(8), - BUS_NO_MORE_DATA_IN(8) => slv_no_more_data(8), - BUS_UNKNOWN_ADDR_IN(8) => slv_unknown_addr(8), - - -- NX Register Setup - BUS_READ_ENABLE_OUT(9) => slv_read(9), - BUS_WRITE_ENABLE_OUT(9) => slv_write(9), - BUS_DATA_OUT(9*32+31 downto 9*32) => slv_data_wr(9*32+31 downto 9*32), - BUS_DATA_IN(9*32+31 downto 9*32) => slv_data_rd(9*32+31 downto 9*32), - BUS_ADDR_OUT(9*16+7 downto 9*16) => slv_addr(9*16+7 downto 9*16), - BUS_ADDR_OUT(9*16+15 downto 9*16+5) => open, - BUS_TIMEOUT_OUT(9) => open, - BUS_DATAREADY_IN(9) => slv_ack(9), - BUS_WRITE_ACK_IN(9) => slv_ack(9), - BUS_NO_MORE_DATA_IN(9) => slv_no_more_data(9), - BUS_UNKNOWN_ADDR_IN(9) => slv_unknown_addr(9), - - ---- debug + CLK => CLK_IN, + RESET => RESET_IN, + + DAT_ADDR_IN => REGIO_ADDR_IN, + DAT_DATA_IN => REGIO_DATA_IN, + DAT_DATA_OUT => REGIO_DATA_OUT, + DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN, + DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN, + DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN, + DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT, + DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, + DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, + DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, + + -- Control Registers + BUS_READ_ENABLE_OUT => slv_read, + BUS_WRITE_ENABLE_OUT => slv_write, + BUS_DATA_OUT => slv_data_wr, + BUS_DATA_IN => slv_data_rd, + BUS_ADDR_OUT => slv_addr, + BUS_TIMEOUT_OUT => open, + BUS_DATAREADY_IN => slv_ack, + BUS_WRITE_ACK_IN => slv_ack, + BUS_NO_MORE_DATA_IN => slv_no_more_data, + BUS_UNKNOWN_ADDR_IN => slv_unknown_addr, + + -- DEBUG STAT_DEBUG => open ); @@ -708,6 +600,9 @@ begin DATA_CLK_OUT => trigger_data_clk, NOMORE_DATA_OUT => validate_nomore_data, + HISTOGRAM_FILL_OUT => trigger_validate_fill, + HISTOGRAM_BIN_OUT => trigger_validate_bin, + SLV_READ_IN => slv_read(8), SLV_WRITE_IN => slv_write(8), SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), @@ -760,6 +655,31 @@ begin DEBUG_OUT => open ); + nx_histograms_1: nx_histograms + generic map ( + NUM_BINS => 7 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + + RESET_HISTS_IN => open, + CHANNEL_STAT_FILL_IN => trigger_validate_fill, + CHANNEL_ID_IN => trigger_validate_bin, + + SLV_READ_IN => slv_read(10), + SLV_WRITE_IN => slv_write(10), + SLV_DATA_OUT => slv_data_rd(10*32+31 downto 10*32), + SLV_DATA_IN => slv_data_wr(10*32+31 downto 10*32), + SLV_ADDR_IN => slv_addr(10*16+15 downto 10*16), + SLV_ACK_OUT => slv_ack(10), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(10), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(10), + + --DEBUG_OUT => DEBUG_LINE_OUT + DEBUG_OUT => open + ); + ------------------------------------------------------------------------------- -- nXyter Signals ------------------------------------------------------------------------------- @@ -767,12 +687,6 @@ begin NX_RESET_OUT <= not nx_ts_reset_o; NX_TESTPULSE_OUT <= nx_testpulse_o; -------------------------------------------------------------------------------- --- ADC Signals -------------------------------------------------------------------------------- - - - ------------------------------------------------------------------------------- -- I2C Signals ------------------------------------------------------------------------------- diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index e541779..8c5e9a0 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -48,13 +48,15 @@ w: clear Resync Counter 0x8503 : r/w r: Parity Error Counter (12bit) w: clear Parity Error Counter -0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6Bit, in 31.25ns, range 2..60) default: 8 +0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6Bit, in 31.25ns, range 2..60) + default: 8 0x8505 : r/w ADC CLK Delay 4ns steps (3Bit: range 0..7) 0: 4ns after frame_valid 1: 8ns -------"--------- ...... -------"--------- 6: 28ns -------"--------- - 7: 32ns -------"--------- <= this shoud be correct i.e. 2ns before new frame clock + 7: 32ns -------"--------- <= this shoud be correct + i.e. 2ns before new frame clock 0x8506 : r current ADC FIFO value -- Event Data Buffer @@ -69,5 +71,3 @@ -- SPI Master 0x8060 : Access to SPI Interface - - diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index fc0e527..149adbf 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -167,6 +167,7 @@ add_file -vhdl -lib "work" "source/nx_event_buffer.vhd" add_file -vhdl -lib "work" "source/nxyter_registers.vhd" add_file -vhdl -lib "work" "source/nx_setup.vhd" +add_file -vhdl -lib "work" "source/nx_histograms.vhd" add_file -vhdl -lib "work" "source/nx_i2c_master.vhd" add_file -vhdl -lib "work" "source/nx_i2c_startstop.vhd" -- 2.43.0