From 87e6bb33d7a93e16571b938b478fdae04403955a Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 17 Nov 2017 15:33:24 +0100 Subject: [PATCH] Update TRB3sc CTS with TDC and timestamp generator --- cts/config.vhd | 67 +++++++---- cts/config_compile_frankfurt.pl | 6 +- cts/par.p2t | 48 +++++--- cts/trb3sc_cts.prj | 32 ++++- cts/trb3sc_cts.vhd | 206 +++++++++++++++++++------------- scripts/nodes_cts_frankfurt.txt | 13 ++ 6 files changed, 241 insertions(+), 131 deletions(-) create mode 100644 scripts/nodes_cts_frankfurt.txt diff --git a/cts/config.vhd b/cts/config.vhd index b428079..8a4c63b 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -36,6 +36,7 @@ package config is constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; --input monitor and trigger generation logic + constant INCLUDE_TDC : integer := c_YES; constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 0; @@ -43,18 +44,25 @@ package config is constant MONITOR_INPUT_NUM : integer := 32; - constant INCLUDE_TDC : integer range c_NO to c_YES := c_YES; - constant TDC_CHANNEL_NUMBER : integer := 9; - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 - -- 0: single edge only, - -- 1: same channel, - -- 2: alternating channels, - -- 3: same channel with stretcher - constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 - --ring buffer size: 32,64,96,128,dyn + constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 + constant PINOUT : integer := 2; + -- 0: KEL on board + -- 1: Canadian + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file + --ring buffer size: 32,64,96,128,dyn + constant TDC_DATA_FORMAT : integer := 0; + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed - - constant GEN_BUSY_OUTPUT : integer := c_NO; constant TRIGGER_COIN_COUNT : integer := 1; @@ -66,13 +74,13 @@ package config is constant CTS_OUTPUT_MULTIPLEXERS : integer := 1; --TODO: -- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO; --- constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO; --Which external trigger module (ETM) to use? -- constant INCLUDE_ETM : integer range c_NO to c_YES := c_NO; -- type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); -- constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM; -- constant ETM_ID : std_logic_vector(7 downto 0); + constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_YES; @@ -106,23 +114,27 @@ package config is -- 2(10) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only --Order: + -- no backplane, no AddOn, 1x SFP, 1x GBE -- no backplane, 4x AddOn, 1x SFP, 1x GBE - -- no backplane, 8x AddOn, 1x SFP, 1x GBE +-- -- -- -- no backplane, 8x AddOn, 1x SFP, 1x GBE -- backplane, 9x backplane, 1x GBE - - constant INTERFACE_NUM_ARR : hub_mii_t := (5,9,10,0); + constant SFP_NUM_ARR : hub_mii_t := (1,5,0,0); + constant INTERFACE_NUM_ARR : hub_mii_t := (1,5,9,10); -- 0 1 2 3 4 5 6 7 8 9 a b c d e f - constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); - constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), - (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0), - (1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), +-- (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); - constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), +-- (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)); constant INTERFACE_NUM : integer; @@ -133,7 +145,7 @@ package config is ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - constant cts_rdo_additional_ports : integer := 1; + constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR; --for TDC constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; @@ -183,9 +195,14 @@ function generateIncludedFeatures return std_logic_vector is begin t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + t(3 downto 0) := x"0"; --std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC + t(16 downto 16) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --data via GbE t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --- t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet + t(26 downto 24) := std_logic_vector(to_unsigned(SFP_NUM_ARR(CFG_MODE),3)); --num SFPs with TrbNet t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); diff --git a/cts/config_compile_frankfurt.pl b/cts/config_compile_frankfurt.pl index e246d69..01ea7d8 100644 --- a/cts/config_compile_frankfurt.pl +++ b/cts/config_compile_frankfurt.pl @@ -6,14 +6,14 @@ synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', #synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", -nodelist_file => 'nodelist_frankfurt.txt', +nodelist_file => 'nodes_cts_frankfurt.txt', pinout_file => 'trb3sc_hub', #Include only necessary lpf files #pinout_file => '', #name of pin-out file, if not equal TOPNAME -include_TDC => 0, -include_GBE => 0, +include_TDC => 1, +include_GBE => 1, #Report settings firefox_open => 0, diff --git a/cts/par.p2t b/cts/par.p2t index e13de7d..2be9006 100644 --- a/cts/par.p2t +++ b/cts/par.p2t @@ -1,21 +1,31 @@ --w --i 15 --l 5 --n 1 --y --s 12 --t 25 --c 1 --e 2 -#-g guidefile.ncd -#-m nodelist.txt # -w -# -i 6 +# -i 15 # -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 +# -y +# -s 12 +# -t 26 +# -c 1 +# -e 2 +# #-g guidefile.ncd +# #-m nodelist.txt +# # -w +# # -i 6 +# # -l 5 +# # -n 1 +# # -t 1 +# # -s 1 +# # -c 0 +# # -e 0 +# # +# +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 3 +-c 0 +-e 0 +-i 6 +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:parHold=ON:parHoldLimit=10000:parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1:parHold=2 diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index f320377..320b823 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -77,7 +77,7 @@ add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" - +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" @@ -265,6 +265,36 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" +#TDC +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_version.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Channel.vhd" +# add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Encoder_304_Bit.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ROM_encoder_ecp3.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "../../trb3sc/tdc_release/up_counter.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd" add_file -vhdl -lib work "./trb3sc_cts.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 2b5ebda..8f06f06 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -110,7 +110,7 @@ architecture trb3sc_arch of trb3sc_cts is - signal clk_sys, clk_full, clk_full_osc : std_logic; + signal clk_sys, clk_full, clk_full_osc, clk_cal : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; @@ -125,9 +125,9 @@ architecture trb3sc_arch of trb3sc_cts is signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, buscts_rx, - bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bustdc_rx : CTRLBUS_RX; signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, buscts_tx, - bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bustdc_tx : CTRLBUS_TX; signal sed_error_i : std_logic; signal bus_master_active : std_logic; @@ -137,8 +137,7 @@ architecture trb3sc_arch of trb3sc_cts is signal common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0); - signal my_address : std_logic_vector(15 downto 0); - signal mc_unique_id : std_logic_vector(63 downto 0); + signal timer : TIMERS; signal reset_via_gbe : std_logic := '0'; signal med_dataready_out : std_logic_vector (5-1 downto 0); @@ -154,7 +153,6 @@ architecture trb3sc_arch of trb3sc_cts is signal rdack, wrack : std_logic; signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); - signal timer_ticks : std_logic_vector(1 downto 0); signal trigger_busy_i : std_logic; signal cts_trigger_out : std_logic; @@ -176,15 +174,8 @@ architecture trb3sc_arch of trb3sc_cts is signal gsc_init_dataready, gsc_reply_dataready : std_logic; signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); signal gsc_busy : std_logic; - - signal cts_rdo_trigger : std_logic; - signal cts_rdo_trg_data_valid : std_logic; - signal cts_rdo_valid_timing_trg : std_logic; - signal cts_rdo_valid_notiming_trg : std_logic; - signal cts_rdo_invalid_trg : std_logic; - - signal cts_rdo_trg_status_bits, - cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); + + signal cts_rdo_trg_status_bits_cts : std_logic_vector(31 downto 0) := (others => '0'); signal cts_rdo_data : std_logic_vector(31 downto 0); signal cts_rdo_write : std_logic; signal cts_rdo_finished : std_logic; @@ -201,11 +192,7 @@ architecture trb3sc_arch of trb3sc_cts is signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); signal cts_rdo_additional : readout_tx_array_t(0 to cts_rdo_additional_ports-1); - - signal cts_rdo_trg_type : std_logic_vector(3 downto 0); - signal cts_rdo_trg_code : std_logic_vector(7 downto 0); - signal cts_rdo_trg_information : std_logic_vector(23 downto 0); - signal cts_rdo_trg_number : std_logic_vector(15 downto 0); + signal cts_rdo_rx : READOUT_RX; signal cts_addon_triggers_in : std_logic_vector(ADDON_LINE_COUNT-1 downto 0); -- signal cts_addon_activity_i, @@ -234,6 +221,8 @@ architecture trb3sc_arch of trb3sc_cts is signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + signal hit_in_i : std_logic_vector(64 downto 1); + attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; attribute syn_keep of bussci1_rx : signal is true; @@ -281,14 +270,22 @@ THE_CLOCK_RESET : entity work.clock_reset_handler reset_via_gbe_long <= '1'; reset_via_gbe_timer <= '1'; end if; - if timer_ticks(0) = '1' then + if timer.tick_us = '1' then reset_via_gbe_timer <= '0'; reset_via_gbe_long <= reset_via_gbe_timer; end if; last_reset_via_gbe_long <= reset_via_gbe_long; make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; end process; - + + + pll_calibration : entity work.pll_in125_out33 + port map ( + CLK => CLK_SUPPL_PCLK, + CLKOP => clk_cal, + LOCK => open); + + --------------------------------------------------------------------------- -- PCSA --------------------------------------------------------------------------- @@ -301,7 +298,7 @@ bussci1_tx.unknown <= '1'; --------------------------------------------------------------------------- -- PCSB Downlink without backplane is SFP --------------------------------------------------------------------------- -gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate +gen_PCSB : if USE_BACKPLANE = c_NO generate THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync generic map( SERDES_NUM => 3, @@ -343,7 +340,7 @@ end generate; -- bussci3_tx.ack <= '0'; -- bussci3_tx.nack <= '0'; -- bussci3_tx.unknown <= '1'; -gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate +gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4 generic map( IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), @@ -434,7 +431,7 @@ end generate; RESET => reset_i, GSR_N => GSR_N, - TRIGGER_IN => cts_rdo_trg_data_valid, + TRIGGER_IN => cts_rdo_rx.data_valid, SD_PRSNT_N_IN(0) => SFP_MOD0(0), SD_LOS_IN(0) => SFP_LOS(0), @@ -457,8 +454,8 @@ end generate; FEE_STATUS_BITS_IN => gbe_fee_status_bits, FEE_BUSY_IN => gbe_fee_busy, - MC_UNIQUE_ID_IN => mc_unique_id, - MY_TRBNET_ADDRESS_IN => my_address, + MC_UNIQUE_ID_IN => timer.uid, + MY_TRBNET_ADDRESS_IN => timer.network_address, ISSUE_REBOOT_OUT => reboot_from_gbe, GSC_CLK_IN => clk_sys, @@ -494,14 +491,15 @@ end generate; MII_IS_DOWNLINK => IS_DOWNLINK, MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, INIT_ENDPOINT_ID => x"0001", BROADCAST_BITMASK => x"7E", CLOCK_FREQUENCY => 100, USE_ONEWIRE => c_YES, BROADCAST_SPECIAL_ADDR => x"35", RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, - RDO_DATA_BUFFER_DEPTH => 10, - RDO_DATA_BUFFER_FULL_THRESH => 2**9+2, + RDO_DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + RDO_DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, RDO_HEADER_BUFFER_DEPTH => 9, RDO_HEADER_BUFFER_FULL_THRESH => 2**9-16 ) @@ -511,16 +509,16 @@ end generate; CLK_EN => '1', -- Media interfacces --------------------------------------------------------------- - MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out, - MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out, - MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out, - MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in, - MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in, - MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in, - MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in, - MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out, - MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op, - MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op, + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), -- Gbe Read-out Path --------------------------------------------------------------- --Event information coming from CTS for GbE @@ -561,14 +559,14 @@ end generate; -- CTS Data Readout ---------------------------------------------------------------- --Trigger to CTS out RDO_TRIGGER_IN => cts_trigger_out, - RDO_TRG_DATA_VALID_OUT => cts_rdo_trg_data_valid, - RDO_VALID_TIMING_TRG_OUT => cts_rdo_valid_timing_trg, - RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_valid_notiming_trg, - RDO_INVALID_TRG_OUT => cts_rdo_invalid_trg, - RDO_TRG_TYPE_OUT => cts_rdo_trg_type, - RDO_TRG_CODE_OUT => cts_rdo_trg_code, - RDO_TRG_INFORMATION_OUT => cts_rdo_trg_information, - RDO_TRG_NUMBER_OUT => cts_rdo_trg_number, + RDO_TRG_DATA_VALID_OUT => cts_rdo_rx.data_valid, + RDO_VALID_TIMING_TRG_OUT => cts_rdo_rx.valid_timing_trg, + RDO_VALID_NOTIMING_TRG_OUT => cts_rdo_rx.valid_notiming_trg, + RDO_INVALID_TRG_OUT => cts_rdo_rx.invalid_trg, + RDO_TRG_TYPE_OUT => cts_rdo_rx.trg_type, + RDO_TRG_CODE_OUT => cts_rdo_rx.trg_code, + RDO_TRG_INFORMATION_OUT => cts_rdo_rx.trg_information, + RDO_TRG_NUMBER_OUT => cts_rdo_rx.trg_number, --Data from CTS in RDO_TRG_STATUSBITS_IN => cts_rdo_trg_status_bits_cts, @@ -586,9 +584,11 @@ end generate; COMMON_CTRL_REGS => common_ctrl_reg, ONEWIRE => TEMPSENS, ONEWIRE_MONITOR_IN => open, - MY_ADDRESS_OUT => my_address, - UNIQUE_ID_OUT => mc_unique_id, - TIMER_TICKS_OUT => timer_ticks, + MY_ADDRESS_OUT => timer.network_address, + UNIQUE_ID_OUT => timer.uid, + TIMER_TICKS_OUT(0) => timer.tick_us, + TIMER_TICKS_OUT(1) => timer.tick_ms, + TEMPERATURE_OUT => timer.temperature, EXTERNAL_SEND_RESET => reset_via_gbe, REGIO_ADDR_OUT => ctrlbus_rx.addr, @@ -630,14 +630,11 @@ end generate; cts_rdo_additional_data(31 + i*32 downto 32*i) <= cts_rdo_additional(i).data; cts_rdo_trg_status_bits_additional(31 + i*32 downto 32*i) <= cts_rdo_additional(i).statusbits; --- cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; --- cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; - cts_rdo_additional_write(i) <= '0'; - cts_rdo_additional_finished(i) <= '1'; + cts_rdo_additional_write(i) <= cts_rdo_additional(i).data_write; + cts_rdo_additional_finished(i) <= cts_rdo_additional(i).data_finished; end generate; - gen_media_record : for i in 0 to INTERFACE_NUM-1 generate med_data_in(i*16+15 downto i*16) <= med2int(i).data; med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; @@ -660,19 +657,7 @@ end generate; THE_CTS : CTS generic map ( EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic - --- TRIGGER_COIN_COUNT => TRIGGER_COIN_COUNT, --- TRIGGER_PULSER_COUNT => TRIGGER_PULSER_COUNT, --- TRIGGER_RAND_PULSER => TRIGGER_RAND_PULSER, - --- TRIGGER_INPUT_COUNT => 0, -- obsolete! now all inputs are routed via an input multiplexer! --- TRIGGER_ADDON_COUNT => TRIGGER_ADDON_COUNT, - --- PERIPH_TRIGGER_COUNT => PERIPH_TRIGGER_COUNT, - OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS, - --- ADDON_LINE_COUNT => CTS_ADDON_LINE_COUNT, ADDON_GROUPS => 2, ADDON_GROUP_UPPER => (1,17, others => 0) ) @@ -722,10 +707,10 @@ end generate; CTS_REGIO_WRITE_ACK_OUT => buscts_tx.wack, CTS_REGIO_UNKNOWN_ADDR_OUT => buscts_tx.unknown, - LVL1_TRG_DATA_VALID_IN => cts_rdo_trg_data_valid, - LVL1_VALID_TIMING_TRG_IN => cts_rdo_valid_timing_trg, - LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_valid_notiming_trg, - LVL1_INVALID_TRG_IN => cts_rdo_invalid_trg, + LVL1_TRG_DATA_VALID_IN => cts_rdo_rx.data_valid, + LVL1_VALID_TIMING_TRG_IN => cts_rdo_rx.valid_timing_trg, + LVL1_VALID_NOTIMING_TRG_IN => cts_rdo_rx.valid_notiming_trg, + LVL1_INVALID_TRG_IN => cts_rdo_rx.invalid_trg, FEE_TRG_STATUSBITS_OUT => cts_rdo_trg_status_bits_cts, FEE_DATA_OUT => cts_rdo_data, @@ -740,19 +725,32 @@ end generate; buscts_tx.ack <= '0'; --------------------------------------------------------------------------- --- TDC +-- Add timestamp generator --------------------------------------------------------------------------- - - - + GEN_TIMESTAMP : if INCLUDE_TIMESTAMP_GENERATOR = c_YES generate + THE_TIMESTAMP : entity work.timestamp_generator + port map( + CLK => clk_sys, + RESET_IN => reset_i, + + TIMER_CLOCK_IN => INP(80), + TIMER_RESET_IN => INP(81), + + TRIGGER_IN => cts_trigger_out, + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(0) + ); + end generate; + + --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 8, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, others => 0), + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"8100", 6 => x"8300", 7 => x"a000", 8 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 8, 6 => 8, 7 => 11, 8 => 12, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -770,6 +768,7 @@ end generate; BUS_RX(5) => busgbeip_rx, BUS_RX(6) => busgbereg_rx, BUS_RX(7) => buscts_rx, + BUS_RX(8) => bustdc_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bustc_tx, BUS_TX(2) => bussci1_tx, @@ -778,6 +777,7 @@ end generate; BUS_TX(5) => busgbeip_tx, BUS_TX(6) => busgbereg_tx, BUS_TX(7) => buscts_tx, + BUS_TX(8) => bustdc_tx, STAT_DEBUG => open ); @@ -866,11 +866,12 @@ end generate; LED_YELLOW <= debug_clock_reset(2); - -gen_hub_leds : for i in 1 to 4 generate - LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); - LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); - LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); +gen_leds_addon : if USE_ADDON = c_YES generate + gen_hub_leds : for i in 1 to 4 generate + LED_HUB_LINKOK(i) <= not med2int(i).stat_op(9); + LED_HUB_TX(i) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); + LED_HUB_RX(i) <= not (med2int(i).stat_op(11)); + end generate; end generate; -- LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else @@ -896,6 +897,45 @@ end generate; -- not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else -- '1'; +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Dubug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2+64 downto 64); + end generate; + + -- For ToT Measurements + gen_double : if DOUBLE_EDGE_TYPE = 2 generate + Gen_Hit_In_Signals : for i in 0 to NUM_TDC_CHANNELS-2 generate + hit_in_i(i*2+1) <= INP(i+64); + hit_in_i(i*2+2) <= not INP(i+64); + end generate Gen_Hit_In_Signals; + end generate; end architecture; diff --git a/scripts/nodes_cts_frankfurt.txt b/scripts/nodes_cts_frankfurt.txt new file mode 100644 index 0000000..7231fd5 --- /dev/null +++ b/scripts/nodes_cts_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc29] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/trb3sc/cts/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 7 +ENV = /d/jspc29/lattice/39_settings.sh +WORKDIR = /d/jspc22/trb/git/trb3sc/cts/workdir -- 2.43.0