From 8800afcee619a9672302d41c6160bd09f86a4e17 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 13 Mar 2015 14:33:04 +0100 Subject: [PATCH] fixed to use internal trigger source for CTS --- base/code/clock_switch.vhd | 6 +++++- cts/trb3_central.p2t | 4 ++-- cts/trb3_central.prj | 2 +- cts/trb3_central.vhd | 5 +++-- cts/trb3_central_constraints_3.lpf | 2 ++ 5 files changed, 13 insertions(+), 6 deletions(-) diff --git a/base/code/clock_switch.vhd b/base/code/clock_switch.vhd index 06fd622..a385546 100644 --- a/base/code/clock_switch.vhd +++ b/base/code/clock_switch.vhd @@ -8,6 +8,9 @@ library work; use work.config.all; entity clock_switch is + generic( + DEFAULT_INTERNAL_TRIGGER : integer := c_NO + ); port ( INT_CLK_IN : in std_logic; -- dont care which clock SYS_CLK_IN : in std_logic; @@ -30,13 +33,14 @@ end entity; architecture clock_switch_arch of clock_switch is constant USE_EXTERNAL_CLOCK_std : std_logic := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1))(0); + constant DEFAULT_INTERNAL_TRIGGER_std : std_logic := std_logic_vector(to_unsigned(DEFAULT_INTERNAL_TRIGGER,1))(0); type INT_FSM_STATES_T is (WAIT_FOR_LOCK, WAIT_PLL_STABLE, OPERATING); signal int_fsm_i : INT_FSM_STATES_T := WAIT_FOR_LOCK; signal int_fsm_code_i : std_logic_vector(3 downto 0); signal select_tc : std_logic_vector(7 downto 0); - signal select_trg : std_logic; + signal select_trg : std_logic := DEFAULT_INTERNAL_TRIGGER_std; signal select_clk : std_logic := USE_EXTERNAL_CLOCK_std; -- signal select_clk_sys : std_logic := USE_EXTERNAL_CLOCK_std; signal select_clk_qsys : std_logic; diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t index b3a6824..123a34b 100644 --- a/cts/trb3_central.p2t +++ b/cts/trb3_central.p2t @@ -4,11 +4,11 @@ -n 1 -y -s 15 --t 19 +-t 18 -c 1 -e 2 #-g guidefile.ncd --m nodelist.txt +#-m nodelist.txt # -w # -i 6 # -l 5 diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index f9fd526..4a98f6b 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -60,7 +60,7 @@ impl -active "workdir" #################### -add_file -fpga_constraint "./trb3_central_syn.fdc" +#add_file -fpga_constraint "./trb3_central_syn.fdc" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index c629048..e902e4b 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -1712,8 +1712,6 @@ begin esb_data_ready <= '0'; fwb_data_ready <= '0'; hitreg_data_ready <= '0'; - - process begin wait until rising_edge(clk_100_i); srb_invalid <= srb_read_en or srb_write_en; @@ -1755,6 +1753,9 @@ begin -- CLK_MNGR2_USER <= select_tc_i(27 downto 24); THE_CLOCK_SWITCH: entity work.clock_switch + generic map( + DEFAULT_INTERNAL_TRIGGER => c_YES + ) port map( INT_CLK_IN => CLK_GPLL_RIGHT, SYS_CLK_IN => clk_100_i, diff --git a/cts/trb3_central_constraints_3.lpf b/cts/trb3_central_constraints_3.lpf index b703e58..57435d2 100644 --- a/cts/trb3_central_constraints_3.lpf +++ b/cts/trb3_central_constraints_3.lpf @@ -52,6 +52,8 @@ LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" UGROUP "THE_RESET_HANDLER_GRP" BLKNAME THE_RESET_HANDLER; MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30.000000 ns ; + #MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; #REGION "MEDIA_UPLINK" "R100C115D" 20 60 DEVSIZE; -- 2.43.0