From 8816233de853319fc83bca4c49f8e973a2d8dbcf Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 20 Jul 2009 13:48:14 +0000 Subject: [PATCH] *** empty log message *** --- mdc_oepb.vhd | 72 ++++++++++++---------------------------------------- 1 file changed, 16 insertions(+), 56 deletions(-) diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index 8ccf201..f3f98cd 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -155,8 +155,9 @@ architecture mdc_oepb_arch of mdc_oepb is signal direction_data_line_out_i : std_logic_vector(3 downto 0); signal motherboard_type_in_i : std_logic_vector(3 downto 0); signal pulse_begin_run_trigger_i : std_logic; + signal data_type_select_in_i : std_logic_vector(19 downto 0); - + signal datbus_data_out : std_logic_vector(31 downto 0); signal datbus_addr_out : std_logic_vector(15 downto 0); signal datbus_timeout_out : std_logic; @@ -166,7 +167,7 @@ architecture mdc_oepb_arch of mdc_oepb is signal reset_counter_led : std_logic; signal counter: std_logic_vector (3 downto 0); signal test_pseudo_signal_i : std_logic; - + begin --------------------------------------------------------------------- @@ -190,7 +191,7 @@ begin reset_counter <= x"000F00"; reset_internal <= '1'; reset_startup <= '1'; - elsif MED_STAT_OP(14) = '1' then --MED_STAT_OP(14) = '1' then + elsif MED_STAT_OP(14) = '1' then reset_counter <= x"000F00"; reset_startup <= '0'; reset_internal <= '1'; @@ -225,6 +226,7 @@ begin --set to 0 for unused ctrl registers to save resources REGIO_USED_CTRL_REGS => (others => '1'), REGIO_USED_CTRL_BITMASK => (others => '1'), + ADDRESS_MASK => x"FEFF", BROADCAST_BITMASK => x"FD", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), CLOCK_FREQUENCY => 100 @@ -381,55 +383,6 @@ THE_REG_DAT_ADDR : process(CLK_100) end if; end process; --- --- THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) --- begin --- if rising_edge(CLK_100) then --- REGIO_WRITE_ACK_IN <= '0'; --- REGIO_NO_MORE_DATA_IN <= '0'; --- REGIO_DATAREADY_IN <= '0'; --- REGIO_DATA_IN <= (others => '0'); --- REGIO_UNKNOWN_ADDR_IN <= '0'; --- --adc --- adc_read <= '0'; --- adc_write <= '0'; --- adc_data_in <= REGIO_DATA_OUT; --- adc_addr <= REGIO_ADDR_OUT(5 downto 0); --- adc_timeout <= REGIO_TIMEOUT_OUT; --- --- --configuration memory --- thresh_mem_data <= REGIO_DATA_OUT(15 downto 0); --- thresh_mem_addr <= REGIO_ADDR_OUT(8 downto 0);--(6 downto 0); --- thresh_mem_write <= '0'; --- thresh_mem_read <= '0'; --- --- --FEE control register --- if reg_REGIO_ADDR(15 downto 12) = x"A" then --- thresh_mem_write <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE; --- thresh_mem_read <= reg_REGIO_READ; --- REGIO_DATA_IN(15 downto 0) <= thresh_mem_data_out; --- REGIO_DATA_IN(31 downto 16)<= (others => '0'); --- REGIO_UNKNOWN_ADDR_IN <= '0'; --- REGIO_NO_MORE_DATA_IN <= '0'; --- REGIO_WRITE_ACK_IN <= reg_REGIO_WRITE; --- REGIO_DATAREADY_IN <= very_last_reg_REGIO_READ; --- --- elsif reg_REGIO_ADDR(15 downto 8) = x"80" then --- REGIO_DATA_IN <= adc_data_out; --- REGIO_DATAREADY_IN <= adc_dataready; --- REGIO_NO_MORE_DATA_IN <= adc_no_more_data; --- REGIO_WRITE_ACK_IN <= adc_write_ack; --- REGIO_UNKNOWN_ADDR_IN <= adc_unknown_addr; --- adc_write <= reg_REGIO_WRITE; --- adc_read <= reg_REGIO_READ; --- --- else --- REGIO_UNKNOWN_ADDR_IN <= reg_REGIO_READ or reg_REGIO_WRITE; --- end if; --- end if; --- end process; - - THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => 2, @@ -550,7 +503,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler -- 0xc0 0x0000 -> select verbose mode data -- 0xc0 0x1000 -> select compact mode data -- 0xc0 0x2000 -> select test data - + PROC_GEN_TIMING : process(CLK_100) begin if rising_edge(CLK_100) then @@ -566,7 +519,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler ENABLE_CLK_IN => '1', SIGNAL_IN => REGIO_COMMON_CTRL_REG_OUT(16), PULSE_OUT => pulse_pseudo_timing_trigger); - + PULSE_BEGRUN_TRIGGER : edge_to_pulse port map ( CLOCK => CLK_100, @@ -574,7 +527,10 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler SIGNAL_IN => REGIO_REGISTERS_OUT(0), PULSE_OUT => pulse_begin_run_trigger_i); - THE_TRIG_DISTR : trigger_distributor + test_pseudo_signal_i <= (pulse_pseudo_timing_trigger and LVL1_TRG_RELEASE_IN) + when (debug_trigger_distributor_i(3 downto 0) = x"1") else '0'; + + THE_TRIG_DISTR : trigger_distributor port map ( CLK => CLK_100, RESET => reset_internal, @@ -760,7 +716,11 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler --------------------------------------------------------------------- -- List of debugging signals --------------------------------------------------------------------- --- + +-- TAD(0) <= CLK; +-- TAD(8 downto 1) <= MED_STAT_DEBUG(39 downto 32); + + -- STAT_OP(2 downto 0) <= med_error; -- STAT_OP(8 downto 3) <= (others => '0'); -- STAT_OP(9) <= link_led; -- 2.43.0