From 8836a7f23b494a46ad1db46f11cc2b59ee742446 Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Wed, 10 Jan 2024 23:56:30 +0100 Subject: [PATCH] compiles without timing errors --- vldb/code/gbt_core.vhd | 77 ++++++++++++++++++++++---------- vldb/config_compile_frankfurt.pl | 2 +- vldb/par.p2t | 2 +- vldb/trb5sc_mimosis.vhd | 8 ++-- 4 files changed, 60 insertions(+), 29 deletions(-) diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 26782a1..d87fefc 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -10,6 +10,7 @@ entity gbt_core is port( CLK_SYS : in std_logic; CLK : in std_logic; + CLK_80 : in std_logic; RESET : in std_logic; BUS_RX : in CTRLBUS_RX; @@ -61,6 +62,9 @@ architecture arch of gbt_core is begin + gbtsc_tx_clk_en <= '1'; + gbtsc_rx_clk_en <= '1'; + THE_GBTSC_TOP : entity work.gbtsc_top generic map( -- IC configuration @@ -137,18 +141,18 @@ begin -- shift signals to the next high enable PROC_SHIFT_TX_EN : process - variable reg_res : std_logic_vector(1 downto 0) := "00"; - variable reg_con : std_logic_vector(1 downto 0) := "00"; - variable reg_cmd : std_logic_vector(1 downto 0) := "00"; - begin - wait until rising_edge(CLK); - reg_res := reg_res(0) & gbtsc_start_reset_cmd_raw; - reg_con := reg_con(0) & gbtsc_start_connect_cmd_raw; - reg_cmd := reg_cmd(0) & gbtsc_start_command_raw; - gbtsc_start_reset_cmd_i <= (reg_res(0) and not gbtsc_tx_clk_en ) or (reg_res(1) and not gbtsc_tx_clk_en); - gbtsc_start_connect_cmd_i <= (reg_con(0) and not gbtsc_tx_clk_en ) or (reg_con(1) and not gbtsc_tx_clk_en); - gbtsc_start_command_i <= (reg_cmd(0) and not gbtsc_tx_clk_en ) or (reg_cmd(1) and not gbtsc_tx_clk_en); - end process; + variable reg_res : std_logic_vector(1 downto 0) := "00"; + variable reg_con : std_logic_vector(1 downto 0) := "00"; + variable reg_cmd : std_logic_vector(1 downto 0) := "00"; + begin + wait until rising_edge(CLK); + reg_res := reg_res(0) & gbtsc_start_reset_cmd_raw; + reg_con := reg_con(0) & gbtsc_start_connect_cmd_raw; + reg_cmd := reg_cmd(0) & gbtsc_start_command_raw; + gbtsc_start_reset_cmd_i <= (reg_res(0) and not gbtsc_tx_clk_en ) or (reg_res(1) and not gbtsc_tx_clk_en); + gbtsc_start_connect_cmd_i <= (reg_con(0) and not gbtsc_tx_clk_en ) or (reg_con(1) and not gbtsc_tx_clk_en); + gbtsc_start_command_i <= (reg_cmd(0) and not gbtsc_tx_clk_en ) or (reg_cmd(1) and not gbtsc_tx_clk_en); + end process; PROC_SYNC_REG : process @@ -160,32 +164,57 @@ begin end process; + -- -- HDLC serializer + -- hdlcser_proc: process(CLK_80) + -- begin + -- if rising_edge(CLK_80) then + -- gbtsc_tx_clk_en <= gbtsc_tx_clk_en xor '1'; + -- if gbtsc_tx_clk_en = '1' then + -- ELINK_TX <= hdlc_from_gbtsc(0); + -- elsif gbtsc_tx_clk_en = '0' then + -- ELINK_TX <= hdlc_from_gbtsc(1); + -- end if; + -- end if; + -- end process; + -- HDLC serializer - hdlcser_proc: process(CLK) + hdlcser_proc: process(CLK_80) begin - if rising_edge(CLK) then - gbtsc_tx_clk_en <= gbtsc_tx_clk_en xor '1'; - if gbtsc_tx_clk_en = '1' then + if rising_edge(CLK_80) then + if CLK = '1' then ELINK_TX <= hdlc_from_gbtsc(0); - elsif gbtsc_tx_clk_en = '0' then + elsif CLK = '0' then ELINK_TX <= hdlc_from_gbtsc(1); end if; end if; end process; + -- -- HDLC deserializer + -- hdlcdes_proc: process(CLK) + -- variable hdlc_des: std_logic_vector(1 downto 0); + -- begin + -- if rising_edge(CLK) then + -- gbtsc_rx_clk_en <= gbtsc_rx_clk_en xor '1'; + -- hdlc_des := hdlc_des(0) & ELINK_RX; + -- if gbtsc_rx_clk_en = '1' then + -- hdlc_to_gbtsc <= hdlc_des; + -- end if; + -- end if; + -- end process; + -- HDLC deserializer - hdlcdes_proc: process(CLK) + hdlcdes_proc: process(CLK_80) + variable hdlc_des: std_logic_vector(1 downto 0); begin - if rising_edge(CLK) then - gbtsc_rx_clk_en <= gbtsc_rx_clk_en xor '1'; - if gbtsc_rx_clk_en = '1' then - hdlc_to_gbtsc(1) <= ELINK_RX; - elsif gbtsc_rx_clk_en = '0' then - hdlc_to_gbtsc(0) <= ELINK_RX; + if rising_edge(CLK_80) then + hdlc_des := hdlc_des(0) & ELINK_RX; + if CLK = '1' then + hdlc_to_gbtsc <= hdlc_des; end if; end if; end process; + PROC_GBTSCA_REG_CMDS : process begin wait until rising_edge(CLK_SYS); diff --git a/vldb/config_compile_frankfurt.pl b/vldb/config_compile_frankfurt.pl index 1c3992f..8f3fb38 100644 --- a/vldb/config_compile_frankfurt.pl +++ b/vldb/config_compile_frankfurt.pl @@ -17,7 +17,7 @@ par_options => '../par.p2t', #Include only necessary lpf files include_TDC => 0, -include_GBE => 0, +include_GBE => 1, #Report settings firefox_open => 0, diff --git a/vldb/par.p2t b/vldb/par.p2t index f989847..bba01d5 100644 --- a/vldb/par.p2t +++ b/vldb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 6 +-t 51 -c 2 -e 2 -i 10 diff --git a/vldb/trb5sc_mimosis.vhd b/vldb/trb5sc_mimosis.vhd index 5a3bdd0..474e641 100644 --- a/vldb/trb5sc_mimosis.vhd +++ b/vldb/trb5sc_mimosis.vhd @@ -728,16 +728,18 @@ begin THE_GBT_CORE : entity work.gbt_core port map( CLK_SYS => clk_sys, - CLK => clk_80, + CLK => clk_40, + CLK_80 => clk_80, RESET => reset_i, BUS_RX => busgbtcore_rx, BUS_TX => busgbtcore_tx, - ELINK_RX => H3(0), - ELINK_TX => H3(2) + ELINK_RX => H3(2), + ELINK_TX => H3(0) ); + H3(3) <= clk_80; --------------------------------------------------------------------------- -- Input stage -- 2.43.0