From 88dce992dcc843eddf737a814279179b763c8a15 Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 22 Jun 2010 08:51:36 +0000 Subject: [PATCH] *** empty log message *** --- trb_net_sbuf5.vhd | 75 +++++++++++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 32 deletions(-) diff --git a/trb_net_sbuf5.vhd b/trb_net_sbuf5.vhd index b157aa9..805f3b3 100644 --- a/trb_net_sbuf5.vhd +++ b/trb_net_sbuf5.vhd @@ -73,20 +73,22 @@ signal fifo_almostfull : std_logic; signal debug_x : std_logic_vector(15 downto 0); +attribute syn_preserve : boolean; +attribute syn_keep : boolean; +attribute syn_preserve of syn_data : signal is true; +attribute syn_keep of syn_data : signal is true; +attribute syn_preserve of syn_dataready : signal is true; +attribute syn_keep of syn_dataready : signal is true; +attribute syn_preserve of syn_dataready_x : signal is true; +attribute syn_keep of syn_dataready_x : signal is true; +attribute syn_preserve of fifo_wcnt : signal is true; +attribute syn_keep of fifo_wcnt : signal is true; +attribute syn_preserve of bsm : signal is true; +attribute syn_keep of bsm : signal is true; - attribute syn_preserve : boolean; - attribute syn_keep : boolean; - attribute syn_preserve of syn_data : signal is true; - attribute syn_keep of syn_data : signal is true; - attribute syn_preserve of syn_dataready : signal is true; - attribute syn_keep of syn_dataready : signal is true; - attribute syn_preserve of syn_dataready_x : signal is true; - attribute syn_keep of syn_dataready_x : signal is true; - - attribute syn_hier : string; - attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm"; - +attribute syn_hier : string; +attribute syn_hier of trb_net_sbuf5_arch : architecture is "flatten, firm"; begin @@ -140,10 +142,12 @@ begin CURRENT_STATE <= IDLE; syn_dataready <= '0'; update <= '0'; + bsm <= x"0"; else CURRENT_STATE <= NEXT_STATE; syn_dataready <= syn_dataready_x; update <= update_x; + bsm <= bsm_x; end if; end if; end process STATE_MEM; @@ -156,23 +160,20 @@ begin syn_dataready_x <= '0'; update_x <= '0'; case CURRENT_STATE is - when IDLE => bsm_x <= x"0"; - if( p_wait_x = '1' ) then + when IDLE => if( p_wait_x = '1' ) then NEXT_STATE <= RD1; fifo_rd_en_x <= '1'; update_x <= '1'; else NEXT_STATE <= IDLE; end if; - when RD1 => bsm_x <= x"1"; - if( p_wait_x = '1' ) then + when RD1 => if( p_wait_x = '1' ) then NEXT_STATE <= RD2; fifo_rd_en_x <= '1'; else NEXT_STATE <= RD1; end if; - when RD2 => bsm_x <= x"2"; - if ( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '1') ) then + when RD2 => if ( (p_avail_x = '1') and (SYN_READ_IN = '1') and (syn_dataready = '1') ) then NEXT_STATE <= RD3; syn_dataready_x <= '1'; fifo_rd_en_x <= '1'; @@ -183,8 +184,7 @@ begin NEXT_STATE <= RD2; syn_dataready_x <= p_avail_x; end if; - when DEL => bsm_x <= x"8"; - if( SYN_READ_IN = '1' ) then + when DEL => if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD3; fifo_rd_en_x <= '1'; syn_dataready_x <= '1'; @@ -192,8 +192,7 @@ begin NEXT_STATE <= DEL; syn_dataready_x <= '1'; end if; - when RD3 => bsm_x <= x"3"; - if( SYN_READ_IN = '1' ) then + when RD3 => if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD4; syn_dataready_x <= '1'; fifo_rd_en_x <= '1'; @@ -201,8 +200,7 @@ begin NEXT_STATE <= RD3; syn_dataready_x <= '1'; end if; - when RD4 => bsm_x <= x"4"; - if( SYN_READ_IN = '1' ) then + when RD4 => if( SYN_READ_IN = '1' ) then NEXT_STATE <= RD5; syn_dataready_x <= '1'; fifo_rd_en_x <= '1'; @@ -210,8 +208,7 @@ begin NEXT_STATE <= RD4; syn_dataready_x <= '1'; end if; - when RD5 => bsm_x <= x"5"; - syn_dataready_x <= '1'; + when RD5 => syn_dataready_x <= '1'; if ( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then NEXT_STATE <= WR5; fifo_rd_en_x <= '1'; @@ -220,26 +217,40 @@ begin else NEXT_STATE <= RD5; end if; - when WT5 => bsm_x <= x"6"; - if( SYN_READ_IN = '1' ) then + when WT5 => if( SYN_READ_IN = '1' ) then NEXT_STATE <= IDLE; else NEXT_STATE <= WT5; syn_dataready_x <= '1'; end if; - when WR5 => bsm_x <= x"7"; --- syn_dataready_x <= '1'; - if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then + when WR5 => if( (SYN_READ_IN = '1') and (p_avail_x = '1') ) then NEXT_STATE <= RD2; fifo_rd_en_x <= '1'; syn_dataready_x <= '1'; else NEXT_STATE <= WR5; end if; - when others => bsm_x <= x"f"; + when others => NEXT_STATE <= IDLE; end case; end process STATE_TRANSFORM; +THE_DECODE_PROC: process( NEXT_STATE ) +begin + case NEXT_STATE is + when IDLE => bsm_x <= x"0"; + when RD1 => bsm_x <= x"1"; + when RD2 => bsm_x <= x"2"; + when RD3 => bsm_x <= x"3"; + when RD4 => bsm_x <= x"4"; + when RD5 => bsm_x <= x"5"; + when WT5 => bsm_x <= x"6"; + when WR5 => bsm_x <= x"7"; + when WD5 => bsm_x <= x"8"; + when DEL => bsm_x <= x"9"; + when others => bsm_x <= x"f"; + end case; +end process THE_DECODE_PROC; + THE_SYNC_PROC: process( CLK ) begin if( rising_edge(CLK) ) then -- 2.43.0