From 89423b6094fac554d4f224f1f49dcaf94a203da5 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 26 Sep 2017 10:32:04 +0200 Subject: [PATCH] Add pinout option for KEL to TDC design --- tdctemplate/config.vhd | 12 ++++++----- tdctemplate/trb3sc_tdctemplate.vhd | 34 +++++++++++++++++------------- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index 560ccad..fc255c3 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -13,13 +13,15 @@ package config is --pinout to be used - don't forget to change config_compile.pl as well -- 0: 32 Pin AddOn -- 1: 4conn AddOn - constant PINOUT : integer := 1; + -- 2: 2x KEL on board + + constant PINOUT : integer := 2; --TDC settings constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 1; --double edge type: 0, 1, 2, 3 + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, @@ -54,9 +56,9 @@ package config is --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; - constant TRIG_GEN_INPUT_NUM : integer := 48; + constant TRIG_GEN_INPUT_NUM : integer := 32; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 52; + constant MONITOR_INPUT_NUM : integer := 36; ------------------------------------------------------------------------------ --End of design configuration diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 10248d3..e6a7573 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -31,17 +31,12 @@ entity trb3sc_tdctemplate is BACK_GPIO : inout std_logic_vector(3 downto 0); --AddOn Connector - 32 Pin AddOn - INP : in std_logic_vector(63 downto 0); - DAC_OUT_SDO : out std_logic_vector(4 downto 1); - DAC_OUT_SCK : out std_logic_vector(4 downto 1); - DAC_OUT_CS : out std_logic_vector(4 downto 1); - DAC_IN_SDI : in std_logic_vector(4 downto 1); + INP : in std_logic_vector(95 downto 0); + DAC_OUT_SDO : out std_logic_vector(6 downto 1); + DAC_OUT_SCK : out std_logic_vector(6 downto 1); + DAC_OUT_CS : out std_logic_vector(6 downto 1); + DAC_IN_SDI : in std_logic_vector(6 downto 1); - RES : out std_logic; - - --KEL Connector - KEL : in std_logic_vector(40 downto 1); - --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); RJ_IO : inout std_logic_vector(3 downto 0); @@ -96,7 +91,7 @@ entity trb3sc_tdctemplate is attribute syn_useioff of FLASH_CS : signal is true; attribute syn_useioff of FLASH_IN : signal is true; attribute syn_useioff of FLASH_OUT : signal is true; - attribute syn_useioff of KEL : signal is false; +-- attribute syn_useioff of KEL : signal is false; --Serdes: Backplane --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane @@ -355,8 +350,8 @@ begin ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => inputs(51 downto 0), - TRIG_GEN_INPUTS => inputs(47 downto 0), + MONITOR_INPUTS => inputs(MONITOR_INPUT_NUM-1 downto 0), + TRIG_GEN_INPUTS => inputs(TRIG_GEN_INPUT_NUM-1 downto 0), TRIG_GEN_OUTPUTS => trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, @@ -392,8 +387,8 @@ begin BACK_GPIO(1 downto 0) <= (others => 'Z'); BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2); - BACK_LVDS <= (others => '0'); - BACK_3V3 <= (others => 'Z'); +-- BACK_LVDS <= (others => '0'); +-- BACK_3V3 <= (others => 'Z'); gen_32pin : if PINOUT = 0 generate @@ -417,7 +412,16 @@ gen_4conn : if PINOUT = 1 generate DAC_OUT_SDO(4 downto 1) <= spi_mosi(3 downto 0); end generate; +gen_kel : if PINOUT = 2 generate + inputs(31 downto 0) <= INP(95 downto 64); + inputs(35 downto 32) <= trig_gen_out_i; + + spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5); + DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4); + DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4); + DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4); +end generate; --------------------------------------------------------------------------- -- 2.43.0