From 8994149ce8fd49316cb41fa6e0eb286f04f76977 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 22 Jul 2009 17:28:38 +0000 Subject: [PATCH] *** empty log message *** --- ..._8192depth_36width_dual_thresh_reg_out.vhd | 691 ++++++++------ design/mdc_oepb_pack.vhd | 66 ++ design/tdc_readout.vhd | 297 +++--- design/tdc_readout_and_trb_interface.vhd | 891 +++++------------- mdc_oepb.vhd | 46 +- 5 files changed, 867 insertions(+), 1124 deletions(-) diff --git a/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd b/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd index 40d64e6..082c299 100644 --- a/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd +++ b/design/fifo_8192depth_36width_dual_thresh_reg_out.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) -- Module Version: 4.6 ---/storage120/lattice/isplever7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -regout -no_enable -pe 0 -pe2 0 -pf 7000 -fill -e +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 36 -depth 8192 -regout -no_enable -pe 0 -pf 0 -fill -e --- Fri Jun 26 10:07:43 2009 +-- Wed Jul 22 17:09:39 2009 library IEEE; use IEEE.std_logic_1164.all; @@ -18,8 +18,8 @@ entity fifo_8192depth_36width_dual_thresh_reg_out is WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; - AmEmptySetThresh: in std_logic_vector(12 downto 0); - AmEmptyClrThresh: in std_logic_vector(12 downto 0); + AmEmptyThresh: in std_logic_vector(12 downto 0); + AmFullThresh: in std_logic_vector(12 downto 0); Q: out std_logic_vector(35 downto 0); WCNT: out std_logic_vector(13 downto 0); Empty: out std_logic; @@ -56,23 +56,8 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is signal wptr_11: std_logic; signal wptr_12: std_logic; signal wptr_13: std_logic; - signal rptr_0: std_logic; - signal rptr_1: std_logic; - signal rptr_2: std_logic; - signal rptr_3: std_logic; - signal rptr_4: std_logic; - signal rptr_5: std_logic; - signal rptr_6: std_logic; - signal rptr_7: std_logic; - signal rptr_8: std_logic; - signal rptr_9: std_logic; - signal rptr_10: std_logic; signal rptr_13: std_logic; - signal rptr_11: std_logic; - signal rptr_12: std_logic; signal rcnt_reg_13: std_logic; - signal ae: std_logic; - signal ae_d: std_logic; signal ifcount_0: std_logic; signal ifcount_1: std_logic; signal bdcnt_bctr_ci: std_logic; @@ -94,7 +79,6 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is signal ifcount_12: std_logic; signal ifcount_13: std_logic; signal co6: std_logic; - signal cnt_con: std_logic; signal co5: std_logic; signal cmp_ci: std_logic; signal co0_1: std_logic; @@ -110,13 +94,23 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is signal fcount_1: std_logic; signal co0_2: std_logic; signal fcount_2: std_logic; + signal fcount_3: std_logic; signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; signal co3_2: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; signal co4_2: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; signal co5_2: std_logic; - signal wren_i: std_logic; signal wren_i_inv: std_logic; + signal fcount_12: std_logic; + signal fcount_13: std_logic; signal cmp_ge_d1: std_logic; signal cmp_ge_d1_c: std_logic; signal iwcount_0: std_logic; @@ -142,6 +136,7 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is signal co6_1: std_logic; signal wcount_13: std_logic; signal co5_3: std_logic; + signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_ctr_ci: std_logic; @@ -351,108 +346,138 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is signal r_nw_inv_inv: std_logic; signal rcount_0: std_logic; signal r_nw_inv: std_logic; - signal wcount_0: std_logic; signal rcnt_sub_1: std_logic; signal rcnt_sub_2: std_logic; signal co0_5: std_logic; signal rcount_1: std_logic; signal rcount_2: std_logic; - signal wcount_1: std_logic; - signal wcount_2: std_logic; signal rcnt_sub_3: std_logic; signal rcnt_sub_4: std_logic; signal co1_5: std_logic; signal rcount_3: std_logic; signal rcount_4: std_logic; - signal wcount_3: std_logic; - signal wcount_4: std_logic; signal rcnt_sub_5: std_logic; signal rcnt_sub_6: std_logic; signal co2_5: std_logic; signal rcount_5: std_logic; signal rcount_6: std_logic; - signal wcount_5: std_logic; - signal wcount_6: std_logic; signal rcnt_sub_7: std_logic; signal rcnt_sub_8: std_logic; signal co3_5: std_logic; signal rcount_7: std_logic; signal rcount_8: std_logic; - signal wcount_7: std_logic; - signal wcount_8: std_logic; signal rcnt_sub_9: std_logic; signal rcnt_sub_10: std_logic; signal co4_5: std_logic; signal rcount_9: std_logic; signal rcount_10: std_logic; - signal wcount_9: std_logic; - signal wcount_10: std_logic; signal rcnt_sub_11: std_logic; signal rcnt_sub_12: std_logic; signal co5_5: std_logic; signal rcount_11: std_logic; signal rcount_12: std_logic; - signal wcount_11: std_logic; - signal wcount_12: std_logic; signal rcnt_sub_13: std_logic; signal co6_3: std_logic; signal rcnt_sub_msb: std_logic; + signal rden_i: std_logic; signal cmp_ci_2: std_logic; + signal rcnt_reg_0: std_logic; + signal rcnt_reg_1: std_logic; signal co0_6: std_logic; + signal rcnt_reg_2: std_logic; + signal rcnt_reg_3: std_logic; signal co1_6: std_logic; + signal rcnt_reg_4: std_logic; + signal rcnt_reg_5: std_logic; signal co2_6: std_logic; + signal rcnt_reg_6: std_logic; + signal rcnt_reg_7: std_logic; signal co3_6: std_logic; + signal rcnt_reg_8: std_logic; + signal rcnt_reg_9: std_logic; signal co4_6: std_logic; + signal rcnt_reg_10: std_logic; + signal rcnt_reg_11: std_logic; signal co5_6: std_logic; + signal rcnt_reg_12: std_logic; signal ae_set_clrsig: std_logic; signal ae_set_setsig: std_logic; signal ae_set_d: std_logic; signal ae_set_d_c: std_logic; - signal rden_i: std_logic; - signal cmp_ci_3: std_logic; - signal rcnt_reg_0: std_logic; - signal rcnt_reg_1: std_logic; + signal wcnt_sub_0: std_logic; + signal cnt_con_inv: std_logic; + signal rptr_0: std_logic; + signal cnt_con: std_logic; + signal wcount_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; signal co0_7: std_logic; - signal rcnt_reg_2: std_logic; - signal rcnt_reg_3: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; signal co1_7: std_logic; - signal rcnt_reg_4: std_logic; - signal rcnt_reg_5: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal wcount_3: std_logic; + signal wcount_4: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; signal co2_7: std_logic; - signal rcnt_reg_6: std_logic; - signal rcnt_reg_7: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal wcount_5: std_logic; + signal wcount_6: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; signal co3_7: std_logic; - signal rcnt_reg_8: std_logic; - signal rcnt_reg_9: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal wcount_7: std_logic; + signal wcount_8: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; signal co4_7: std_logic; - signal rcnt_reg_10: std_logic; - signal rcnt_reg_11: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal wcount_9: std_logic; + signal wcount_10: std_logic; + signal wcnt_sub_11: std_logic; + signal wcnt_sub_12: std_logic; signal co5_7: std_logic; - signal rcnt_reg_12: std_logic; - signal ae_clr_clrsig: std_logic; - signal ae_clr_setsig: std_logic; - signal ae_clr_d: std_logic; - signal ae_clr_d_c: std_logic; - signal cmp_ci_4: std_logic; - signal fcount_3: std_logic; - signal fcount_4: std_logic; + signal rptr_11: std_logic; + signal rptr_12: std_logic; + signal wcount_11: std_logic; + signal wcount_12: std_logic; + signal wcnt_sub_13: std_logic; + signal co6_4: std_logic; + signal wcnt_sub_msb: std_logic; + signal wren_i: std_logic; + signal cmp_ci_3: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; signal co0_8: std_logic; - signal fcount_5: std_logic; - signal fcount_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; signal co1_8: std_logic; - signal fcount_7: std_logic; - signal fcount_8: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; signal co2_8: std_logic; - signal fcount_9: std_logic; - signal fcount_10: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; signal co3_8: std_logic; - signal scuba_vhi: std_logic; - signal fcount_11: std_logic; - signal fcount_12: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; signal co4_8: std_logic; - signal fcount_13: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal co5_8: std_logic; + signal wcnt_reg_12: std_logic; + signal wcnt_reg_13: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -617,9 +642,8 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is attribute DATA_WIDTH_B : string; attribute DATA_WIDTH_A : string; attribute GSR : string; - attribute initval of LUT4_2 : label is "0x3232"; attribute initval of LUT4_1 : label is "0x3232"; - attribute initval of LUT4_0 : label is "0x4450"; + attribute initval of LUT4_0 : label is "0x3232"; attribute MEM_LPC_FILE of pdp_ram_0_0_15 : label is "fifo_8192depth_36width_dual_thresh_reg_out.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_0_15 : label is ""; attribute CSDECODE_B of pdp_ram_0_0_15 : label is "0b000"; @@ -812,6 +836,20 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is attribute REGMODE_A of pdp_ram_3_3_0 : label is "NOREG"; attribute DATA_WIDTH_B of pdp_ram_3_3_0 : label is "9"; attribute DATA_WIDTH_A of pdp_ram_3_3_0 : label is "9"; + attribute GSR of FF_139 : label is "ENABLED"; + attribute GSR of FF_138 : label is "ENABLED"; + attribute GSR of FF_137 : label is "ENABLED"; + attribute GSR of FF_136 : label is "ENABLED"; + attribute GSR of FF_135 : label is "ENABLED"; + attribute GSR of FF_134 : label is "ENABLED"; + attribute GSR of FF_133 : label is "ENABLED"; + attribute GSR of FF_132 : label is "ENABLED"; + attribute GSR of FF_131 : label is "ENABLED"; + attribute GSR of FF_130 : label is "ENABLED"; + attribute GSR of FF_129 : label is "ENABLED"; + attribute GSR of FF_128 : label is "ENABLED"; + attribute GSR of FF_127 : label is "ENABLED"; + attribute GSR of FF_126 : label is "ENABLED"; attribute GSR of FF_125 : label is "ENABLED"; attribute GSR of FF_124 : label is "ENABLED"; attribute GSR of FF_123 : label is "ENABLED"; @@ -942,80 +980,73 @@ architecture Structure of fifo_8192depth_36width_dual_thresh_reg_out is begin -- component instantiation statements - AND2_t9: AND2 + AND2_t8: AND2 port map (A=>WrEn, B=>invout_2, Z=>wren_i); - INV_7: INV + INV_8: INV port map (A=>full_i, Z=>invout_2); - AND2_t8: AND2 + AND2_t7: AND2 port map (A=>RdEn, B=>invout_1, Z=>rden_i); - INV_6: INV + INV_7: INV port map (A=>empty_i, Z=>invout_1); - AND2_t7: AND2 + AND2_t6: AND2 port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); - XOR2_t6: XOR2 + XOR2_t5: XOR2 port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); - INV_5: INV + INV_6: INV port map (A=>rden_i, Z=>rden_i_inv); - INV_4: INV + INV_5: INV port map (A=>wren_i, Z=>wren_i_inv); - LUT4_2: ROM16X1 + LUT4_1: ROM16X1 -- synopsys translate_off generic map (initval=> "0x3232") -- synopsys translate_on port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, AD0=>empty_i, DO0=>empty_d); - LUT4_1: ROM16X1 + LUT4_0: ROM16X1 -- synopsys translate_off generic map (initval=> "0x3232") -- synopsys translate_on port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, AD0=>full_i, DO0=>full_d); - AND2_t5: AND2 + AND2_t4: AND2 port map (A=>rden_i, B=>invout_0, Z=>r_nw); - INV_3: INV + INV_4: INV port map (A=>wren_i, Z=>invout_0); - INV_2: INV + INV_3: INV port map (A=>r_nw, Z=>r_nw_inv); - XOR2_t4: XOR2 + XOR2_t3: XOR2 port map (A=>wcount_13, B=>rcount_13, Z=>rcnt_sub_msb); - INV_1: INV + INV_2: INV port map (A=>r_nw_inv, Z=>r_nw_inv_inv); - INV_0: INV + INV_1: INV port map (A=>rcnt_reg_12, Z=>rcnt_reg_12_inv); - AND2_t3: AND2 - port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_set_clrsig); - AND2_t2: AND2 - port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_set_setsig); + port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_set_clrsig); AND2_t1: AND2 - port map (A=>rcnt_reg_13, B=>rcnt_reg_12_inv, Z=>ae_clr_clrsig); + port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_set_setsig); - AND2_t0: AND2 - port map (A=>rcnt_reg_13, B=>rcnt_reg_12, Z=>ae_clr_setsig); + XOR2_t0: XOR2 + port map (A=>wcount_13, B=>rptr_13, Z=>wcnt_sub_msb); - LUT4_0: ROM16X1 - -- synopsys translate_off - generic map (initval=> "0x4450") - -- synopsys translate_on - port map (AD3=>ae, AD2=>ae_set_d, AD1=>ae_clr_d, AD0=>scuba_vlo, - DO0=>ae_d); + INV_0: INV + port map (A=>cnt_con, Z=>cnt_con_inv); pdp_ram_0_0_15: DP16KB -- synopsys translate_off @@ -1669,869 +1700,953 @@ begin DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, DOB17=>open); - FF_125: FD1P3DX + FF_139: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_0); - FF_124: FD1P3DX + FF_138: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_1); - FF_123: FD1P3DX + FF_137: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_2); - FF_122: FD1P3DX + FF_136: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_3); - FF_121: FD1P3DX + FF_135: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_4); - FF_120: FD1P3DX + FF_134: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_5); - FF_119: FD1P3DX + FF_133: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_6); - FF_118: FD1P3DX + FF_132: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_7); - FF_117: FD1P3DX + FF_131: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_8); - FF_116: FD1P3DX + FF_130: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_9); - FF_115: FD1P3DX + FF_129: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_10); - FF_114: FD1P3DX + FF_128: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_11); - FF_113: FD1P3DX + FF_127: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_12, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_12); - FF_112: FD1P3DX + FF_126: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ifcount_13, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_13); - FF_111: FD1S3BX + FF_125: FD1S3BX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); - FF_110: FD1S3DX + FF_124: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); - FF_109: FD1P3BX + FF_123: FD1P3BX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, Q=>wcount_0); - FF_108: FD1P3DX + FF_122: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_1); - FF_107: FD1P3DX + FF_121: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_2); - FF_106: FD1P3DX + FF_120: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_3); - FF_105: FD1P3DX + FF_119: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_4); - FF_104: FD1P3DX + FF_118: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_5); - FF_103: FD1P3DX + FF_117: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_6); - FF_102: FD1P3DX + FF_116: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_7); - FF_101: FD1P3DX + FF_115: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_8); - FF_100: FD1P3DX + FF_114: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_9); - FF_99: FD1P3DX + FF_113: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_10); - FF_98: FD1P3DX + FF_112: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_11); - FF_97: FD1P3DX + FF_111: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_12); - FF_96: FD1P3DX + FF_110: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>iwcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_13); - FF_95: FD1P3BX + FF_109: FD1P3BX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, Q=>rcount_0); - FF_94: FD1P3DX + FF_108: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_1); - FF_93: FD1P3DX + FF_107: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_2); - FF_92: FD1P3DX + FF_106: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_3); - FF_91: FD1P3DX + FF_105: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_4); - FF_90: FD1P3DX + FF_104: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_5); - FF_89: FD1P3DX + FF_103: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_6); - FF_88: FD1P3DX + FF_102: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_7); - FF_87: FD1P3DX + FF_101: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_8); - FF_86: FD1P3DX + FF_100: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_9); - FF_85: FD1P3DX + FF_99: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_10); - FF_84: FD1P3DX + FF_98: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_11); - FF_83: FD1P3DX + FF_97: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_12, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_12); - FF_82: FD1P3DX + FF_96: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ircount_13, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_13); - FF_81: FD1P3DX + FF_95: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_0); - FF_80: FD1P3DX + FF_94: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_1); - FF_79: FD1P3DX + FF_93: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_2); - FF_78: FD1P3DX + FF_92: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_3); - FF_77: FD1P3DX + FF_91: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_4); - FF_76: FD1P3DX + FF_90: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_5); - FF_75: FD1P3DX + FF_89: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_6); - FF_74: FD1P3DX + FF_88: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_7); - FF_73: FD1P3DX + FF_87: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_8); - FF_72: FD1P3DX + FF_86: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_9); - FF_71: FD1P3DX + FF_85: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_10); - FF_70: FD1P3DX + FF_84: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_11); - FF_69: FD1P3DX + FF_83: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_12, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_12); - FF_68: FD1P3DX + FF_82: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>wcount_13, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wptr_13); - FF_67: FD1P3DX + FF_81: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_0); - FF_66: FD1P3DX + FF_80: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_1); - FF_65: FD1P3DX + FF_79: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_2); - FF_64: FD1P3DX + FF_78: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_3); - FF_63: FD1P3DX + FF_77: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_4); - FF_62: FD1P3DX + FF_76: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_5); - FF_61: FD1P3DX + FF_75: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_6); - FF_60: FD1P3DX + FF_74: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_7); - FF_59: FD1P3DX + FF_73: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_8); - FF_58: FD1P3DX + FF_72: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_9); - FF_57: FD1P3DX + FF_71: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_10); - FF_56: FD1P3DX + FF_70: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_11); - FF_55: FD1P3DX + FF_69: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_12, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_12); - FF_54: FD1P3DX + FF_68: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcount_13, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rptr_13); - FF_53: FD1P3DX + FF_67: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rptr_11, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, Q=>rptr_11_ff); - FF_52: FD1P3DX + FF_66: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rptr_12, SP=>rden_i, CK=>Clock, CD=>scuba_vlo, Q=>rptr_12_ff); - FF_51: FD1P3DX + FF_65: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_0, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(0)); - FF_50: FD1P3DX + FF_64: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_1, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(1)); - FF_49: FD1P3DX + FF_63: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_2, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(2)); - FF_48: FD1P3DX + FF_62: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_3, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(3)); - FF_47: FD1P3DX + FF_61: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_4, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(4)); - FF_46: FD1P3DX + FF_60: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_5, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(5)); - FF_45: FD1P3DX + FF_59: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_6, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(6)); - FF_44: FD1P3DX + FF_58: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_7, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(7)); - FF_43: FD1P3DX + FF_57: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_8, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(8)); - FF_42: FD1P3DX + FF_56: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_9, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(9)); - FF_41: FD1P3DX + FF_55: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_10, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(10)); - FF_40: FD1P3DX + FF_54: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_11, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(11)); - FF_39: FD1P3DX + FF_53: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_12, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(12)); - FF_38: FD1P3DX + FF_52: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_13, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(13)); - FF_37: FD1P3DX + FF_51: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_14, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(14)); - FF_36: FD1P3DX + FF_50: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_15, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(15)); - FF_35: FD1P3DX + FF_49: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_16, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(16)); - FF_34: FD1P3DX + FF_48: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_17, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(17)); - FF_33: FD1P3DX + FF_47: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_18, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(18)); - FF_32: FD1P3DX + FF_46: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_19, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(19)); - FF_31: FD1P3DX + FF_45: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_20, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(20)); - FF_30: FD1P3DX + FF_44: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_21, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(21)); - FF_29: FD1P3DX + FF_43: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_22, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(22)); - FF_28: FD1P3DX + FF_42: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_23, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(23)); - FF_27: FD1P3DX + FF_41: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_24, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(24)); - FF_26: FD1P3DX + FF_40: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_25, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(25)); - FF_25: FD1P3DX + FF_39: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_26, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(26)); - FF_24: FD1P3DX + FF_38: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_27, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(27)); - FF_23: FD1P3DX + FF_37: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_28, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(28)); - FF_22: FD1P3DX + FF_36: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_29, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(29)); - FF_21: FD1P3DX + FF_35: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_30, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(30)); - FF_20: FD1P3DX + FF_34: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_31, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(31)); - FF_19: FD1P3DX + FF_33: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_32, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(32)); - FF_18: FD1P3DX + FF_32: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_33, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(33)); - FF_17: FD1P3DX + FF_31: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_34, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(34)); - FF_16: FD1P3DX + FF_30: FD1P3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>ffidata_35, SP=>scuba_vhi, CK=>Clock, CD=>Reset, Q=>Q(35)); - FF_15: FD1S3DX + FF_29: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_0, CK=>Clock, CD=>Reset, Q=>rcnt_reg_0); - FF_14: FD1S3DX + FF_28: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_1, CK=>Clock, CD=>Reset, Q=>rcnt_reg_1); - FF_13: FD1S3DX + FF_27: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_2, CK=>Clock, CD=>Reset, Q=>rcnt_reg_2); - FF_12: FD1S3DX + FF_26: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_3, CK=>Clock, CD=>Reset, Q=>rcnt_reg_3); - FF_11: FD1S3DX + FF_25: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_4, CK=>Clock, CD=>Reset, Q=>rcnt_reg_4); - FF_10: FD1S3DX + FF_24: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_5, CK=>Clock, CD=>Reset, Q=>rcnt_reg_5); - FF_9: FD1S3DX + FF_23: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_6, CK=>Clock, CD=>Reset, Q=>rcnt_reg_6); - FF_8: FD1S3DX + FF_22: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_7, CK=>Clock, CD=>Reset, Q=>rcnt_reg_7); - FF_7: FD1S3DX + FF_21: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_8, CK=>Clock, CD=>Reset, Q=>rcnt_reg_8); - FF_6: FD1S3DX + FF_20: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_9, CK=>Clock, CD=>Reset, Q=>rcnt_reg_9); - FF_5: FD1S3DX + FF_19: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_10, CK=>Clock, CD=>Reset, Q=>rcnt_reg_10); - FF_4: FD1S3DX + FF_18: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_11, CK=>Clock, CD=>Reset, Q=>rcnt_reg_11); - FF_3: FD1S3DX + FF_17: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_12, CK=>Clock, CD=>Reset, Q=>rcnt_reg_12); - FF_2: FD1S3DX + FF_16: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on port map (D=>rcnt_sub_13, CK=>Clock, CD=>Reset, Q=>rcnt_reg_13); - FF_1: FD1S3BX + FF_15: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ae_set_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + + FF_2: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>ae); + port map (D=>wcnt_sub_12, CK=>Clock, CD=>Reset, Q=>wcnt_reg_12); + + FF_1: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcnt_sub_13, CK=>Clock, CD=>Reset, Q=>wcnt_reg_13); FF_0: FD1S3DX -- synopsys translate_off generic map (GSR=> "ENABLED") -- synopsys translate_on - port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); bdcnt_bctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, @@ -2674,6 +2789,9 @@ begin port map (CI=>co5_3, PC0=>wcount_12, PC1=>wcount_13, CO=>co6_1, NC0=>iwcount_12, NC1=>iwcount_13); + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + r_ctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, @@ -2928,31 +3046,31 @@ begin CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); ae_set_cmp_0: AGEB2 - port map (A0=>AmEmptySetThresh(0), A1=>AmEmptySetThresh(1), + port map (A0=>AmEmptyThresh(0), A1=>AmEmptyThresh(1), B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_2, GE=>co0_6); ae_set_cmp_1: AGEB2 - port map (A0=>AmEmptySetThresh(2), A1=>AmEmptySetThresh(3), + port map (A0=>AmEmptyThresh(2), A1=>AmEmptyThresh(3), B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_6, GE=>co1_6); ae_set_cmp_2: AGEB2 - port map (A0=>AmEmptySetThresh(4), A1=>AmEmptySetThresh(5), + port map (A0=>AmEmptyThresh(4), A1=>AmEmptyThresh(5), B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_6, GE=>co2_6); ae_set_cmp_3: AGEB2 - port map (A0=>AmEmptySetThresh(6), A1=>AmEmptySetThresh(7), + port map (A0=>AmEmptyThresh(6), A1=>AmEmptyThresh(7), B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_6, GE=>co3_6); ae_set_cmp_4: AGEB2 - port map (A0=>AmEmptySetThresh(8), A1=>AmEmptySetThresh(9), + port map (A0=>AmEmptyThresh(8), A1=>AmEmptyThresh(9), B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_6, GE=>co4_6); ae_set_cmp_5: AGEB2 - port map (A0=>AmEmptySetThresh(10), A1=>AmEmptySetThresh(11), + port map (A0=>AmEmptyThresh(10), A1=>AmEmptyThresh(11), B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_6, GE=>co5_6); ae_set_cmp_6: AGEB2 - port map (A0=>AmEmptySetThresh(12), A1=>ae_set_setsig, + port map (A0=>AmEmptyThresh(12), A1=>ae_set_setsig, B0=>rcnt_reg_12, B1=>ae_set_clrsig, CI=>co5_6, GE=>ae_set_d_c); @@ -2961,82 +3079,78 @@ begin B1=>scuba_vlo, CI=>ae_set_d_c, COUT=>open, S0=>ae_set_d, S1=>open); - ae_clr_cmp_ci_a: FADD2B - port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, - CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - - ae_clr_cmp_0: AGEB2 - port map (A0=>AmEmptyClrThresh(0), A1=>AmEmptyClrThresh(1), - B0=>rcnt_reg_0, B1=>rcnt_reg_1, CI=>cmp_ci_3, GE=>co0_7); + wcnt_0: FSUB2B + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + BI=>scuba_vlo, BOUT=>co0_7, S0=>open, S1=>wcnt_sub_0); - ae_clr_cmp_1: AGEB2 - port map (A0=>AmEmptyClrThresh(2), A1=>AmEmptyClrThresh(3), - B0=>rcnt_reg_2, B1=>rcnt_reg_3, CI=>co0_7, GE=>co1_7); + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + BI=>co0_7, BOUT=>co1_7, S0=>wcnt_sub_1, S1=>wcnt_sub_2); - ae_clr_cmp_2: AGEB2 - port map (A0=>AmEmptyClrThresh(4), A1=>AmEmptyClrThresh(5), - B0=>rcnt_reg_4, B1=>rcnt_reg_5, CI=>co1_7, GE=>co2_7); + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + BI=>co1_7, BOUT=>co2_7, S0=>wcnt_sub_3, S1=>wcnt_sub_4); - ae_clr_cmp_3: AGEB2 - port map (A0=>AmEmptyClrThresh(6), A1=>AmEmptyClrThresh(7), - B0=>rcnt_reg_6, B1=>rcnt_reg_7, CI=>co2_7, GE=>co3_7); + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + BI=>co2_7, BOUT=>co3_7, S0=>wcnt_sub_5, S1=>wcnt_sub_6); - ae_clr_cmp_4: AGEB2 - port map (A0=>AmEmptyClrThresh(8), A1=>AmEmptyClrThresh(9), - B0=>rcnt_reg_8, B1=>rcnt_reg_9, CI=>co3_7, GE=>co4_7); + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + BI=>co3_7, BOUT=>co4_7, S0=>wcnt_sub_7, S1=>wcnt_sub_8); - ae_clr_cmp_5: AGEB2 - port map (A0=>AmEmptyClrThresh(10), A1=>AmEmptyClrThresh(11), - B0=>rcnt_reg_10, B1=>rcnt_reg_11, CI=>co4_7, GE=>co5_7); + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + BI=>co4_7, BOUT=>co5_7, S0=>wcnt_sub_9, S1=>wcnt_sub_10); - ae_clr_cmp_6: AGEB2 - port map (A0=>AmEmptyClrThresh(12), A1=>ae_clr_setsig, - B0=>rcnt_reg_12, B1=>ae_clr_clrsig, CI=>co5_7, - GE=>ae_clr_d_c); + wcnt_6: FSUB2B + port map (A0=>wcount_11, A1=>wcount_12, B0=>rptr_11, B1=>rptr_12, + BI=>co5_7, BOUT=>co6_4, S0=>wcnt_sub_11, S1=>wcnt_sub_12); - a3: FADD2B - port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>ae_clr_d_c, COUT=>open, S0=>ae_clr_d, + wcnt_7: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co6_4, BOUT=>open, S0=>wcnt_sub_13, S1=>open); - af_cmp_ci_a: FADD2B - port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_4, S0=>open, - S1=>open); + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_3, S0=>open, S1=>open); - af_cmp_0: AGEB2 - port map (A0=>fcount_3, A1=>fcount_4, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>cmp_ci_4, GE=>co0_8); + af_set_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_3, GE=>co0_8); - af_cmp_1: AGEB2 - port map (A0=>fcount_5, A1=>fcount_6, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>co0_8, GE=>co1_8); + af_set_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_8, GE=>co1_8); - af_cmp_2: AGEB2 - port map (A0=>fcount_7, A1=>fcount_8, B0=>scuba_vlo, - B1=>scuba_vhi, CI=>co1_8, GE=>co2_8); + af_set_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_8, GE=>co2_8); - af_cmp_3: AGEB2 - port map (A0=>fcount_9, A1=>fcount_10, B0=>scuba_vhi, - B1=>scuba_vlo, CI=>co2_8, GE=>co3_8); + af_set_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_8, GE=>co3_8); - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); + af_set_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_8, GE=>co4_8); - af_cmp_4: AGEB2 - port map (A0=>fcount_11, A1=>fcount_12, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>co3_8, GE=>co4_8); + af_set_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>AmFullThresh(11), CI=>co4_8, GE=>co5_8); - af_cmp_5: AGEB2 - port map (A0=>fcount_13, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co4_8, GE=>af_d_c); + af_set_cmp_6: AGEB2 + port map (A0=>wcnt_reg_12, A1=>wcnt_reg_13, B0=>AmFullThresh(12), + B1=>scuba_vlo, CI=>co5_8, GE=>af_set_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); - a4: FADD2B + a3: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); WCNT(0) <= fcount_0; WCNT(1) <= fcount_1; @@ -3054,7 +3168,6 @@ begin WCNT(13) <= fcount_13; Empty <= empty_i; Full <= full_i; - AlmostEmpty <= ae; end Structure; -- synopsys translate_off diff --git a/design/mdc_oepb_pack.vhd b/design/mdc_oepb_pack.vhd index 9e62f3b..f943df3 100644 --- a/design/mdc_oepb_pack.vhd +++ b/design/mdc_oepb_pack.vhd @@ -122,7 +122,73 @@ component mdc_addon_daq_bus_0 LED_GOOD_OUT : out std_logic); end component; + component counter_4bit + port ( + QOUT : out std_logic_vector(3 downto 0); + UP : in std_logic; + CLK : in std_logic; + RESET : in std_logic; + CLR : in std_logic); + end component; + + + +--------------------------------------------------------------------------- +--tdc_readout +--------------------------------------------------------------------------- + component tdc_readout + port ( + CLK : in std_logic; + RESET : in std_logic; + A_ADD_IN : in std_logic_vector(8 downto 0); + A_RESERV_IN : in std_logic; --this is 11 bit of dataword + A_AOD_IN : in std_logic; --address or data + A_DST_IN : in std_logic; + TOKEN_IN : in std_logic_vector(3 downto 0); + TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); + FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); + DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(23 downto 0); + DATA_VALID_OUT : out std_logic; + FULL_FIFO_IN : in std_logic; + INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); + DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); --x"0"debug, + --x"1" 2 hit in one word + DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); + end component; + + component fifo_8192depth_36width_dual_thresh_reg_out + port ( + Data: in std_logic_vector(35 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + AmEmptyThresh: in std_logic_vector(12 downto 0); + AmFullThresh: in std_logic_vector(12 downto 0); + Q: out std_logic_vector(35 downto 0); + WCNT: out std_logic_vector(13 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; + AlmostFull: out std_logic); + end component; + component fifo_fall_through_512depth_52width_reg_out + port ( + Data : in std_logic_vector(51 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptySetThresh : in std_logic_vector(8 downto 0); + AmEmptyClrThresh : in std_logic_vector(8 downto 0); + Q : out std_logic_vector(51 downto 0); + WCNT : out std_logic_vector(9 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + AlmostFull : out std_logic); + end component; component edge_to_pulse port ( diff --git a/design/tdc_readout.vhd b/design/tdc_readout.vhd index 14c386b..1876539 100644 --- a/design/tdc_readout.vhd +++ b/design/tdc_readout.vhd @@ -1,9 +1,9 @@ ------------------------------------------------------------------------------- -- Attilio Tarantola --- Create Date: 18/04/2007 +-- Create Date: 18/04/2007 -- Description: it reads out data, first I save the first part of the data and -- then the second. --- +-- -- --This code has not optimized yet. -- @@ -33,7 +33,7 @@ entity tdc_readout is FULL_FIFO_IN : in std_logic; INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); --from common stop generator ---x"0"debug, x"1" 2 hit in one word, x"2" test data, +--x"0"debug, x"1" 2 hit in one word, x"2" test data, DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); end tdc_readout; @@ -43,7 +43,7 @@ architecture behavioral of tdc_readout is -- debug mode signals ------------------------------------------------------------------------------- type state_type is (idle_state, - save_H_word_state, save_H_word_state_next, + wait_for_AOD_low_state, save_H_word_state_next, save_L_word_state,save_L_word_state_next, wait_1_state,wait_2_state,wait_3_state, wait_4_state, send_data,send_data_next, send_data_with_valid, @@ -126,11 +126,11 @@ signal reg_token_tdc_readout_i_test_data, next_token_tdc_readout_i_test_data : s signal counter_test_data : std_logic_vector(15 downto 0); begin -- behavioral - + ------------------------------------------------------------------------------- -- DEBUG DATAWORD STRUCTURE : BEGIN -------------------------------------------------------------------------------- - REGISTER_OUTPUT : process (CLK, reg_data_type_select_in) +------------------------------------------------------------------------------- + REGISTER_OUTPUT : process (CLK, reg_data_type_select_in) begin if rising_edge(CLK) then if (RESET = '1' or reg_data_type_select_in = x"1" or @@ -150,31 +150,30 @@ begin -- behavioral end if; end process REGISTER_OUTPUT; - + ------------------------------------------------------------------------------ --- purpose: state machine. get TDC data and build a std_logic_vector +-- purpose: state machine. get TDC data and build a std_logic_vector ------------------------------------------------------------------------------ process(current_state, TOKEN_IN, INIT_TDC_READOUT_IN, A_DST_IN, A_AOD_IN, FULL_FIFO_IN) - - begin - + + begin + next_data_valid_out <= '0'; next_data_bus_out <= (others => '0'); next_debug_register <= (others => '0'); next_token_tdc_readout_i <= (others => '0'); - + next_state <= current_state; + case current_state is when idle_state => next_debug_register <= "0000"; -- x"1" normal trigger -- x"9" calibration trigger - if (INIT_TDC_READOUT_IN = x"1" or + if (INIT_TDC_READOUT_IN = x"1" or INIT_TDC_READOUT_IN = x"9") then next_state <= save_L_word_state; - else - next_state <= idle_state; end if; ------------------------------------------------------------------------------- -- If (A_DST = '1' and A_AOD_IN = '1') means one dataword is coming, if so it @@ -188,85 +187,71 @@ begin -- behavioral -- token back: TOKEN_IN = x"1" -- token NOT back: TOKEN_IN = x"2" ------------------------------------------------------------------------------- - when save_L_word_state => - next_debug_register <= "0001"; + when save_L_word_state => + next_debug_register <= "0001"; if A_DST_IN = '1' and A_AOD_IN = '1' then --- next_state <= save_L_word_state_next; +-- next_state <= save_L_word_state_next; next_state <= wait_1_state; -- elsif TOKEN_IN = x"1" then --token and NO data --- next_state <= send_token_state_2; +-- next_state <= send_token_state_2; -- elsif TOKEN_IN = x"2" then --NO token and NO data -- next_state <= send_token_state_3; - else - next_state <= save_L_word_state; end if; - when wait_1_state => + when wait_1_state => next_state <= wait_2_state; - when wait_2_state => + when wait_2_state => next_state <= save_L_word_state_next; - + when save_L_word_state_next => --here I save data - next_state <= save_H_word_state; - - when save_H_word_state => - next_debug_register <= "0011"; + next_state <= wait_for_AOD_low_state; + + when wait_for_AOD_low_state => + next_debug_register <= "0011"; if A_DST_IN = '1' and A_AOD_IN = '0' then - -- next_state <= save_H_word_state_next; next_state <= wait_3_state; - else - next_state <= save_H_word_state; end if; - when wait_3_state => + when wait_3_state => next_state <= wait_4_state; - when wait_4_state => + when wait_4_state => next_state <= save_H_word_state_next; - + when save_H_word_state_next => --here I save data - --next_data_valid_out <= '1'; - next_state <= send_data_with_valid; - - - when send_data_with_valid => - next_debug_register <= "0101"; - next_data_valid_out <= '0'; --connected to WRITE_FIFO - next_state <= send_data_with_valid_next; + next_state <= send_data_with_valid; + + when send_data_with_valid => + next_debug_register <= "0101"; + next_state <= send_data_with_valid_next; -- if FULL_FIFO_IN = '1' then --not full --- next_state <= send_data_with_valid_next; +-- next_state <= send_data_with_valid_next; -- else --- next_state <= fifo_full_state; +-- next_state <= fifo_full_state; -- end if; - + when send_data_with_valid_next => next_debug_register <= "0111"; next_data_valid_out <= '1'; next_state <= send_data_no_valid; when send_data_no_valid => - next_debug_register <= "1000"; - next_data_valid_out <= '0'; --connected to WRITE_FIFO - if (A_AOD_IN = '1' and TOKEN_IN = x"0") then - next_state <= save_L_word_state; - elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then + next_debug_register <= "1000"; + if (TOKEN_IN = x"1") then next_state <= send_token_state_1; --token and data - --- elsif (A_AOD_IN = '0' and TOKEN_IN = x"2") then --NO token back and data in fifo --- next_state <= send_token_state_4; -- NO token and data - else - next_state <= send_data_no_valid; + elsif (A_AOD_IN = '1') then + next_state <= save_L_word_state; end if; - + ------------------------------------------------------------------------------- -- token + data => => => => OK ------------------------------------------------------------------------------- when send_token_state_1 => - next_debug_register <= "1001"; - next_token_tdc_readout_i <= x"1"; + next_debug_register <= "1001"; + next_token_tdc_readout_i <= x"1"; next_state <= idle_state; - + when others => next_state <= idle_state; @@ -277,14 +262,14 @@ begin -- behavioral -- process: it gets the token from entity "send_token", -- it is back I send to TRB ------------------------------------------------------------------------------ - save_data: process (CLK,next_state) - begin + save_data: process (CLK) + begin if rising_edge(CLK) then if RESET = '1' then saved_data <= (others => '0'); elsif (next_state = save_H_word_state_next) then saved_data(35 downto 32) <= reg_flag_event_counter_in; - saved_data(31 downto 26) <= reg_flag_event_counter_in & "00";--x"0"; + saved_data(31 downto 26) <= reg_flag_event_counter_in & "00";--x"0"; saved_data(25 downto 23) <= '0' & "00";--mb_number; saved_data(22 downto 19) <= x"0";--reg_bus_number;--x"1"; saved_data(18 downto 12) <= A_ADD_IN(8 downto 2); @@ -292,11 +277,9 @@ begin -- behavioral saved_data(10 downto 9) <= A_ADD_IN(1 downto 0); saved_data(8 downto 0) <= saved_data(8 downto 0); elsif (next_state = save_L_word_state_next) then - saved_data(18 downto 9) <= saved_data(18 downto 9); - saved_data(8 downto 0) <= A_ADD_IN(8 downto 0); - else - saved_data <= saved_data; - end if; + saved_data(18 downto 9) <= saved_data(18 downto 9); + saved_data(8 downto 0) <= A_ADD_IN(8 downto 0); + end if; end if; end process save_data; @@ -314,12 +297,12 @@ begin -- behavioral ------------------------------------------------------------------------------- -- DEBUG DATAWORD STRUCTURE : END -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- 2 HITS IN ONE DATAWORD STRUCTURE : BEGIN -- here I repeat a new FSM to build the data in a compact way: 2 hits in one word -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- --register data select process (CLK, RESET) @@ -334,7 +317,7 @@ begin -- behavioral end if; end if; end process; - + ------------------------------------------------------------------------------- -- DATA SELECT MULTIPLEXER ------------------------------------------------------------------------------- @@ -358,7 +341,7 @@ begin -- behavioral DATA_BUS_OUT <= reg_data_bus_out_test_data; TOKEN_TDC_READOUT_OUT <= reg_token_tdc_readout_i_test_data; DEBUG_REGISTER_OUT <= reg_debug_register_test_data; - + else --debug mode DATA_VALID_OUT <= reg_data_valid_out; DATA_BUS_OUT <= saved_data; @@ -369,9 +352,9 @@ begin -- behavioral end process; ------------------------------------------------------------------------------- --- +-- ------------------------------------------------------------------------------- --- REGISTER_OUTPUT_NEW_FORMAT : process (CLK, reg_data_type_select_in) +-- REGISTER_OUTPUT_NEW_FORMAT : process (CLK, reg_data_type_select_in) -- begin -- if rising_edge(CLK) then -- if (RESET = '1' or reg_data_type_select_in = x"0") then @@ -388,7 +371,7 @@ begin -- behavioral -- reg_token_tdc_readout_i_new_format <= next_token_tdc_readout_i_new_format; -- end if; -- end if; --- end process REGISTER_OUTPUT_NEW_FORMAT; +-- end process REGISTER_OUTPUT_NEW_FORMAT; -- ------------------------------------------------------------------------------ -- -- purpose: state machine. @@ -396,12 +379,12 @@ begin -- behavioral -- process(current_state_new_format, TOKEN_IN, INIT_TDC_READOUT_IN, -- A_DST_IN, A_AOD_IN, FULL_FIFO_IN, -- counter_check_hit, --- saved_data_new_format_hit_0, saved_data_new_format_hit_1, +-- saved_data_new_format_hit_0, saved_data_new_format_hit_1, -- counter_check_hit_calibration, -- saved_data_new_format_hit_0_cal, saved_data_new_format_hit_1_cal) - --- begin - + +-- begin + -- next_data_valid_out_new_format <= '0'; -- next_data_bus_out_new_format <= (others => '0'); -- next_debug_register_new_format <= (others => '0'); @@ -412,7 +395,7 @@ begin -- behavioral -- up_counter_check_hit_calibration <= '0'; -- saved_data_new_format <= (others => '0'); -- clear_saved_data_new_format_hit_0_1_cal <= '0'; - + -- case current_state_new_format is -- when idle_state_new_format => @@ -422,31 +405,31 @@ begin -- behavioral -- --normal trigger -- if (INIT_TDC_READOUT_IN = x"1") then -- next_state_new_format <= save_L_word_state_new_format; --- --calibration trigger +-- --calibration trigger -- elsif (INIT_TDC_READOUT_IN = x"9") then -- next_state_new_format <= save_L_word_state_new_format_calibration; -- else -- next_state_new_format <= idle_state_new_format; -- end if; --- when save_L_word_state_new_format => --- next_debug_register_new_format <= x"1"; +-- when save_L_word_state_new_format => +-- next_debug_register_new_format <= x"1"; -- if (A_DST_IN = '1' and A_AOD_IN = '1') then --- next_state_new_format <= save_L_word_state_next_new_format; +-- next_state_new_format <= save_L_word_state_next_new_format; -- elsif (TOKEN_IN = x"1") then --token and NO data --- next_state_new_format <= send_token_state_2_new_format; +-- next_state_new_format <= send_token_state_2_new_format; -- elsif (TOKEN_IN = x"2") then --NO token and NO data -- next_state_new_format <= send_token_state_3_new_format; -- else -- next_state_new_format <= save_L_word_state_new_format; -- end if; - + -- when save_L_word_state_next_new_format => --here I save data --- next_debug_register_new_format <= x"2"; +-- next_debug_register_new_format <= x"2"; -- next_state_new_format <= save_H_word_state_new_format; - + -- when save_H_word_state_new_format => --- next_debug_register_new_format <= x"3"; +-- next_debug_register_new_format <= x"3"; -- if (A_DST_IN = '1' and A_AOD_IN = '0') then -- next_state_new_format <= save_H_word_state_next_new_format; -- else @@ -454,7 +437,7 @@ begin -- behavioral -- end if; -- ------------------------------------------------------------------------------- -- -- I must check the hit number. If it is '0' --- ------------------------------------------------------------------------------- +-- ------------------------------------------------------------------------------- -- when save_H_word_state_next_new_format => --here I save data -- next_debug_register_new_format <= x"4"; -- up_counter_check_hit <= '1'; --increase hit number @@ -466,12 +449,12 @@ begin -- behavioral -- case counter_check_hit is -- --first hit already saved - + -- when x"1" => -- --go and save the second hit --- if (saved_data_new_format_hit_0(11) = '1') then +-- if (saved_data_new_format_hit_0(11) = '1') then -- --new dataword coming --- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then +-- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then -- next_state_new_format <= save_L_word_state_new_format; -- else -- next_state_new_format <= check_hit_number_state_new_format; @@ -481,7 +464,7 @@ begin -- behavioral -- if (saved_data_new_format_hit_0(28 downto 22) = saved_data_new_format_hit_1(28 downto 22) ) then -- --3rd hit -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "010"; +-- saved_data_new_format(31 downto 29) <= "010"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= (others => '0'); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); @@ -489,16 +472,16 @@ begin -- behavioral -- --single hit -- else -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "101"; +-- saved_data_new_format(31 downto 29) <= "101"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= (others => '0'); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); -- next_state_new_format <= send_one_hit_new_format; --- end if; --- end if; --- --I check if tdc number and channel are the same --- when x"2" => --- if (saved_data_new_format_hit_0(28 downto 22) = saved_data_new_format_hit_1(28 downto 22) ) then +-- end if; +-- end if; +-- --I check if tdc number and channel are the same +-- when x"2" => +-- if (saved_data_new_format_hit_0(28 downto 22) = saved_data_new_format_hit_1(28 downto 22) ) then -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); -- saved_data_new_format(31 downto 29) <= "001"; --normal word, two hit in one -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); @@ -508,18 +491,18 @@ begin -- behavioral -- else -- --I send 2 hit in one but with error flag -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(31 downto 29) <= "100"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); -- next_state_new_format <= send_error_word; -- end if; --- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => +-- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => -- next_state_new_format <= send_data_with_valid_new_format; -- when others => null; -- end case; - + -- ------------------------------------------------------------------------------- -- -- send two hits in one dataword -- ------------------------------------------------------------------------------- @@ -562,7 +545,7 @@ begin -- behavioral -- end if; -- ------------------------------------------------------------------------------- --- -- send single hit in one dataword +-- -- send single hit in one dataword -- ------------------------------------------------------------------------------- -- when send_one_hit_new_format => -- next_debug_register_new_format <= x"8"; @@ -600,7 +583,7 @@ begin -- behavioral -- next_state_new_format <= wait_state_1_new_format; -- end if; -- ------------------------------------------------------------------------------- --- -- send third hit +-- -- send third hit -- ------------------------------------------------------------------------------- -- when send_third_hit_new_format => -- next_data_valid_out_new_format <= '1'; @@ -642,7 +625,7 @@ begin -- behavioral -- next_debug_register_new_format <= x"6"; -- next_data_valid_out_new_format <= '1'; -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(31 downto 29) <= "100"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); @@ -653,7 +636,7 @@ begin -- behavioral -- next_debug_register_new_format <= x"7"; -- next_data_valid_out_new_format <= '0'; -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(31 downto 29) <= "100"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); @@ -663,7 +646,7 @@ begin -- behavioral -- next_debug_register_new_format <= x"8"; -- next_data_valid_out_new_format <= '0'; -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0(35 downto 32); --- saved_data_new_format(31 downto 29) <= "100"; +-- saved_data_new_format(31 downto 29) <= "100"; -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0(10 downto 0); @@ -677,7 +660,7 @@ begin -- behavioral -- end if; -- ------------------------------------------------------------------------------ --- --READOUT CALIBRATION DATA +-- --READOUT CALIBRATION DATA -- ------------------------------------------------------------------------------ -- when save_L_word_state_new_format_calibration => -- next_debug_register_new_format <= x"1"; @@ -718,7 +701,7 @@ begin -- behavioral -- up_counter_check_hit_calibration <= '0'; -- case counter_check_hit_calibration is --- --clear counter_check_hit_calibration after one channel has been calibrated +-- --clear counter_check_hit_calibration after one channel has been calibrated -- when x"1" => -- --go and save the second hit -- if (saved_data_new_format_hit_0_cal(11) = '1') then @@ -740,24 +723,24 @@ begin -- behavioral -- end if; -- --combine word nr0 and nr1 and send --- when x"2" => +-- when x"2" => -- --you should add a safe condition, in case the FEE has problem, like --- --if (saved_data_new_format_hit_1_cal(11) = '1' ) then --- -- if (saved_data_new_format_hit_0_cal(28 downto 22) = saved_data_new_format_hit_1_cal(28 downto 22) ) then +-- --if (saved_data_new_format_hit_1_cal(11) = '1' ) then +-- -- if (saved_data_new_format_hit_0_cal(28 downto 22) = saved_data_new_format_hit_1_cal(28 downto 22) ) then -- saved_data_new_format(35 downto 32) <= saved_data_new_format_hit_0_cal(35 downto 32); -- saved_data_new_format(31 downto 29) <= "110"; --normal cal word, two hit in one -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); -- next_state_new_format <= wait_state_2_calibration;--send_calibration_data; - --- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => + +-- when x"0"|x"3"|x"4"|x"5"|x"6"|x"7"|x"8"|x"9"|x"a"|x"b"|x"c"| x"d"|x"e"|x"f" => -- next_state_new_format <= send_error_calibration_word; -- when others => null; -- end case; - + -- ------------------------------------------------------------------------------- --- --send calibration data, when no error found in dataword building +-- --send calibration data, when no error found in dataword building -- ------------------------------------------------------------------------------- -- when wait_state_2_calibration => @@ -800,7 +783,7 @@ begin -- behavioral -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); -- if (A_AOD_IN = '1' and TOKEN_IN = x"0") then -- clear_counter_check_hit_calibration <= '1'; --clear cal dataword number --- clear_saved_data_new_format_hit_0_1_cal <= '1'; --clear save data vector +-- clear_saved_data_new_format_hit_0_1_cal <= '1'; --clear save data vector -- next_state_new_format <= save_L_word_state_new_format_calibration; -- elsif (A_AOD_IN = '0' and TOKEN_IN = x"1") then -- next_state_new_format <= send_token_state_1_new_format; @@ -818,7 +801,7 @@ begin -- behavioral -- saved_data_new_format(28 downto 22) <= saved_data_new_format_hit_0_cal(28 downto 22); -- saved_data_new_format(21 downto 11) <= saved_data_new_format_hit_1_cal(10 downto 0); -- saved_data_new_format(10 downto 0) <= saved_data_new_format_hit_0_cal(10 downto 0); --- next_state_new_format <= send_error_calibration_word_next; +-- next_state_new_format <= send_error_calibration_word_next; -- when send_error_calibration_word_next => -- next_debug_register_new_format <= x"7"; @@ -860,34 +843,34 @@ begin -- behavioral -- -- token + NO data => => => => OK -- ------------------------------------------------------------------------------- -- when send_token_state_2_new_format => --- next_debug_register_new_format <= "1011"; --- next_token_tdc_readout_i_new_format <= x"3"; +-- next_debug_register_new_format <= "1011"; +-- next_token_tdc_readout_i_new_format <= x"3"; -- next_state_new_format <= idle_state_new_format; -- ------------------------------------------------------------------------------- -- -- NO token + NO data -- ------------------------------------------------------------------------------- -- when send_token_state_3_new_format => --- next_debug_register_new_format <= "1100"; --- next_token_tdc_readout_i_new_format <= x"4"; +-- next_debug_register_new_format <= "1100"; +-- next_token_tdc_readout_i_new_format <= x"4"; -- next_state_new_format <= idle_state_new_format; -- ------------------------------------------------------------------------------- -- -- NO token + data -- ------------------------------------------------------------------------------- -- when send_token_state_4_new_format => --- next_debug_register_new_format <= "1100"; --- next_token_tdc_readout_i_new_format <= x"5"; +-- next_debug_register_new_format <= "1100"; +-- next_token_tdc_readout_i_new_format <= x"5"; -- next_state_new_format <= idle_state_new_format; - + -- when fifo_full_state_new_format => --- next_debug_register_new_format <= "1100"; +-- next_debug_register_new_format <= "1100"; -- next_data_valid_out_new_format <= '0'; -- --I stay here if there is no space in the fifo -- if FULL_FIFO_IN = '1' then --cannot write anymore in fifo --- next_state_new_format <= fifo_full_state_new_format; +-- next_state_new_format <= fifo_full_state_new_format; -- else --- next_state_new_format <= idle_state_new_format; +-- next_state_new_format <= idle_state_new_format; -- end if; - + -- when others => -- next_state_new_format <= idle_state_new_format; -- end case; @@ -904,7 +887,7 @@ begin -- behavioral -- if (RESET = '1') then -- saved_data_new_format_hit_0 <= (others => '0'); -- saved_data_new_format_hit_1 <= (others => '0'); - + -- --I increase the counter after one full word is collected -- -- FIRST HIT @@ -924,7 +907,7 @@ begin -- behavioral -- else -- saved_data_new_format_hit_0 <= saved_data_new_format_hit_0; -- end if; - + -- -- SECOND HIT -- elsif (counter_check_hit = x"1") then --save the second hit and TDC number/channel @@ -935,7 +918,7 @@ begin -- behavioral -- saved_data_new_format_hit_1(11) <= A_RESERV_IN; --hit number -- saved_data_new_format_hit_1(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA -- saved_data_new_format_hit_1(8 downto 0) <= saved_data_new_format_hit_1(8 downto 0); - + -- elsif (next_state_new_format = save_L_word_state_next_new_format) then -- saved_data_new_format_hit_1(18 downto 9) <= saved_data_new_format_hit_1(18 downto 9); -- saved_data_new_format_hit_1(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA @@ -947,7 +930,7 @@ begin -- behavioral -- end if; -- end if; -- end process SAVE_DATA_NEW_FORMAT; - + -- ------------------------------------------------------------------------------- -- -- Save calibration data process -- ------------------------------------------------------------------------------- @@ -958,7 +941,7 @@ begin -- behavioral -- if (RESET = '1' or clear_saved_data_new_format_hit_0_1_cal = '1') then -- saved_data_new_format_hit_0_cal <= (others => '0'); -- saved_data_new_format_hit_1_cal <= (others => '0'); - + -- --I increase the counter after one full word is collected -- elsif (counter_check_hit_calibration = x"0") then --save the first hit and TDC number/channel @@ -979,15 +962,15 @@ begin -- behavioral -- end if; -- elsif (counter_check_hit_calibration = x"1") then --save the second hit and TDC number/channel - + -- if (current_state_new_format = save_H_word_state_next_new_format_calibration) then -- saved_data_new_format_hit_1_cal(35 downto 32) <= FLAG_EVENT_COUNTER_IN; --INTERNAL USE --- saved_data_new_format_hit_1_cal(31 downto 29) <= saved_data_new_format_hit_1_cal(31 downto 29); +-- saved_data_new_format_hit_1_cal(31 downto 29) <= saved_data_new_format_hit_1_cal(31 downto 29); -- saved_data_new_format_hit_1_cal(28 downto 22) <= A_ADD_IN(8 downto 2); --TDCnr/CHANNEL -- saved_data_new_format_hit_1_cal(11) <= A_RESERV_IN; --hit number -- saved_data_new_format_hit_1_cal(10 downto 9) <= A_ADD_IN(1 downto 0); --DATA -- saved_data_new_format_hit_1_cal(8 downto 0) <= saved_data_new_format_hit_1_cal(8 downto 0); - + -- elsif (current_state_new_format = save_L_word_state_next_new_format_calibration) then -- saved_data_new_format_hit_1_cal(18 downto 9) <= saved_data_new_format_hit_1_cal(18 downto 9); -- saved_data_new_format_hit_1_cal(8 downto 0) <= A_ADD_IN(8 downto 0); --DATA @@ -1030,13 +1013,13 @@ begin -- behavioral ------------------------------------------------------------------------------- -- 2 HITS IN ONE DATAWORD STRUCTURE : END -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- TEST DATA: START -------------------------------------------------------------------------------- - process (CLK) +------------------------------------------------------------------------------- + process (CLK) begin if rising_edge(CLK) then if (RESET = '1' or reg_data_type_select_in = x"0" or @@ -1060,9 +1043,9 @@ begin -- behavioral -- purpose: built test data and send to fifo ------------------------------------------------------------------------------- process(current_state_test_data, INIT_TDC_READOUT_IN, counter_test_data) - - begin - + + begin + next_data_valid_out_test_data <= '0'; next_debug_register_test_data <= (others => '0'); next_token_tdc_readout_i_test_data <= (others => '0'); @@ -1078,7 +1061,7 @@ begin -- behavioral when idle_state_test_data => next_debug_register_test_data <= x"0"; - next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); + next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); if (INIT_TDC_READOUT_IN = x"1") then next_state_test_data <= send_data_with_valid_test_data; else @@ -1089,33 +1072,33 @@ begin -- behavioral next_debug_register_test_data <= x"1"; up_counter_test_data <= '1'; next_data_valid_out_test_data <= '1'; - next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); - next_state_test_data <= send_data_with_valid_next_test_data; + next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); + next_state_test_data <= send_data_with_valid_next_test_data; when send_data_with_valid_next_test_data => - next_debug_register_test_data <= x"2"; + next_debug_register_test_data <= x"2"; next_data_valid_out_test_data <= '0'; - next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); + next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); next_state_test_data <= check_dataword_number_test_data; when check_dataword_number_test_data => next_debug_register_test_data <= x"3"; next_data_valid_out_test_data <= '0'; - next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); + next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); if (conv_integer(counter_test_data) >= reg_test_data_maximun_word_number) then next_state_test_data <= send_token_state_test_data; else - next_state_test_data <= send_data_with_valid_test_data; + next_state_test_data <= send_data_with_valid_test_data; end if; - ---send token here it is simulated after a constant number of dataword + +--send token here it is simulated after a constant number of dataword when send_token_state_test_data => next_debug_register_test_data <= x"4"; next_token_tdc_readout_i_test_data <= x"1"; clear_counter_test_data <= '1'; - next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); + next_data_bus_out_test_data(15 downto 0) <= std_logic_vector(TO_UNSIGNED(conv_integer(counter_test_data), reg_test_data_maximun_word_number'Length)); next_state_test_data <= idle_state_test_data; - + when others => next_state_test_data <= idle_state_test_data; @@ -1138,8 +1121,8 @@ begin -- behavioral ------------------------------------------------------------------------------- -- TEST DATA: END -------------------------------------------------------------------------------- - +------------------------------------------------------------------------------- + end behavioral; diff --git a/design/tdc_readout_and_trb_interface.vhd b/design/tdc_readout_and_trb_interface.vhd index 1d086ba..c3bb29d 100644 --- a/design/tdc_readout_and_trb_interface.vhd +++ b/design/tdc_readout_and_trb_interface.vhd @@ -1,6 +1,6 @@ ------------------------------------------------------------------------------- -- Attilio Tarantola --- Create Date: 18/08/2007 +-- Create Date: 18/08/2007 -- Description: it it the top level design of: --1) fifo_0 --2) tdc_readout: it builds the dataword @@ -17,6 +17,8 @@ use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; +library work; +use work.mdc_oepb_pack.all; -- synopsys translate_off library ecp2m; use ecp2m.components.all; @@ -25,7 +27,7 @@ use ecp2m.components.all; entity tdc_readout_and_trb_interface is -- generic (width : integer := 16; -- bus_number: std_logic_vector(3 downto 0)); - port ( + port ( CLK : in std_logic; RESET : in std_logic; @@ -35,7 +37,7 @@ entity tdc_readout_and_trb_interface is A_ADD : in std_logic_vector(8 downto 0); A_RESERV : in std_logic; --this is 11 bit of dataword A_AOD : in std_logic; --address or data - A_ACK : in std_logic; + A_ACK : in std_logic; A_DST : in std_logic; A_DRE : out std_logic; TOKEN_IN : in std_logic_vector(3 downto 0); @@ -43,7 +45,7 @@ entity tdc_readout_and_trb_interface is ------------------------------------------------------------------------------- -- tdc_readout_and_trb_interface -------------------------------------------------------------------------------- +------------------------------------------------------------------------------- DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); TOKEN_TO_TRB_OUT : out std_logic; REINIT_ROC1_IN : in std_logic; @@ -53,7 +55,7 @@ entity tdc_readout_and_trb_interface is DEBUG_REGISTER_0 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_1 : out std_logic_vector(7 downto 0); DEBUG_REGISTER_2 : out std_logic_vector(7 downto 0); - + ------------------------------------------------------------------------------- -- trbnet interface ------------------------------------------------------------------------------- @@ -64,7 +66,7 @@ entity tdc_readout_and_trb_interface is LVL1_TRG_INFORMATION_IN : in std_logic_vector(7 downto 0); LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0) := x"00000000"; LVL1_TRG_RELEASE_OUT : out std_logic := '0'; - + --Data Port IPU_NUMBER_IN : in std_logic_vector (15 downto 0); IPU_INFORMATION_IN : in std_logic_vector (7 downto 0); @@ -86,199 +88,78 @@ architecture behavioral of tdc_readout_and_trb_interface is ---------------------------------------------------------------------- -- FSM_HEADER ---------------------------------------------------------------------- - + type state_type is (idle_state, wait_for_token, send_second_header_state, send_data_state, send_data_1_state,busy_header_state); - + signal current_state, next_state : state_type; - + ---------------------------------------------------------------------- -- FSM_FIFO_MULTIPLEXER ---------------------------------------------------------------------- type state_type_fsm_multiplexer is (idle_state_fsm_multiplexer, - wait_for_complete_event_fsm_multiplexer, + wait_for_header_fifo_ready, send_first_and_second_header_state_fsm_multiplexer, - send_data_state_fsm_multiplexer, - end_of_event_transfer_fsm_multiplexer, - dummy_wait_1_fsm_multiplexer, - dummy_wait_2_fsm_multiplexer, - dummy_wait_4_fsm_multiplexer ); - + end_of_event_transfer_fsm_multiplexer); signal current_state_fsm_multiplexer, next_state_fsm_multiplexer : state_type_fsm_multiplexer; - - signal reg_fifo_data_in_i, next_fifo_data_in_i, fifo_data_in_i : std_logic_vector(31 downto 0); - signal reg_fifo_data_out_i, fifo_data_out_i : std_logic_vector(31 downto 0); - signal reg_fifo_write_enable_i, next_fifo_write_enable_i : std_logic; + signal reg_lvl1_busy_i, next_lvl1_busy_i : std_logic; - signal init_tdc_readout_i : std_logic_vector(3 downto 0); - signal reg_debug_register_i, next_debug_register_i : std_logic_vector(7 downto 0); - signal words_in_event_test_data : std_logic_vector(15 downto 0):=(others => '0'); - signal words_in_event_first_header : std_logic_vector(15 downto 0):=(others => '0'); signal words_in_event : std_logic_vector(15 downto 0):=(others => '0'); - signal lvl1_data_counter : std_logic_vector(15 downto 0):=(others => '0'); - signal pulse_a_aod_i : std_logic; signal debug_register_tdc_readout_i : std_logic_vector(3 downto 0); signal reg_trigger_type : std_logic_vector(3 downto 0); signal token_tdc_readout_i : std_logic_vector(3 downto 0); - signal first_header : std_logic_vector(51 downto 0); signal reg_first_header : std_logic_vector(51 downto 0); signal data_tdc_readout_i : std_logic_vector(35 downto 0); signal write_fee_data_fifo_i : std_logic; - signal reg_LVL1_TRG_TYPE_IN : std_logic_vector(3 downto 0); - signal reg_LVL1_TRG_INFORMATION_IN : std_logic_vector(7 downto 0); - signal reg_LVL1_TRG_NUMBER_IN : std_logic_vector(15 downto 0); signal flag_event_counter : std_logic_vector(3 downto 0); signal pulse_init_tdc_readout : std_logic; signal next_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); - signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); + signal reg_debug_register_fsm_multiplexer : std_logic_vector(7 downto 0); signal fee_data_fifo_out_i : std_logic_vector(35 downto 0); signal header_data_fifo_out_i : std_logic_vector(51 downto 0); - signal next_data_to_trb_net : std_logic_vector(31 downto 0); signal data_header_fifo_in_i : std_logic_vector(51 downto 0); signal reg_debug_register_fsm_header, next_debug_register_fsm_header : std_logic_vector(7 downto 0); signal write_header_fifo_i, next_write_header_fifo_i : std_logic; - signal reg_read_fee_data_fifo_i,next_read_fee_data_fifo_i, next_read_header_fifo_i, reg_read_header_fifo_i : std_logic; signal word_count_fee_data_fifo : std_logic_vector(13 downto 0); - signal word_count_header_fifo : std_logic_vector(9 downto 0); - signal reg_lvl1_trg_received, pulse_ipu_start_readout, reg_ipu_read : std_logic; + signal word_count_header_fifo : std_logic_vector(9 downto 0); + signal reg_lvl1_trg_received : std_logic; signal reg_lvl1_trg_type : std_logic_vector(3 downto 0); signal reg_lvl1_trg_code : std_logic_vector(7 downto 0); signal reg_lvl1_trg_information, reg_ipu_information : std_logic_vector(7 downto 0); signal reg_ipu_number : std_logic_vector (15 downto 0); - signal reg_lvl1_error_pattern, next_lvl1_error_pattern : std_logic_vector (31 downto 0); - -- signal reg_ipu_error_pattern, next_ipu_error_pattern : std_logic_vector (31 downto 0); - - signal reg_lvl1_trg_release, next_lvl1_trg_release : std_logic; - signal reg_ipu_data, next_ipu_data : std_logic_vector (31 downto 0); - signal reg_ipu_data_ready, next_ipu_data_ready : std_logic; + signal next_ipu_data : std_logic_vector (31 downto 0); signal reg_ipu_finished, next_ipu_finished : std_logic; - signal how_many_complete_event_in_fifo_counter : std_logic_vector (31 downto 0); - signal pulse_reg_lvl1_trg_received : std_logic; - signal reg_lvl1_trg_number : std_logic_vector(15 downto 0); + signal reg_lvl1_trg_number : std_logic_vector(15 downto 0); signal read_header_fifo,read_fee_data_fifo : std_logic; signal counter_word_read_from_trbnet : std_logic_vector(3 downto 0); - signal clear_counter_word_read_from_trbnet : std_logic; signal reg_flag_in_header : std_logic_vector(3 downto 0); - signal push_read_fee_data_i,push_read_header_data_i : std_logic; signal empty_flag_fee_data_fifo_i, empty_flag_header_data_fifo_i : std_logic; - signal reg_empty_flag_fee_data_fifo_i : std_logic; - signal reg_reg_empty_flag_fee_data_fifo_i : std_logic; - signal last_empty_flag_fee_data_fifo_i : std_logic; - signal pulse_write_header_fifo_i, pulse_write_fee_data_fifo_i : std_logic; - signal counter_pulse_write_header_fifo_i, counter_pulse_write_fee_data_fifo_i : std_logic_vector(15 downto 0); signal counter_token_back : std_logic_vector(31 downto 0); signal full_flag_fee_data_fifo_i,almost_empty_flag_fee_data_fifo_i,almost_full_flag_fee_data_fifo_i : std_logic; signal full_flag_header_data_fifo_i,almost_empty_flag_header_data_fifo_i,almost_full_flag_header_data_fifo_i : std_logic; signal reg_ipu_start_readout_in : std_logic; - signal push_read_fee_data_1_i : std_logic; - signal last_not_empty_flag_fee_data_fifo_i : std_logic; - signal not_empty_flag_fee_data_fifo_i : std_logic; - signal pulse_not_empty_flag_fee_data_fifo_i : std_logic; - signal counter_pulse_not_empty : std_logic_vector(15 downto 0); - - signal last_not_empty_flag_header_data_fifo_i : std_logic; - signal not_empty_flag_header_data_fifo_i : std_logic; - signal pulse_not_empty_flag_header_data_fifo_i : std_logic; - signal counter_pulse_not_empty_header : std_logic_vector(15 downto 0); signal fee_data_fifo_data_valid : std_logic; - signal last_read_fee_data_fifo : std_logic; - signal reg_pseudo_token,next_pseudo_token: std_logic; - - component counter_4bit - port ( - QOUT : out std_logic_vector(3 downto 0); - UP : in std_logic; - CLK : in std_logic; - RESET : in std_logic; - CLR : in std_logic); - end component; - -------------------------------------------------------------------------------- --- Make a pulse from pulse -------------------------------------------------------------------------------- - component edge_to_pulse - port ( - CLOCK : in std_logic; - ENABLE_CLK_IN : in std_logic; - SIGNAL_IN : in std_logic; - PULSE_OUT : out std_logic); - end component; - ---------------------------------------------------------------------------- ---tdc_readout ---------------------------------------------------------------------------- - component tdc_readout - port ( - CLK : in std_logic; - RESET : in std_logic; - A_ADD_IN : in std_logic_vector(8 downto 0); - A_RESERV_IN : in std_logic; --this is 11 bit of dataword - A_AOD_IN : in std_logic; --address or data - A_DST_IN : in std_logic; - TOKEN_IN : in std_logic_vector(3 downto 0); - TOKEN_TDC_READOUT_OUT : out std_logic_vector(3 downto 0); - FLAG_EVENT_COUNTER_IN : in std_logic_vector(3 downto 0); - DATA_BUS_OUT : out std_logic_vector(35 downto 0); --(25 downto 0); --(23 downto 0); - DATA_VALID_OUT : out std_logic; - FULL_FIFO_IN : in std_logic; - INIT_TDC_READOUT_IN : in std_logic_vector(3 downto 0); - DATA_TYPE_SELECT_IN : in std_logic_vector(19 downto 0); --x"0"debug, - --x"1" 2 hit in one word - DEBUG_REGISTER_OUT : out std_logic_vector(3 downto 0)); - end component; - - component fifo_8192depth_36width_dual_thresh_reg_out - port ( - Data : in std_logic_vector(35 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - AmEmptySetThresh : in std_logic_vector(12 downto 0); - AmEmptyClrThresh : in std_logic_vector(12 downto 0); - Q : out std_logic_vector(35 downto 0); - WCNT : out std_logic_vector(13 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); - end component; - - component fifo_fall_through_512depth_52width_reg_out - port ( - Data : in std_logic_vector(51 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - AmEmptySetThresh : in std_logic_vector(8 downto 0); - AmEmptyClrThresh : in std_logic_vector(8 downto 0); - Q : out std_logic_vector(51 downto 0); - WCNT : out std_logic_vector(9 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - AlmostFull : out std_logic); - end component; + signal last_read_header_fifo : std_logic; + signal last2_read_header_fifo : std_logic; + signal last_read_fee_data_fifo : std_logic; + signal last2_read_fee_data_fifo : std_logic; + signal next_ipu_dataready : std_logic; + signal reg_ipu_error_pattern : std_logic_vector(31 downto 0); + signal next_ipu_error_pattern : std_logic_vector(31 downto 0); + signal next_flag_in_header : std_logic_vector(3 downto 0); + signal init_tdc_readout_i : std_logic_vector(3 downto 0); begin -- behavioral - A_ADO_PULSE: edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN =>'1', - SIGNAL_IN => A_AOD, - PULSE_OUT => pulse_a_aod_i); - INIT_TDC_READOUT_IN_0_PULSE : edge_to_pulse port map ( CLOCK => CLK, @@ -286,35 +167,7 @@ begin -- behavioral SIGNAL_IN => INIT_TDC_READOUT_IN(0), PULSE_OUT => pulse_init_tdc_readout); - TRIGGER_RECEIVED_PULSE : edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN => '1', - SIGNAL_IN => reg_lvl1_trg_received, - PULSE_OUT => pulse_reg_lvl1_trg_received); - - IPU_START_READOUT_IN_PULSE : edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN => '1', - SIGNAL_IN => IPU_START_READOUT_IN, - PULSE_OUT => pulse_ipu_start_readout); - PUSH_FIRST_HEADER_DATA_OUT : edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN => '1', - SIGNAL_IN => write_header_fifo_i, - PULSE_OUT => pulse_write_header_fifo_i); - - PUSH_FIRST_FEE_DATA_OUT : edge_to_pulse - port map ( - CLOCK => CLK, - ENABLE_CLK_IN => '1', - SIGNAL_IN => write_fee_data_fifo_i, - PULSE_OUT => pulse_write_fee_data_fifo_i); - - TDC_READOUT_INTERFACE : tdc_readout port map ( CLK => CLK, @@ -335,15 +188,20 @@ TDC_READOUT_INTERFACE : tdc_readout --generator after send --token FULL_FIFO_IN => '0', - DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, + DATA_TYPE_SELECT_IN => DATA_TYPE_SELECT_IN, DEBUG_REGISTER_OUT => debug_register_tdc_readout_i); ------------------------------------------------------------------------------- -- OENP point test token back ------------------------------------------------------------------------------- --data transmission to trbnet terminated - TOKEN_TO_TRB_OUT <= reg_pseudo_token; + TOKEN_TO_TRB_OUT <= token_tdc_readout_i(0); + + +------------------------------------------------------------------------------- +-- FIFO for Data and Header Information +------------------------------------------------------------------------------- FEE_DATA_FIFO : fifo_8192depth_36width_dual_thresh_reg_out port map ( Data => data_tdc_readout_i, @@ -351,8 +209,8 @@ TDC_READOUT_INTERFACE : tdc_readout WrEn => write_fee_data_fifo_i, RdEn => read_fee_data_fifo, Reset => RESET, - AmEmptySetThresh => "0000000000000", - AmEmptyClrThresh => "0000000000000", + AmEmptyThresh => "0000000000100", + AmFullThresh => "1110000000000", Q => fee_data_fifo_out_i, WCNT => word_count_fee_data_fifo, Empty => empty_flag_fee_data_fifo_i, @@ -361,35 +219,7 @@ TDC_READOUT_INTERFACE : tdc_readout AlmostFull => almost_full_flag_fee_data_fifo_i); - not_empty_flag_fee_data_fifo_i <= not empty_flag_fee_data_fifo_i; - - process(CLK, counter_pulse_not_empty) - begin - if rising_edge(CLK) then - if (counter_pulse_not_empty = x"0001") then - pulse_not_empty_flag_fee_data_fifo_i <= '0'; - else - last_not_empty_flag_fee_data_fifo_i <= not_empty_flag_fee_data_fifo_i; - pulse_not_empty_flag_fee_data_fifo_i <= not_empty_flag_fee_data_fifo_i and not (last_not_empty_flag_fee_data_fifo_i); - end if; - end if; - end process; - - process(CLK, pulse_not_empty_flag_fee_data_fifo_i, RESET, token_tdc_readout_i(0) ) - begin - if rising_edge(CLK) then - if (RESET = '1' or token_tdc_readout_i(0) = '1') then - counter_pulse_not_empty <= (others => '0'); - elsif (pulse_not_empty_flag_fee_data_fifo_i = '1') then - counter_pulse_not_empty <= counter_pulse_not_empty + '1'; - end if; - end if; -end process; - - read_fee_data_fifo <= (IPU_READ_IN and reg_read_fee_data_fifo_i) or - pulse_not_empty_flag_fee_data_fifo_i; - -HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out + HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out port map ( Data => reg_first_header, Clock => CLK, @@ -405,198 +235,84 @@ HEADER_FIFO: fifo_fall_through_512depth_52width_reg_out AlmostEmpty => almost_empty_flag_header_data_fifo_i, AlmostFull => almost_full_flag_header_data_fifo_i); -------------------------------------------------------------------------------- --- reg_ipu_read is setted by TRBNET, --- reg_read_header_fifo_i is defined by the state machine -------------------------------------------------------------------------------- -read_header_fifo <= (IPU_READ_IN and reg_read_header_fifo_i) or - push_read_header_data_i or - pulse_not_empty_flag_header_data_fifo_i; -------------------------------------------------------------------------------- - not_empty_flag_header_data_fifo_i <= not empty_flag_header_data_fifo_i; - process(CLK, counter_pulse_not_empty_header) +-- Count number of dataword per event written to fifo + a_add_data_counter : process (CLK) begin if rising_edge(CLK) then - if (counter_pulse_not_empty_header = x"0001") then - pulse_not_empty_flag_header_data_fifo_i <= '0'; - else - last_not_empty_flag_header_data_fifo_i <= not_empty_flag_header_data_fifo_i; - pulse_not_empty_flag_header_data_fifo_i <= not_empty_flag_header_data_fifo_i and not (last_not_empty_flag_header_data_fifo_i); + if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger + words_in_event <= (others => '0'); + elsif (write_fee_data_fifo_i = '1') then + words_in_event <= words_in_event + 1; end if; end if; - end process; - - process(CLK, pulse_not_empty_flag_header_data_fifo_i, RESET, next_ipu_finished ) - begin - if rising_edge(CLK) then - if (RESET = '1' or next_ipu_finished = '1') then - counter_pulse_not_empty_header <= (others => '0'); - elsif (pulse_not_empty_flag_header_data_fifo_i = '1') then - counter_pulse_not_empty_header <= counter_pulse_not_empty_header + '1'; - end if; - end if; -end process; + end process a_add_data_counter; ------------------------------------------------------------------------------- --- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO HEADER --- OUTPUT -------------------------------------------------------------------------------- - process (CLK, RESET, pulse_write_header_fifo_i,counter_pulse_write_header_fifo_i) - begin - if rising_edge(CLK) then - if (RESET = '1') then - push_read_header_data_i <= '0'; - elsif (pulse_write_header_fifo_i = '1' and counter_pulse_write_header_fifo_i = X"0000") then - push_read_header_data_i <= '1'; - else - push_read_header_data_i <= '0'; - end if; - end if; - end process; +-- OUTPUT CONNECTIONS +------------------------------------------------------------------------------- ------------------------------------------------------------------------------ --- register empty flag for fee data ------------------------------------------------------------------------------ - process (CLK, RESET) + PROC_LVL1_OUTPUT : process(CLK) begin if rising_edge(CLK) then - last_empty_flag_fee_data_fifo_i <= empty_flag_fee_data_fifo_i; - reg_empty_flag_fee_data_fifo_i <= last_empty_flag_fee_data_fifo_i; - reg_reg_empty_flag_fee_data_fifo_i <= reg_empty_flag_fee_data_fifo_i; + if RESET = '1' then + LVL1_TRG_RELEASE_OUT <= '0'; + else + LVL1_ERROR_PATTERN_OUT <= x"00000000"; + LVL1_TRG_RELEASE_OUT <= reg_lvl1_busy_i and not next_lvl1_busy_i; + end if; end if; end process; - - process (CLK, pulse_write_header_fifo_i) - begin - if rising_edge(CLK) then - if (RESET = '1') then - counter_pulse_write_header_fifo_i <= (others => '0'); - elsif (pulse_write_header_fifo_i = '1') then - counter_pulse_write_header_fifo_i <= counter_pulse_write_header_fifo_i + 1; - -- elsif (pulse_read_header_fifo = '1') then - else - counter_pulse_write_header_fifo_i <= counter_pulse_write_header_fifo_i; - end if; - end if; - end process; - -------------------------------------------------------------------------------- --- I WANT THE FIRST DATAWORD TO APPEAR AT FIFO DATA --- OUTPUT. this is important when I gather the first event -------------------------------------------------------------------------------- - process (CLK, RESET, pulse_write_fee_data_fifo_i, empty_flag_fee_data_fifo_i) - begin - if rising_edge(CLK) then - if (RESET = '1') then - push_read_fee_data_i <= '0'; - elsif (counter_pulse_write_fee_data_fifo_i >= x"0001") then - push_read_fee_data_i <= '0'; - elsif (pulse_write_fee_data_fifo_i = '1' and counter_pulse_write_fee_data_fifo_i = X"0000") then - push_read_fee_data_i <= '1'; - else - push_read_fee_data_i <= push_read_fee_data_i; - end if; - end if; - end process; + --register later, if needed? + IPU_DATA_OUT <= next_ipu_data(31 downto 0); + IPU_DATAREADY_OUT <= next_ipu_dataready; + IPU_READOUT_FINISHED_OUT <= reg_ipu_finished; + IPU_LENGTH_OUT <= header_data_fifo_out_i(51 downto 36); + IPU_ERROR_PATTERN_OUT <= reg_ipu_error_pattern; - process (CLK, pulse_write_fee_data_fifo_i) - begin - if rising_edge(CLK) then - if (RESET = '1') then - counter_pulse_write_fee_data_fifo_i <= (others => '0'); - elsif (pulse_write_fee_data_fifo_i = '1') then - counter_pulse_write_fee_data_fifo_i <= counter_pulse_write_fee_data_fifo_i + 1; - else - counter_pulse_write_fee_data_fifo_i <= counter_pulse_write_fee_data_fifo_i; - end if; - end if; - end process; -------------------------------------------------------------------------------- --- INPUT CONNECTIONS -------------------------------------------------------------------------------- ------------------------------------------------------------------------------- --- OUTPUT CONNECTIONS +-- Count Tokens ------------------------------------------------------------------------------- - LVL1_ERROR_PATTERN_OUT <= x"00000000"; - LVL1_TRG_RELEASE_OUT <= reg_empty_flag_fee_data_fifo_i and (not next_lvl1_busy_i); - - IPU_DATA_OUT <= next_data_to_trb_net(31 downto 0); - IPU_DATAREADY_OUT <= (fee_data_fifo_data_valid and next_ipu_data_ready) when - (current_state_fsm_multiplexer=send_data_state_fsm_multiplexer) else - reg_ipu_data_ready; - - IPU_READOUT_FINISHED_OUT <= reg_ipu_finished; - - IPU_LENGTH_OUT <= reg_first_header(51 downto 36); - ---test in case no data in fifo (ok if I don't buffer many events) ---set the 18th bit if fifo data is empty - IPU_ERROR_PATTERN_OUT <= x"000" & "0000" & x"0000"; --when (empty_flag_fee_data_fifo_i = '1') else (others => '0');--reg_ipu_error_pattern; - - --- Count number of dataword per event - a_add_data_counter : process (CLK, pulse_init_tdc_readout, pulse_a_aod_i) - begin - if rising_edge(CLK) then - if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger - words_in_event <= (others => '0'); - elsif (pulse_a_aod_i = '1') then - words_in_event <= words_in_event + 1; - else - words_in_event <= words_in_event; - end if; - end if; - end process a_add_data_counter; - --- Count number of dataword in case of test data - a_add_data_counter : process (CLK, pulse_init_tdc_readout, pulse_write_fee_data_fifo_i) - begin - if rising_edge(CLK) then - if (RESET = '1' or pulse_init_tdc_readout = '1') then --reset at every trigger - words_in_event_test_data <= (others => '0'); - elsif (pulse_write_fee_data_fifo_i = '1') then - words_in_event_test_data <= words_in_event_test_data + 1; - else - words_in_event_test_data <= words_in_event_test_data; - end if; - end if; - end process a_add_data_counter; - ---register input - process (CLK, RESET) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_ipu_read <= '0'; - else - reg_ipu_read <= IPU_READ_IN; - end if; - end if; - end process; - --counter number of token back --reset it when the event has been transferred to trbnet - process (CLK, RESET,token_tdc_readout_i, reg_pseudo_token) +process (CLK, RESET,token_tdc_readout_i) begin if rising_edge(CLK) then - if (RESET = '1' or reg_pseudo_token ='1') then + if (RESET = '1') then counter_token_back <= (others => '0'); elsif (token_tdc_readout_i(0) = '1') then counter_token_back <= counter_token_back + 1; - else - counter_token_back <= counter_token_back; end if; end if; end process; - - -- process init_signals + +------------------------------------------------------------------------------- +-- Make headers 36 bit +------------------------------------------------------------------------------- + +--register header +process (CLK) + begin + if rising_edge(CLK) then + reg_first_header <= words_in_event & --(15 downto 0) + flag_event_counter & --(3 downto 0) + "0000" & --(3 downto 0) + reg_lvl1_trg_type & --(3 downto 0) + reg_lvl1_trg_code & --(7 downto 0) + reg_lvl1_trg_number; --(15 downto 0); + end if; + end process; + +------------------------------------------------------------------------------- +--FSM: Control writing to FIFOs +------------------------------------------------------------------------------- + process (CLK) - begin + begin if rising_edge(CLK) then if RESET = '1' then current_state <= idle_state; @@ -612,20 +328,17 @@ end process; end if; end process; -------------------------------------------------------------------------------- --- FSM_HEADER: --- COMBINATORIAL PART: BUILD HEADER AND WRITE THEM IN THE FIFO FOR HEADER, --- MANAGES THE BUSY SIGNAL -------------------------------------------------------------------------------- - process(current_state, reg_lvl1_trg_received, token_tdc_readout_i, - pulse_init_tdc_readout, INIT_TDC_READOUT_IN, almost_empty_flag_fee_data_fifo_i) + + process(current_state, token_tdc_readout_i, reg_first_header, almost_full_flag_fee_data_fifo_i, + INIT_TDC_READOUT_IN) begin - + next_write_header_fifo_i <= '0'; next_debug_register_fsm_header <= (others => '0'); next_lvl1_busy_i <= '0'; - data_header_fifo_in_i <= reg_first_header; - + data_header_fifo_in_i <= reg_first_header; + next_state <= current_state; + case current_state is when idle_state => @@ -633,10 +346,10 @@ end process; next_write_header_fifo_i <= '0'; data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '0'; - if (INIT_TDC_READOUT_IN(0) = '1') then + if (INIT_TDC_READOUT_IN(0) = '1') then next_state <= wait_for_token; else - next_state <= idle_state; + next_state <= idle_state; end if; ----------------------------------------------------------------------- @@ -651,38 +364,36 @@ end process; next_write_header_fifo_i <= '0'; data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '1'; - if (token_tdc_readout_i(0) = '1' and almost_empty_flag_fee_data_fifo_i = '0') then + if (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '0') then next_state <= send_second_header_state; - elsif (token_tdc_readout_i(0) = '1' and almost_empty_flag_fee_data_fifo_i = '1') then + elsif (token_tdc_readout_i(0) = '1' and almost_full_flag_fee_data_fifo_i = '1') then next_state <= busy_header_state; else next_state <= wait_for_token; end if; - + ------------------------------------------------------------------------------- -- SEND HEADER ------------------------------------------------------------------------------- - when send_second_header_state => - next_debug_register_fsm_header <= x"03"; - next_write_header_fifo_i <= '1'; --write in header fifo - data_header_fifo_in_i <= reg_first_header; - next_lvl1_busy_i <= '1'; - next_state <= idle_state; - - --at 6000 dataword in fee data fifo almost_empty_flag_fee_data_fifo_i - --is asserted + when send_second_header_state => + next_debug_register_fsm_header <= x"03"; + next_write_header_fifo_i <= '1'; --write in header fifo + data_header_fifo_in_i <= reg_first_header; + next_lvl1_busy_i <= '1'; + next_state <= idle_state; + when busy_header_state => next_debug_register_fsm_header <= x"04"; next_write_header_fifo_i <= '0'; data_header_fifo_in_i <= reg_first_header; next_lvl1_busy_i <= '1'; - if (almost_empty_flag_fee_data_fifo_i = '0') then - -- clear_counter_pulse_not_empty <= '1'; + if (almost_full_flag_fee_data_fifo_i = '0') then + -- clear_counter_pulse_not_empty <= '1'; next_state <= send_second_header_state; else next_state <= busy_header_state; end if; - + when others => next_debug_register_fsm_header <= x"00"; next_write_header_fifo_i <= '0'; @@ -693,7 +404,7 @@ end process; end process; ----------------------------------------------------------------------------- --- Syncronization and reset FSM_FIFO_MULTIPLEXER +-- Syncronization and reset FSM_FIFO_MULTIPLEXER ----------------------------------------------------------------------------- process (CLK, RESET) begin @@ -701,195 +412,102 @@ end process; if RESET = '1' then current_state_fsm_multiplexer <= idle_state_fsm_multiplexer; reg_debug_register_fsm_multiplexer <= (others => '0'); - reg_read_fee_data_fifo_i <= '0'; - reg_read_header_fifo_i <= '0'; - reg_lvl1_error_pattern <= (others => '0'); - reg_lvl1_trg_release <= '0'; - reg_ipu_data <= (others => '0'); - reg_ipu_data_ready <= '0'; reg_ipu_finished <= '0'; - reg_pseudo_token <= '0'; - -- reg_ipu_error_pattern <= (others => '0'); else current_state_fsm_multiplexer <= next_state_fsm_multiplexer; reg_debug_register_fsm_multiplexer <= next_debug_register_fsm_multiplexer; - reg_read_fee_data_fifo_i <= next_read_fee_data_fifo_i; - reg_read_header_fifo_i <= next_read_header_fifo_i; - reg_lvl1_error_pattern <= next_lvl1_error_pattern; - reg_lvl1_trg_release <= next_lvl1_trg_release; - reg_ipu_data <= next_ipu_data; - reg_ipu_data_ready <= next_ipu_data_ready; + reg_flag_in_header <= next_flag_in_header; + reg_ipu_error_pattern <= next_ipu_error_pattern; reg_ipu_finished <= next_ipu_finished; - reg_pseudo_token <= next_pseudo_token; - -- reg_ipu_error_pattern <= next_ipu_error_pattern; end if; end if; end process; - + ------------------------------------------------------------------------------- -- FSM_FIFO_MULTIPLEXER: -- this fsm multiplex data and header into TRB net entity. ------------------------------------------------------------------------------- - process(current_state_fsm_multiplexer, reg_lvl1_trg_received, - how_many_complete_event_in_fifo_counter, - counter_word_read_from_trbnet, INIT_TDC_READOUT_IN, - word_count_header_fifo, fee_data_fifo_out_i, reg_ipu_read, - reg_reg_empty_flag_fee_data_fifo_i,reg_flag_in_header,read_header_fifo, - pulse_ipu_start_readout,counter_token_back, reg_ipu_start_readout_in, - header_data_fifo_out_i ) - +process(current_state_fsm_multiplexer, header_data_fifo_out_i, reg_ipu_start_readout_in, + empty_flag_header_data_fifo_i, last_read_header_fifo, IPU_READ_IN, reg_flag_in_header, + fee_data_fifo_out_i, fee_data_fifo_data_valid, last_read_fee_data_fifo, + empty_flag_fee_data_fifo_i, reg_ipu_error_pattern) begin - + next_state_fsm_multiplexer <= current_state_fsm_multiplexer; next_debug_register_fsm_multiplexer <= (others => '0'); - next_data_to_trb_net <= (others => '0'); - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - - next_lvl1_error_pattern <= (others => '0'); - next_lvl1_trg_release <= '0'; - next_ipu_data <= (others => '0'); - next_ipu_data_ready <= '0'; - next_ipu_finished <= '0'; - clear_counter_word_read_from_trbnet <= '0'; - push_read_fee_data_1_i <= '0'; - next_pseudo_token <= '0'; - -- next_ipu_error_pattern <= (others => '0'); - - case current_state_fsm_multiplexer is + read_fee_data_fifo <= '0'; + read_header_fifo <= '0'; + next_ipu_dataready <= '0'; + next_ipu_finished <= '0'; + next_flag_in_header<= reg_flag_in_header; + next_ipu_data <= header_data_fifo_out_i(31 downto 0); + next_ipu_error_pattern <= reg_ipu_error_pattern; + case current_state_fsm_multiplexer is when idle_state_fsm_multiplexer => + next_ipu_error_pattern <= (others => '0'); next_debug_register_fsm_multiplexer <= x"00"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; - next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); ---start readout if IPU requests comes - if (pulse_ipu_start_readout = '1') then - next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer; - else - next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; - end if; -------------------------------------------------------------------------------- --- WAIT for at least one complete event in the fifo. If I have one complete event --- the header fifo must containt at least 1 word (the first dataword is written --- at the beginning, after the token comes back). This check is important only --- if one event is written and the same event is read -------------------------------------------------------------------------------- - when wait_for_complete_event_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"01"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; - next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); ---here I wait only when the first token from the first event is back ---in future I need to see there is one event at least in the header fifo ---check if header is in the header fifo - if (empty_flag_header_data_fifo_i = '0') then - --if (conv_integer(counter_token_back) >= 1) then - next_state_fsm_multiplexer <= dummy_wait_4_fsm_multiplexer; - else - next_state_fsm_multiplexer <= wait_for_complete_event_fsm_multiplexer; + if reg_ipu_start_readout_in = '1' and empty_flag_header_data_fifo_i = '0' then + read_header_fifo <= '1'; + next_state_fsm_multiplexer <= wait_for_header_fifo_ready; end if; - when dummy_wait_4_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"02"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; - next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); - next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer; -------------------------------------------------------------------------------- --- FIRST HEADER and SECOND : Connect header_fifo to trbnet. --- The first and second headers can be sended. --- I check that the TRBNET read only ONE word than I switch the --- to the data fifo -------------------------------------------------------------------------------- - when send_first_and_second_header_state_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"03"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '1'; - next_ipu_data_ready <= not IPU_READ_IN or not reg_ipu_data_ready; --trbnet can read - next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); --header_fifo - - if (read_header_fifo = '1') then --this read correspond to the header - --read from trbnet - --next_read_header_fifo_i <= '0'; - --next_ipu_data_ready <= '0'; - -- push_read_fee_data_1_i <= '1'; - next_state_fsm_multiplexer <= dummy_wait_1_fsm_multiplexer; - else + when wait_for_header_fifo_ready => + if last_read_header_fifo = '1' then next_state_fsm_multiplexer <= send_first_and_second_header_state_fsm_multiplexer; end if; ---here register header flag - when dummy_wait_1_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"04"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; --trbnet cannot read - next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); + when send_first_and_second_header_state_fsm_multiplexer => + next_ipu_data <= header_data_fifo_out_i(31 downto 0); + next_flag_in_header <= header_data_fifo_out_i(35 downto 32); + next_ipu_dataready <= '1'; + if IPU_READ_IN = '1' then next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; - -------------------------------------------------------------------------------- --- Connect fee_data_fifo to trbnet. --- I leave connected till the flag change to next event -------------------------------------------------------------------------------- - when send_data_state_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"05"; - next_read_fee_data_fifo_i <= '1'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '1'; --trbnet can read - next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); --data_fifo - --chenge state if event you read from the fifo is different from the - --event you are sending or if the fifo does not contain anymore data. --- if ( (fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header ) or - if (reg_empty_flag_fee_data_fifo_i = '1') then - next_ipu_data_ready <= '0'; - next_read_fee_data_fifo_i <= '0'; - next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; - else - next_state_fsm_multiplexer <= send_data_state_fsm_multiplexer; + if fee_data_fifo_data_valid = '0' then + read_fee_data_fifo <= '1'; end if; - - --stay if no tok back and fifo empty for + end if; + + when send_data_state_fsm_multiplexer => + next_ipu_data <= fee_data_fifo_out_i(31 downto 0); + next_ipu_dataready <= fee_data_fifo_data_valid; + read_fee_data_fifo <= IPU_READ_IN or not fee_data_fifo_data_valid; + + if (empty_flag_fee_data_fifo_i = '1' and last_read_fee_data_fifo = '0' and fee_data_fifo_data_valid = '0') + or ( fee_data_fifo_out_i(35 downto 32) /= reg_flag_in_header and fee_data_fifo_data_valid = '1') then + next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; + next_ipu_dataready <= '0'; + next_ipu_finished <= '1'; + end if; + when end_of_event_transfer_fsm_multiplexer => - next_debug_register_fsm_multiplexer <= x"07"; - next_read_fee_data_fifo_i <= '0'; - next_read_header_fifo_i <= '0'; - next_ipu_data_ready <= '0'; - next_data_to_trb_net <= fee_data_fifo_out_i(31 downto 0); - next_ipu_finished <= '1'; --transmission terminated - clear_counter_word_read_from_trbnet <= '1'; - push_read_fee_data_1_i <= '1'; - - if (reg_ipu_start_readout_in = '0') then - next_pseudo_token <= '1'; - next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; - else - next_state_fsm_multiplexer <= end_of_event_transfer_fsm_multiplexer; - end if; - - when others => - next_debug_register_fsm_multiplexer <= x"08"; - next_data_to_trb_net <= header_data_fifo_out_i(31 downto 0); - next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; + if reg_ipu_start_readout_in = '0' then + next_state_fsm_multiplexer <= idle_state_fsm_multiplexer; + end if; + end case; end process; -process (CLK) -begin - if rising_edge(CLK) then - last_read_fee_data_fifo <= read_fee_data_fifo; - if last_read_fee_data_fifo = '1' and last_empty_flag_fee_data_fifo_i = '0' then - fee_data_fifo_data_valid <= '1'; - elsif IPU_READ_IN = '1' and current_state_fsm_multiplexer = send_data_state_fsm_multiplexer then - fee_data_fifo_data_valid <= '0'; - end if; - end if; - -end process; - + PROC_FIFO_DATA_VALID : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + fee_data_fifo_data_valid <= '0'; + else + if last_read_fee_data_fifo = '1' then + fee_data_fifo_data_valid <= '1'; + elsif IPU_READ_IN = '1' and next_ipu_dataready = '1' then + fee_data_fifo_data_valid <= '0'; + end if; + end if; + end if; + end process; + + +------------------------------------------------------------------------------- + + + ------------------------------------------------------------------------------- -- EVENT FLAG GENERATOR: -- For each event I generate a flag (4 bits), which will be used to distinguish @@ -902,17 +520,19 @@ end process; flag_event_counter <= (others => '0'); elsif (pulse_init_tdc_readout = '1') then flag_event_counter <= flag_event_counter + 1; - else - flag_event_counter <= flag_event_counter; end if; end if; end process; +--use bigger width, compare to trbnet trigger number + ------------------------------------------------------------------------------- -- I see which trigger has been processed and I store it. I use this -- information in the first dataword ------------------------------------------------------------------------------- - process (CLK) +init_tdc_readout_i <= x"0"; + +process (CLK) begin if rising_edge(CLK) then if RESET = '1' then @@ -921,81 +541,34 @@ begin reg_trigger_type <= x"1"; elsif init_tdc_readout_i = x"9" then --calibration trigger reg_trigger_type <= x"9"; - else - reg_trigger_type <= reg_trigger_type; end if; end if; end process; -------------------------------------------------------------------------------- --- Make headers 36 bit -------------------------------------------------------------------------------- -first_header <= words_in_event_first_header & --(15 downto 0) - flag_event_counter & --(3 downto 0) - "0000" & --(3 downto 0) - reg_lvl1_trg_type & --(3 downto 0) - reg_lvl1_trg_code & --(7 downto 0) - reg_lvl1_trg_number; --(15 downto 0) - ---number of dataword are counted in differet way if test data is enabled -words_in_event_first_header <= words_in_event_test_data when (DATA_TYPE_SELECT_IN(3 downto 0) = x"2") - else words_in_event; - ---register header -process (CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_first_header<= (others => '0'); - else - reg_first_header <= first_header; - end if; - end if; - end process; - -DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); -------------------------------------------------------------------------------- --- EVENT COMPLETE in FIFO: --- the counter is used to check how many event complete are stored in the fifo. ------------------------------------------------------------------------------ -process(CLK, RESET, pulse_init_tdc_readout, token_tdc_readout_i) -begin - if (rising_edge(CLK)) then - if (RESET = '1') then - how_many_complete_event_in_fifo_counter <= (others => '0'); - elsif (( not(pulse_init_tdc_readout) and token_tdc_readout_i(0)) = '1') then - how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter + 1; ---decrese by one every event is read out --- elsif then --- how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter - 1; - else - how_many_complete_event_in_fifo_counter <= how_many_complete_event_in_fifo_counter; - end if; - end if; -end process; + ------------------------------------------------------------------------------- -- REGISTER INPUT TRBNET SIGNALS ------------------------------------------------------------------------------- -process(CLK, RESET) -begin - if rising_edge(CLK) then - if RESET = '1' then - -- LVL1 trigger APL - reg_lvl1_trg_type <= (others => '0'); - reg_lvl1_trg_received <= '0'; - reg_lvl1_trg_number <= (others => '0'); - reg_lvl1_trg_code <= (others => '0'); - reg_lvl1_trg_information <= (others => '0'); - --Data Port - reg_ipu_number <= (others => '0'); - reg_ipu_information <= (others => '0'); - --start strobe - reg_ipu_start_readout_in <= '0'; - -- reg_ipu_read <= '0'; - else - --reg_ipu_read <= IPU_READ_IN; - -- LVL1 trigger APL +-- process(CLK, RESET) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- -- LVL1 trigger APL +-- reg_lvl1_trg_type <= (others => '0'); +-- reg_lvl1_trg_received <= '0'; +-- reg_lvl1_trg_number <= (others => '0'); +-- reg_lvl1_trg_code <= (others => '0'); +-- reg_lvl1_trg_information <= (others => '0'); +-- --Data Port +-- reg_ipu_number <= (others => '0'); +-- reg_ipu_information <= (others => '0'); +-- --start strobe +-- reg_ipu_start_readout_in <= '0'; +-- -- reg_ipu_read <= '0'; +-- else +-- --reg_ipu_read <= IPU_READ_IN; +-- -- LVL1 trigger APL reg_lvl1_trg_type <= LVL1_TRG_TYPE_IN; --4bit reg_lvl1_trg_received <= LVL1_TRG_RECEIVED_IN; reg_lvl1_trg_number <= LVL1_TRG_NUMBER_IN;--16bit @@ -1006,42 +579,41 @@ begin reg_ipu_information <= IPU_INFORMATION_IN; --start strobe reg_ipu_start_readout_in <= IPU_START_READOUT_IN; - end if; - end if; -end process; +-- end if; +-- end if; +-- end process; ------------------------------------------------------------------------------- -- PROCESS to count how many word the TRB net reads from the FIFO_HADER ------------------------------------------------------------------------------- -process (CLK, RESET, clear_counter_word_read_from_trbnet, reg_ipu_read, current_state_fsm_multiplexer) -begin +process (CLK) +begin if (rising_edge(CLK)) then - if (RESET = '1' or clear_counter_word_read_from_trbnet = '1') then + if (RESET = '1') then counter_word_read_from_trbnet <= (others => '0'); - elsif (reg_ipu_read = '1' and - current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then - counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1; - else - counter_word_read_from_trbnet <= counter_word_read_from_trbnet; - end if; + elsif read_fee_data_fifo = '1' then + counter_word_read_from_trbnet <= counter_word_read_from_trbnet + 1; + end if; end if; end process; ------------------------------------------------------------------------------- --- READ and REGISTER event number +-- Keep track of read operations ----------------------------------------------------------------------------- -process (CLK, RESET, current_state_fsm_multiplexer,header_data_fifo_out_i) -begin - if (rising_edge(CLK)) then - if (RESET = '1') then - reg_flag_in_header <= (others => '0'); - elsif (current_state_fsm_multiplexer = send_first_and_second_header_state_fsm_multiplexer) then - reg_flag_in_header <= header_data_fifo_out_i(35 downto 32); - else - reg_flag_in_header <= reg_flag_in_header; - end if; - end if; -end process; + + PROC_REG_READ_SIGS : process(CLK) + begin + if rising_edge(CLK) then + last_read_header_fifo <= read_header_fifo; + last2_read_header_fifo <= last_read_header_fifo; + + last_read_fee_data_fifo <= read_fee_data_fifo and not empty_flag_fee_data_fifo_i; + last2_read_fee_data_fifo <= last_read_fee_data_fifo; + + end if; + end process; + + ------------------------------------------------------------------------------- -- read data fifo @@ -1049,9 +621,20 @@ end process; ------------------------------------------------------------------------------- --- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS. +-- AVERAGE NUMBER OF DATAWORDS PER EVENT ON THIS BUS. +------------------------------------------------------------------------------- + + + + + +------------------------------------------------------------------------------- +-- Debug ------------------------------------------------------------------------------- +DEBUG_REGISTER_0 <= x"0" & reg_debug_register_fsm_multiplexer(3 downto 0); + + end behavioral; diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index ecfa2ae..cada1eb 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -647,38 +647,36 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler ------------------------------------------------------------------------------- -- DATA MULTIPLEXER for INOUT DST, AOD,TAD ------------------------------------------------------------------------------- - process(TAD,TAOD, TDST,direction_data_line_out_i, + process(direction_data_line_out_i, a_add_configuration_i, a_aod_configuration_i, a_dst_configuration_i) begin - ---DATA TACKING - if direction_data_line_out_i = x"1" then - a_add_data_i <= TAD; - a_aod_data_i <= TAOD; - a_dst_data_i <= TDST; - TAOD <= 'Z'; - TDST <= 'Z'; - TAD <= (others => 'Z'); - ---CONFIGURATION or CALIBRATION - elsif(direction_data_line_out_i = x"D") then - + --CONFIGURATION or CALIBRATION + if (direction_data_line_out_i = x"D") then TAOD <= a_aod_configuration_i; TDST <= a_dst_configuration_i; - TAD <= a_add_configuration_i; - - a_add_data_i <= (others => '0'); - a_aod_data_i <= '0'; - a_dst_data_i <= '0'; + TAD <= a_add_configuration_i; + --DATA TAKING else - --DATA TACKING - a_add_data_i <= TAD; - a_aod_data_i <= TAOD; - a_dst_data_i <= TDST; TAOD <= 'Z'; TDST <= 'Z'; - TAD <= (others => 'Z'); + TAD <= (others => 'Z'); + end if; + end process; + + + process(CLK_100) + begin + if rising_edge(CLK_100) then + if direction_data_line_out_i = x"D" then + a_add_data_i <= (others => '0'); + a_aod_data_i <= '0'; + a_dst_data_i <= '0'; + else + a_add_data_i <= TAD; + a_aod_data_i <= TAOD; + a_dst_data_i <= TDST; + end if; end if; end process; -- 2.43.0