From 8a7369e69233e3b3bd7d8863769ed24bc0cd0eb2 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Thu, 26 Feb 2015 14:10:59 +0100 Subject: [PATCH] adding timings for synplify --- ADC/trb3_periph_adc.sdc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/ADC/trb3_periph_adc.sdc b/ADC/trb3_periph_adc.sdc index 4642741..f9e90a3 100644 --- a/ADC/trb3_periph_adc.sdc +++ b/ADC/trb3_periph_adc.sdc @@ -19,6 +19,8 @@ define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -c define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6 define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7 define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_tx_ch} -freq 100 -clockgroup default_clkgroup_8 +define_clock {n:pll_in200_out80_gen_80MHz_THE_ADC_REF_0|CLKOP_inferred_clock} -name {n:pll_in200_out80_gen_80MHz_THE_ADC_REF_0|CLKOP_inferred_clock} -freq 80 -clockgroup default_clkgroup_9 +define_clock {n:pll_in200_out80_gen_80MHz_THE_ADC_REF|CLKOP_inferred_clock} -name {n:pll_in200_out80_gen_80MHz_THE_ADC_REF|CLKOP_inferred_clock} -freq 80 -clockgroup default_clkgroup_10 # # Clock to Clock -- 2.43.0