From 8abfab09165d8a9e600eab413e9c5c7d29393e29 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 7 Aug 2024 16:21:04 +0200 Subject: [PATCH] few updates to ADC design, incl block memory --- adc/source/adc_addon.vhd | 5 +++- adc/source/adc_processor.vhd | 43 +++++++++++++++++++++++------------ adc_standalone/config.vhd | 6 +++++ adc_standalone/trb5sc_cts.prj | 1 + adc_standalone/trb5sc_cts.vhd | 19 +++++++++++++++- 5 files changed, 57 insertions(+), 17 deletions(-) diff --git a/adc/source/adc_addon.vhd b/adc/source/adc_addon.vhd index 656fed9..9acd029 100644 --- a/adc/source/adc_addon.vhd +++ b/adc/source/adc_addon.vhd @@ -40,6 +40,7 @@ end entity; architecture arch of adc_addon is + attribute syn_ramstyle : string; @@ -82,7 +83,9 @@ architecture arch of adc_addon is signal baseline_reset_value : brv_arr_t := (others => (others => (others => '0'))); type config_mem_t is array(0 to 1023) of std_logic_vector(31 downto 0); - signal config_mem : config_mem_t; + signal config_mem : config_mem_t; + attribute syn_ramstyle of config_mem : signal is "block_ram"; + signal read_mem : std_logic; signal config_mem_out : std_logic_vector(31 downto 0); diff --git a/adc/source/adc_processor.vhd b/adc/source/adc_processor.vhd index 44aab61..8e9aa53 100644 --- a/adc/source/adc_processor.vhd +++ b/adc/source/adc_processor.vhd @@ -51,11 +51,11 @@ attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute syn_hier of arch : architecture is "hard"; -type ram_t is array (0 to 1023) of unsigned(23 downto 0); +type ram_t is array (0 to 1023) of std_logic_vector(23 downto 0); signal ram_write : std_logic := '0'; signal ram_read : std_logic := '0'; signal ram_data_in : unsigned(23 downto 0); -signal ram_data_out : unsigned(23 downto 0); +signal ram_data_out : std_logic_vector(23 downto 0); signal reg_ram_data_out : unsigned(23 downto 0); signal baseline : unsigned(19 downto 0); @@ -66,7 +66,7 @@ signal ram_rd_move_value : unsigned( 9 downto 0) := (others => '0'); signal ram_wr_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_rd_pointer : unsigned( 9 downto 0) := (others => '0'); signal ram_count : unsigned( 9 downto 0) := (others => '0'); -signal ram_clear : std_logic; +signal ram_clear : std_logic := '0'; signal last_ramread : std_logic; signal ram_valid : std_logic; signal ram_rd_move : std_logic; @@ -77,9 +77,7 @@ signal reg2_ram_remove : std_logic; signal trigger_gen : std_logic; signal stop_writing : std_logic; -signal ram : ram_t := (others => (others => '0')); -attribute syn_ramstyle of ram : signal is "block_ram"; - +-- signal ram : ram_t := (others => (others => '0')); signal after_trg_cnt : unsigned(11 downto 0) := (others => '1'); signal stop_writing_rdo : std_logic := '0'; @@ -115,6 +113,7 @@ signal psa_data_i : std_logic_vector(8 downto 0); signal psa_ram_out_t : std_logic_vector(8 downto 0); signal psa_ram_out : std_logic_vector(8 downto 0); signal psa_ram : psa_ram_t; +attribute syn_ramstyle of psa_ram : signal is "block_ram"; type psa_state_t is (PSA_IDLE, PSA_START_CHANNEL, PSA_WAIT_RAM, PSA_WAIT_RAM2, PSA_CALC, PSA_WAITWRITE, PSA_WAITWRITE2, PSA_DOWRITE, PSA_FINISH, PSA_WAIT_AFTER); type rdo_state_t is (RDO_IDLE, READ_CHANNEL, NEXT_BLOCK, RDO_DONE, RDO_FINISH, RDO_WAIT_AFTER); @@ -257,16 +256,30 @@ end process; end process; - + THE_RAM: entity work.ram_36x1k_oreg + port map ( + WrAddress => std_logic_vector(ram_wr_pointer), + RdAddress => std_logic_vector(ram_rd_pointer), + Data(23 downto 0) => std_logic_vector(ram_data_in), + WE => ram_write, + RdClock => CLK, + RdClockEn => '1', + Reset => '0', + WrClock => CLK, + WrClockEn => '1', + Q(23 downto 0) => ram_data_out + ); - PROC_RAM : process begin - wait until rising_edge(CLK); - if ram_write = '1' then - ram(to_integer(ram_wr_pointer)) <= ram_data_in; - end if; - ram_data_out <= ram(to_integer(ram_rd_pointer)); - reg_ram_data_out <= ram_data_out; - end process; + reg_ram_data_out <= unsigned(ram_data_out); + + -- PROC_RAM : process begin + -- wait until rising_edge(CLK); + -- if ram_write = '1' then + -- ram(to_integer(ram_wr_pointer)) <= std_logic_vector(ram_data_in); + -- end if; + -- ram_data_out <= unsigned(ram(to_integer(ram_rd_pointer))); + -- reg_ram_data_out <= ram_data_out; + -- end process; proc_buffer_write : process begin wait until rising_edge(CLK); diff --git a/adc_standalone/config.vhd b/adc_standalone/config.vhd index f6137bb..9c2ad45 100644 --- a/adc_standalone/config.vhd +++ b/adc_standalone/config.vhd @@ -96,6 +96,12 @@ package config is constant IS_UPLINK : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); constant IS_DOWNLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); constant IS_UPLINK_ONLY : hub_ct := (0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + + -- constant INTERFACE_NUM : integer := 0; + -- constant IS_UPLINK : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + -- constant IS_DOWNLINK : hub_ct := (1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + -- constant IS_UPLINK_ONLY : hub_ct := (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); + ------------------------------------------------------------------------------ diff --git a/adc_standalone/trb5sc_cts.prj b/adc_standalone/trb5sc_cts.prj index 81fd75c..a02061f 100644 --- a/adc_standalone/trb5sc_cts.prj +++ b/adc_standalone/trb5sc_cts.prj @@ -286,6 +286,7 @@ add_file -vhdl -lib work "../../trb3/cts/source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts_trigger.vhd" add_file -vhdl -lib work "../../trb3/cts/source/cts.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/ram_36x1k_oreg/ram_36x1k_oreg.vhd" add_file -vhdl -lib work "../adc/source/adc_package.vhd" add_file -vhdl -lib work "../adc/cores/fifo_cdt_70x16/fifo_cdt_70x16.vhd" add_file -vhdl -lib work "../adc/cores/mulaccsub3/mulaccsub3.vhd" diff --git a/adc_standalone/trb5sc_cts.vhd b/adc_standalone/trb5sc_cts.vhd index 4712e1a..fcd6f6c 100644 --- a/adc_standalone/trb5sc_cts.vhd +++ b/adc_standalone/trb5sc_cts.vhd @@ -213,6 +213,8 @@ architecture arch of trb5sc_cts is signal cts_ipu_status_bits : std_logic_vector(31 downto 0); signal cts_ipu_busy : std_logic; + signal reset_via_gbe_long, reset_via_gbe_timer, last_reset_via_gbe_long, make_reset : std_logic; + begin @@ -224,7 +226,7 @@ begin THE_CLOCK_RESET : entity work.clock_reset_handler port map( CLOCK_IN => CLK_200, - RESET_FROM_NET => reset_via_gbe,--med2int(0).stat_op(13), + RESET_FROM_NET => make_reset,--med2int(0).stat_op(13), SEND_RESET_IN => '0', --med2int(0).stat_op(15), BUS_RX => bustc_rx, @@ -254,6 +256,21 @@ begin CLK_A <= clk_50; + + proc_make_reset : process begin + wait until rising_edge(clk_sys); + if(reset_via_gbe = '1') then + reset_via_gbe_long <= '1'; + reset_via_gbe_timer <= '1'; + end if; + if timer.tick_us = '1' then + reset_via_gbe_timer <= '0'; + reset_via_gbe_long <= reset_via_gbe_timer; + end if; + last_reset_via_gbe_long <= reset_via_gbe_long; + make_reset <= last_reset_via_gbe_long and not reset_via_gbe_long; + end process; + --------------------------------------------------------------------------- -- GbE --------------------------------------------------------------------------- -- 2.43.0