From 8c14dcda08b5ced2fc358302729af910735da232 Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Thu, 8 Feb 2018 18:22:49 +0100 Subject: [PATCH] w.i.p., IF --- media_interfaces/sync/rx_control.vhd | 66 ++++++++++++++++++++++++++-- media_interfaces/sync/tx_control.vhd | 20 ++++++--- 2 files changed, 77 insertions(+), 9 deletions(-) diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 2a04916..c8409c2 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -47,7 +47,7 @@ end entity; architecture rx_control_arch of rx_control is -type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR); +type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, MAKE_RESET, START_RETR, GET_CRC); signal rx_state : rx_state_t; signal rx_state_bits : std_logic_vector(3 downto 0); signal rx_packet_num : std_logic_vector(2 downto 0); @@ -68,6 +68,8 @@ signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; signal got_link_ready_i : std_logic := '0'; signal start_retr_i : std_logic; signal start_retr_pos_i : std_logic_vector(7 downto 0); +signal req_retr_i : std_logic; +signal req_retr_pos_i : std_logic_vector(7 downto 0); signal rx_dlm_i : std_logic; signal rx_dlm_word_i : std_logic_vector(7 downto 0); @@ -80,6 +82,12 @@ signal reg_rx_k_in : std_logic; signal reset_cnt : unsigned(7 downto 0); +signal crc_reset : std_logic; +signal crc_q : std_logic_vector(7 downto 0); +signal crc_en : std_logic; +signal crc_data : std_logic_vector(7 downto 0); + + begin ---------------------------------------------------------------------- @@ -131,6 +139,22 @@ THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); +---------------------------------------------------------------------- +-- CRC +---------------------------------------------------------------------- + +crc_data <= reg_rx_data_in when rising_edge(CLK_200); + +CRC_CALC : trb_net_CRC8 + port map( + CLK => CLK_200, + RESET => crc_reset, + CLK_EN => crc_en, + DATA_IN => crc_data, + CRC_OUT => crc_q, + CRC_match => open + ); + ---------------------------------------------------------------------- -- Read incoming data ---------------------------------------------------------------------- @@ -138,9 +162,12 @@ PROC_RX_FSM : process begin wait until rising_edge(CLK_200); ct_fifo_write <= '0'; start_retr_i <= '0'; + req_retr_i <= '0'; rx_dlm_i <= '0'; idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); idle_hist_i(0) <= got_link_ready_i; + crc_en <= '0'; + crc_reset <= '0'; case rx_state is when SLEEP => @@ -162,6 +189,7 @@ PROC_RX_FSM : process begin case reg_rx_data_in is when K_IDLE => rx_state <= GET_IDLE; + crc_reset <= '1'; when K_RST => rx_state <= MAKE_RESET; reset_cnt <= x"00"; @@ -169,10 +197,13 @@ PROC_RX_FSM : process begin rx_state <= GET_DLM; when K_REQ => rx_state <= START_RETR; + when K_EOP => + rx_state <= GET_CRC; when others => null; end case; else rx_state <= GET_DATA; + crc_en <= '1'; end if; when GET_IDLE => @@ -188,6 +219,7 @@ PROC_RX_FSM : process begin when GET_DATA => rx_state_bits <= x"4"; + crc_en <= '1'; if reg_rx_k_in = '0' then next_sop <= '0'; rx_data(15 downto 8)<= reg_rx_data_in; @@ -198,6 +230,13 @@ PROC_RX_FSM : process begin else rx_state <= SLEEP; end if; + + when GET_CRC => --TODO: mitzaehlen, of CRC nach 5 16-Bit-Paketen kommt + crc_reset <= '1'; + rx_state <= FIRST; + if (crc_q = reg_rx_data_in) then + req_retr_i <= '1'; + end if; when GET_DLM => rx_state_bits <= x"5"; @@ -249,13 +288,34 @@ reg_rx_k_in <= RX_K_IN when rising_edge(CLK_200); ---------------------------------------------------------------------- GOT_LINK_READY <= got_link_ready_i; -START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200); +--START_RETRANSMIT_OUT <= start_retr_i when rising_edge(CLK_200); +START_RETRANSMIT_OUT_SYNC : pulse_sync + port map( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_IN, + PULSE_A_IN => start_retr_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => START_RETRANSMIT_OUT + ); + START_POSITION_OUT <= start_retr_pos_i when rising_edge(CLK_200); RX_DLM <= rx_dlm_i when rising_edge(CLK_200); RX_DLM_WORD <= rx_dlm_word_i when rising_edge(CLK_200); -REQUEST_RETRANSMIT_OUT <= '0'; --TODO: check incoming data +--REQUEST_RETRANSMIT_OUT <= req_retr_i when rising_edge(CLK_200); -- '0'; --TODO: check incoming data +REQUEST_RETRANSMIT_OUT_SYNC : pulse_sync + port map( + CLK_A_IN => CLK_200, + RESET_A_IN => RESET_IN, + PULSE_A_IN => req_retr_i, + CLK_B_IN => CLK_100, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => REQUEST_RETRANSMIT_OUT + ); + + REQUEST_POSITION_OUT <= x"00"; --TODO: check incoming data SEND_LINK_RESET_OUT <= send_link_reset_i when rising_edge(CLK_200); diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 64cb3ee..fdbc1a8 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -46,7 +46,7 @@ architecture arch of tx_control is type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H, - SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, + SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10 signal current_state : state_t; signal state_bits : std_logic_vector(3 downto 0); @@ -242,6 +242,7 @@ begin TX_CD_OUT <= '0'; debug_sending_dlm <= '0'; first_idle <= '1'; +-- load_read_pointer_i <= '0'; case current_state is when SEND_IDLE_L => TX_DATA_OUT <= K_IDLE; @@ -278,14 +279,16 @@ begin when SEND_CHKSUM_H => TX_DATA_OUT <= crc_q; - + when SEND_START_L => TX_DATA_OUT <= K_BGN; TX_K_OUT <= '1'; current_state <= SEND_START_H; when SEND_START_H => - TX_DATA_OUT <= std_logic_vector(ram_read_addr); + --TX_DATA_OUT <= std_logic_vector(ram_read_addr); + TX_DATA_OUT <= x"FF"; + current_state <= SEND_DATA_L; when SEND_REQUEST_L => TX_DATA_OUT <= K_REQ; @@ -315,7 +318,7 @@ begin when others => current_state <= SEND_IDLE_L; end case; - + if current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or @@ -330,6 +333,7 @@ begin current_state <= SEND_REQUEST_L; elsif make_restart_i = '1' then current_state <= SEND_START_L; +-- load_read_pointer_i <= '1'; elsif send_dlm_i = '1' then current_state <= SEND_DLM_L; elsif (load_eop = '1') then @@ -447,13 +451,16 @@ begin if RESET_IN = '1' then make_restart_i <= '0'; restart_position_i <= (others => '0'); + load_read_pointer_i <= '0'; elsif rising_edge(CLK_200) then + load_read_pointer_i <= '0'; if tx_allow_qtx = '0' then make_restart_i <= '0'; restart_position_i <= (others => '0'); elsif start_retransmit_i = '1' then make_restart_i <= '1'; restart_position_i <= restart_position_q; + load_read_pointer_i <= '1'; --prepare load at the same time elsif current_state = SEND_START_L then make_restart_i <= '0'; elsif current_state = SEND_START_H then @@ -461,7 +468,7 @@ begin end if; end if; end process; - + --Store DLM send THE_STORE_DLM_PROC : process(CLK_200, RESET_IN) begin @@ -478,7 +485,8 @@ begin end if; end process; - load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; + -- load_read_pointer_i <= '1' when current_state = SEND_START_L else '0'; + -- ---in this scheme the load pointer comes too late -- gk 05.10.10 crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0'; -- 2.43.0