From 8cad8f8eaf0c1bcf14427c406d65b09411f62e58 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Wed, 12 Feb 2014 18:24:22 +0100
Subject: [PATCH] added description for the anyInputTrigger module

---
 trb3/TriggerModule.tex | 27 +++++++++++++++++++++++++++
 trb3/main.tex          |  5 ++++-
 2 files changed, 31 insertions(+), 1 deletion(-)
 create mode 100644 trb3/TriggerModule.tex

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
new file mode 100644
index 0000000..fd00264
--- /dev/null
+++ b/trb3/TriggerModule.tex
@@ -0,0 +1,27 @@
+The trigger module can be used to forward any input of a peripheral FPGA via the central FPGA to 
+the CTS. E.g. any input to any TDC can be used to generate the trigger in the CTS.
+
+The VHDL code is available in \files{base/code/input\_to\_trigger\_logic.vhd}
+
+\paragraph*{Setup}
+The trigger module can feature up to 32 input signals and up to 16 independent outputs.
+An extension to 64 inputs (matching the maximal number of inputs to the TDC) is foreseen but not 
+yet implemented.
+For each output, any of the connected inputs can be enabled or disabled as well as been inverted 
+individually. The output is an 'or' of all enabled inputs. The peripheral FPGA can send four 
+outputs to the central FPGA. Depending on the AddOn used, additional outputs can be routed to free 
+I/O pins if available.
+
+The central FPGA contains the same trigger logic to combine the four signals from each of the 
+peripheral FPGAs to one common signal forwarded on the trigger output on the RJ-45 connector 
+(middle pair). Additional signals can be forward to the AddOn connector of the central FPGA, e.g. 
+to one of the RJ-45 sockets on the CTS-AddOn.
+
+\paragraph*{SlowControl}
+Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has four 
+configuration registers. The first one contains a bit mask to enable individual inputs. The second 
+one contains a bitmask to invert individual input signals. The other two registers are reserved for 
+future extensions. 
+
+In case of four outputs configured, registers 0xcf00, 0xcf04, 0xcf08 and 0xcf0c contain the enable 
+bit mask and registers 0xcf01, 0xcf05, 0xcf09 and 0xcf0d contain the inverter bits.
\ No newline at end of file
diff --git a/trb3/main.tex b/trb3/main.tex
index dc46671..a91230e 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -186,9 +186,12 @@
       \input{TdcDataFormat}
     \subsection{Slow Control Registers}
       \input{TdcSlowControl}
-\newpage
+  \clearpage
+  \section{Additional Modules}
     \subsection{DAC Programming}
       \input{DacProgramming}
+    \subsection{Forward inputs for trigger}
+      \input{TriggerModule}      
 
   \clearpage
   \section[GbE Data Read-out]{GbE Data Read-out\footnote{This space to be filled by Grzegorz Korcyl. At the moment: read the TrbNet manual.}}
-- 
2.43.0