From 8cbd5eec1aa3a8d854006dbec645cb3b38a96dfe Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 21 Dec 2012 13:03:38 +0000 Subject: [PATCH] *** empty log message *** --- base/cores/pll_in200_out100.ipx | 8 +- base/cores/pll_in200_out100.lpc | 10 +- base/cores/pll_in200_out100.vhd | 24 +- base/trb3_components.vhd | 1 + cts/compile_central_frankfurt.pl | 5 +- cts/trb3_central.prj | 22 +- cts/trb3_central.vhd | 680 +++++++++++++------- cts/trb3_central_constraints.lpf | 6 +- tdc_releases/tdc_v1.1.1/TDC.vhd | 24 +- tdc_releases/tdc_v1.1.1/tdc_constraints.lpf | 86 +-- wasa/compile_padiwa_frankfurt.pl | 3 +- wasa/compile_panda_dirc_wasa_frankfurt.pl | 2 +- wasa/sim/machxo.mpf | 51 +- wasa/trb3_periph_padiwa.prj | 33 +- wasa/trb3_periph_padiwa.vhd | 8 +- 15 files changed, 601 insertions(+), 362 deletions(-) diff --git a/base/cores/pll_in200_out100.ipx b/base/cores/pll_in200_out100.ipx index 3130d36..65763d1 100644 --- a/base/cores/pll_in200_out100.ipx +++ b/base/cores/pll_in200_out100.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/pll_in200_out100.lpc b/base/cores/pll_in200_out100.lpc index 4901c30..4aa89ef 100644 --- a/base/cores/pll_in200_out100.lpc +++ b/base/cores/pll_in200_out100.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PLL -CoreRevision=5.2 +CoreRevision=5.3 ModuleName=pll_in200_out100 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=08/24/2011 -Time=15:08:55 +Date=12/14/2012 +Time=18:35:48 [Parameters] Verilog=0 @@ -54,10 +54,10 @@ U_KFrq=50 OK_Tol=0.0 KFrq=200.000000 ClkRst=0 -PCDR=0 +PCDR=1 FINDELA=0 VcoRate= -Bandwidth= +Bandwidth=1.485393 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 diff --git a/base/cores/pll_in200_out100.vhd b/base/cores/pll_in200_out100.vhd index b9cef7a..583c729 100644 --- a/base/cores/pll_in200_out100.vhd +++ b/base/cores/pll_in200_out100.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.2 ---/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 200 -fclkok_tol 0.0 -norst -noclkok2 -e +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.3 +--/d/jspc29/lattice/diamond/2.0/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypassk -fclkop 100 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -fclkok 200 -fclkok_tol 0.0 -use_rst -noclkok2 -bw -e --- Wed Aug 24 15:08:55 2011 +-- Fri Dec 14 18:35:48 2012 library IEEE; use IEEE.std_logic_1164.all; @@ -14,6 +14,7 @@ use ecp3.components.all; entity pll_in200_out100 is port ( CLK: in std_logic; + RESET: in std_logic; CLKOP: out std_logic; CLKOK: out std_logic; LOCK: out std_logic); @@ -77,14 +78,13 @@ begin PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 2, FIN=> "200.000000") - port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, - RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, - DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, - DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, - DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, - FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, - CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, - CLKINTFB=>CLKFB_t); + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, + DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, + DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, + FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>CLKOK, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t); CLKOP <= CLKOP_t; end Structure; diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 158ac13..86b8316 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -13,6 +13,7 @@ package trb3_components is component pll_in200_out100 port ( CLK : in std_logic; + RESET : in std_logic := '0'; CLKOP : out std_logic; --100 MHz CLKOK : out std_logic; --200 MHz, bypass LOCK : out std_logic diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index 795e62e..2b63979 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -9,7 +9,9 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_central"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; +#my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; +#my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -39,6 +41,7 @@ my $SPEEDGRADE="8"; #create full lpf file system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.1.1/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 18259f1..0784f9b 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -223,7 +223,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" - +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "source/cts_pkg.vhd" add_file -vhdl -lib work "source/cts_fifo.vhd" add_file -vhdl -lib work "source/cts_trg_input.vhd" @@ -232,6 +232,26 @@ add_file -vhdl -lib work "source/cts_trg_pseudorand_pulser.vhd" add_file -vhdl -lib work "source/cts_trigger.vhd" add_file -vhdl -lib work "source/cts.vhd" +############### +#Change path to tdc release also in compile script! +############### +#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd" + add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 329b05b..a0d158a 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -176,185 +176,234 @@ entity trb3_central is end entity; architecture trb3_central_arch of trb3_central is - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - - signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL - signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. - signal clear_i : std_logic; - signal reset_i : std_logic; - signal GSR_N : std_logic; - attribute syn_keep of GSR_N : signal is true; - attribute syn_preserve of GSR_N : signal is true; - - --FPGA Test - signal time_counter, time_counter2 : unsigned(31 downto 0); - - --Media Interface - signal med_stat_op : std_logic_vector (5*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); - signal med_stat_debug : std_logic_vector (5*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0); - signal med_data_out : std_logic_vector (5*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (5*3-1 downto 0); - signal med_dataready_out : std_logic_vector (5*1-1 downto 0); - signal med_read_out : std_logic_vector (5*1-1 downto 0); - signal med_data_in : std_logic_vector (5*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (5*3-1 downto 0); - signal med_dataready_in : std_logic_vector (5*1-1 downto 0); - signal med_read_in : std_logic_vector (5*1-1 downto 0); - - --Hub - signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0); - signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0); - signal my_address : std_logic_vector (16-1 downto 0); - signal regio_addr_out : std_logic_vector (16-1 downto 0); - signal regio_read_enable_out : std_logic; - signal regio_write_enable_out : std_logic; - signal regio_data_out : std_logic_vector (32-1 downto 0); - signal regio_data_in : std_logic_vector (32-1 downto 0); - signal regio_dataready_in : std_logic; - signal regio_no_more_data_in : std_logic; - signal regio_write_ack_in : std_logic; - signal regio_unknown_addr_in : std_logic; - signal regio_timeout_out : std_logic; - - signal spictrl_read_en : std_logic; - signal spictrl_write_en : std_logic; - signal spictrl_data_in : std_logic_vector(31 downto 0); - signal spictrl_addr : std_logic; - signal spictrl_data_out : std_logic_vector(31 downto 0); - signal spictrl_ack : std_logic; - signal spictrl_busy : std_logic; - signal spimem_read_en : std_logic; - signal spimem_write_en : std_logic; - signal spimem_data_in : std_logic_vector(31 downto 0); - signal spimem_addr : std_logic_vector(5 downto 0); - signal spimem_data_out : std_logic_vector(31 downto 0); - signal spimem_ack : std_logic; - - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal gbe_cts_number : std_logic_vector(15 downto 0); - signal gbe_cts_code : std_logic_vector(7 downto 0); - signal gbe_cts_information : std_logic_vector(7 downto 0); - signal gbe_cts_start_readout : std_logic; - signal gbe_cts_readout_type : std_logic_vector(3 downto 0); - signal gbe_cts_readout_finished : std_logic; - signal gbe_cts_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_data : std_logic_vector(15 downto 0); - signal gbe_fee_dataready : std_logic; - signal gbe_fee_read : std_logic; - signal gbe_fee_status_bits : std_logic_vector(31 downto 0); - signal gbe_fee_busy : std_logic; - - signal stage_stat_regs : std_logic_vector (31 downto 0); - signal stage_ctrl_regs : std_logic_vector (31 downto 0); - - signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); - signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); - signal mb_stat_reg_read : std_logic; - signal mb_stat_reg_write : std_logic; - signal mb_stat_reg_ack : std_logic; - signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used - signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); - signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); - signal mb_ip_mem_read : std_logic; - signal mb_ip_mem_write : std_logic; - signal mb_ip_mem_ack : std_logic; - signal ip_cfg_mem_clk : std_logic; - signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); - signal ip_cfg_mem_data : std_logic_vector(31 downto 0); - signal ctrl_reg_addr : std_logic_vector(15 downto 0); - signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); - signal gbe_stp_data : std_logic_vector(31 downto 0); - signal gbe_stp_reg_ack : std_logic; - signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); - signal gbe_stp_reg_read : std_logic; - signal gbe_stp_reg_write : std_logic; - signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); - - signal debug : std_logic_vector(63 downto 0); - - signal next_reset, make_reset_via_network_q : std_logic; - signal reset_counter : std_logic_vector(11 downto 0); - signal link_ok : std_logic; - - signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); - signal gsc_init_read, gsc_reply_read : std_logic; - signal gsc_init_dataready, gsc_reply_dataready : std_logic; - signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); - signal gsc_busy : std_logic; - signal mc_unique_id : std_logic_vector(63 downto 0); - signal trb_reset_in : std_logic; - signal reset_via_gbe : std_logic; - signal reset_via_gbe_delayed : std_logic_vector(2 downto 0); - signal reset_i_temp : std_logic; - - signal cts_rdo_trigger : std_logic; - signal cts_rdo_trg_data_valid : std_logic; - signal cts_rdo_valid_timing_trg : std_logic; - signal cts_rdo_valid_notiming_trg : std_logic; - signal cts_rdo_invalid_trg : std_logic; - - signal cts_rdo_trg_status_bits, - cts_rdo_trg_status_bits_cts, - cts_rdo_trg_status_bits_additional: std_logic_vector(31 downto 0) := (others => '0'); - signal cts_rdo_data : std_logic_vector(31 downto 0); - signal cts_rdo_write : std_logic; - signal cts_rdo_finished : std_logic; - - signal cts_ext_trigger : std_logic; - signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); - signal cts_ext_control : std_logic_vector(31 downto 0); - signal cts_ext_debug : std_logic_vector(31 downto 0); - - signal cts_rdo_additional_data : std_logic_vector(31 downto 0); - signal cts_rdo_additional_write : std_logic := '0'; - signal cts_rdo_additional_finished : std_logic := '0'; - - signal cts_trg_send : std_logic; - signal cts_trg_type : std_logic_vector(3 downto 0); - signal cts_trg_number : std_logic_vector(15 downto 0); - signal cts_trg_information : std_logic_vector(23 downto 0); - signal cts_trg_code : std_logic_vector(7 downto 0); - signal cts_trg_status_bits : std_logic_vector(31 downto 0); - signal cts_trg_busy : std_logic; - - signal cts_ipu_send : std_logic; - signal cts_ipu_type : std_logic_vector(3 downto 0); - signal cts_ipu_number : std_logic_vector(15 downto 0); - signal cts_ipu_information : std_logic_vector(7 downto 0); - signal cts_ipu_code : std_logic_vector(7 downto 0); - signal cts_ipu_status_bits : std_logic_vector(31 downto 0); - signal cts_ipu_busy : std_logic; - - signal cts_regio_addr : std_logic_vector(15 downto 0); - signal cts_regio_read : std_logic; - signal cts_regio_write : std_logic; - signal cts_regio_data_out : std_logic_vector(31 downto 0); - signal cts_regio_data_in : std_logic_vector(31 downto 0); - signal cts_regio_dataready : std_logic; - signal cts_regio_no_more_data : std_logic; - signal cts_regio_write_ack : std_logic; - signal cts_regio_unknown_addr : std_logic; - - signal cts_trigger_out : std_logic; - signal external_send_reset : std_logic; - signal timer_ticks : std_logic_vector(1 downto 0); - - signal trigger_busy_i : std_logic; - signal trigger_in_buf_i : std_logic_vector(3 downto 0); - - signal select_tc : std_logic_vector(31 downto 0); - signal select_tc_data_in : std_logic_vector(31 downto 0); - signal select_tc_write : std_logic; - signal select_tc_read : std_logic; - signal select_tc_ack : std_logic; + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL + signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL + signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clear_i : std_logic; + signal reset_i : std_logic; + signal GSR_N : std_logic; + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + --FPGA Test + signal time_counter, time_counter2 : unsigned(31 downto 0); + + --Media Interface + signal med_stat_op : std_logic_vector (5*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); + signal med_stat_debug : std_logic_vector (5*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0); + signal med_data_out : std_logic_vector (5*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (5*3-1 downto 0); + signal med_dataready_out : std_logic_vector (5*1-1 downto 0); + signal med_read_out : std_logic_vector (5*1-1 downto 0); + signal med_data_in : std_logic_vector (5*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (5*3-1 downto 0); + signal med_dataready_in : std_logic_vector (5*1-1 downto 0); + signal med_read_in : std_logic_vector (5*1-1 downto 0); + + --Hub + signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0); + signal common_ctrl_regs : std_logic_vector (std_COMCTRLREG*32-1 downto 0); + signal my_address : std_logic_vector (16-1 downto 0); + signal regio_addr_out : std_logic_vector (16-1 downto 0); + signal regio_read_enable_out : std_logic; + signal regio_write_enable_out : std_logic; + signal regio_data_out : std_logic_vector (32-1 downto 0); + signal regio_data_in : std_logic_vector (32-1 downto 0); + signal regio_dataready_in : std_logic; + signal regio_no_more_data_in : std_logic; + signal regio_write_ack_in : std_logic; + signal regio_unknown_addr_in : std_logic; + signal regio_timeout_out : std_logic; + + signal spictrl_read_en : std_logic; + signal spictrl_write_en : std_logic; + signal spictrl_data_in : std_logic_vector(31 downto 0); + signal spictrl_addr : std_logic; + signal spictrl_data_out : std_logic_vector(31 downto 0); + signal spictrl_ack : std_logic; + signal spictrl_busy : std_logic; + signal spimem_read_en : std_logic; + signal spimem_write_en : std_logic; + signal spimem_data_in : std_logic_vector(31 downto 0); + signal spimem_addr : std_logic_vector(5 downto 0); + signal spimem_data_out : std_logic_vector(31 downto 0); + signal spimem_ack : std_logic; + + signal spi_bram_addr : std_logic_vector(7 downto 0); + signal spi_bram_wr_d : std_logic_vector(7 downto 0); + signal spi_bram_rd_d : std_logic_vector(7 downto 0); + signal spi_bram_we : std_logic; + + signal gbe_cts_number : std_logic_vector(15 downto 0); + signal gbe_cts_code : std_logic_vector(7 downto 0); + signal gbe_cts_information : std_logic_vector(7 downto 0); + signal gbe_cts_start_readout : std_logic; + signal gbe_cts_readout_type : std_logic_vector(3 downto 0); + signal gbe_cts_readout_finished : std_logic; + signal gbe_cts_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_data : std_logic_vector(15 downto 0); + signal gbe_fee_dataready : std_logic; + signal gbe_fee_read : std_logic; + signal gbe_fee_status_bits : std_logic_vector(31 downto 0); + signal gbe_fee_busy : std_logic; + + signal stage_stat_regs : std_logic_vector (31 downto 0); + signal stage_ctrl_regs : std_logic_vector (31 downto 0); + + signal mb_stat_reg_data_wr : std_logic_vector(31 downto 0); + signal mb_stat_reg_data_rd : std_logic_vector(31 downto 0); + signal mb_stat_reg_read : std_logic; + signal mb_stat_reg_write : std_logic; + signal mb_stat_reg_ack : std_logic; + signal mb_ip_mem_addr : std_logic_vector(15 downto 0); -- only [7:0] in used + signal mb_ip_mem_data_wr : std_logic_vector(31 downto 0); + signal mb_ip_mem_data_rd : std_logic_vector(31 downto 0); + signal mb_ip_mem_read : std_logic; + signal mb_ip_mem_write : std_logic; + signal mb_ip_mem_ack : std_logic; + signal ip_cfg_mem_clk : std_logic; + signal ip_cfg_mem_addr : std_logic_vector(7 downto 0); + signal ip_cfg_mem_data : std_logic_vector(31 downto 0); + signal ctrl_reg_addr : std_logic_vector(15 downto 0); + signal gbe_stp_reg_addr : std_logic_vector(15 downto 0); + signal gbe_stp_data : std_logic_vector(31 downto 0); + signal gbe_stp_reg_ack : std_logic; + signal gbe_stp_reg_data_wr : std_logic_vector(31 downto 0); + signal gbe_stp_reg_read : std_logic; + signal gbe_stp_reg_write : std_logic; + signal gbe_stp_reg_data_rd : std_logic_vector(31 downto 0); + + signal debug : std_logic_vector(63 downto 0); + + signal next_reset, make_reset_via_network_q : std_logic; + signal reset_counter : std_logic_vector(11 downto 0); + signal link_ok : std_logic; + + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + signal mc_unique_id : std_logic_vector(63 downto 0); + signal trb_reset_in : std_logic; + signal reset_via_gbe : std_logic; + signal reset_via_gbe_delayed : std_logic_vector(2 downto 0); + signal reset_i_temp : std_logic; + + signal cts_rdo_trigger : std_logic; + signal cts_rdo_trg_data_valid : std_logic; + signal cts_rdo_valid_timing_trg : std_logic; + signal cts_rdo_valid_notiming_trg : std_logic; + signal cts_rdo_invalid_trg : std_logic; + + signal cts_rdo_trg_status_bits, + cts_rdo_trg_status_bits_cts, + cts_rdo_trg_status_bits_additional: std_logic_vector(31 downto 0) := (others => '0'); + signal cts_rdo_data : std_logic_vector(31 downto 0); + signal cts_rdo_write : std_logic; + signal cts_rdo_finished : std_logic; + + signal cts_ext_trigger : std_logic; + signal cts_ext_status : std_logic_vector(31 downto 0) := (others => '0'); + signal cts_ext_control : std_logic_vector(31 downto 0); + signal cts_ext_debug : std_logic_vector(31 downto 0); + + signal cts_rdo_additional_data : std_logic_vector(31 downto 0); + signal cts_rdo_additional_write : std_logic := '0'; + signal cts_rdo_additional_finished : std_logic := '0'; + + signal cts_trg_send : std_logic; + signal cts_trg_type : std_logic_vector(3 downto 0); + signal cts_trg_number : std_logic_vector(15 downto 0); + signal cts_trg_information : std_logic_vector(23 downto 0); + signal cts_trg_code : std_logic_vector(7 downto 0); + signal cts_trg_status_bits : std_logic_vector(31 downto 0); + signal cts_trg_busy : std_logic; + + signal cts_ipu_send : std_logic; + signal cts_ipu_type : std_logic_vector(3 downto 0); + signal cts_ipu_number : std_logic_vector(15 downto 0); + signal cts_ipu_information : std_logic_vector(7 downto 0); + signal cts_ipu_code : std_logic_vector(7 downto 0); + signal cts_ipu_status_bits : std_logic_vector(31 downto 0); + signal cts_ipu_busy : std_logic; + + signal cts_regio_addr : std_logic_vector(15 downto 0); + signal cts_regio_read : std_logic; + signal cts_regio_write : std_logic; + signal cts_regio_data_out : std_logic_vector(31 downto 0); + signal cts_regio_data_in : std_logic_vector(31 downto 0); + signal cts_regio_dataready : std_logic; + signal cts_regio_no_more_data : std_logic; + signal cts_regio_write_ack : std_logic; + signal cts_regio_unknown_addr : std_logic; + + signal cts_trigger_out : std_logic; + signal external_send_reset : std_logic; + signal timer_ticks : std_logic_vector(1 downto 0); + + signal trigger_busy_i : std_logic; + signal trigger_in_buf_i : std_logic_vector(3 downto 0); + + signal select_tc : std_logic_vector(31 downto 0); + signal select_tc_data_in : std_logic_vector(31 downto 0); + signal select_tc_write : std_logic; + signal select_tc_read : std_logic; + signal select_tc_ack : std_logic; + + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_data_in : std_logic_vector(31 downto 0); + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; + + signal srb_read_en : std_logic; + signal srb_write_en : std_logic; + signal srb_data_in : std_logic_vector(31 downto 0); + signal srb_addr : std_logic_vector(6 downto 0); + signal srb_data_out : std_logic_vector(31 downto 0); + signal srb_data_ready : std_logic; + signal srb_invalid : std_logic; + +-- signal lhb_read_en : std_logic; +-- signal lhb_write_en : std_logic; +-- signal lhb_data_in : std_logic_vector(31 downto 0); +-- signal lhb_addr : std_logic_vector(6 downto 0); +-- signal lhb_data_out : std_logic_vector(31 downto 0); +-- signal lhb_data_ready : std_logic; +-- signal lhb_invalid : std_logic; + + signal esb_read_en : std_logic; + signal esb_write_en : std_logic; + signal esb_data_in : std_logic_vector(31 downto 0); + signal esb_addr : std_logic_vector(6 downto 0); + signal esb_data_out : std_logic_vector(31 downto 0); + signal esb_data_ready : std_logic; + signal esb_invalid : std_logic; + + signal fwb_read_en : std_logic; + signal fwb_write_en : std_logic; + signal fwb_data_in : std_logic_vector(31 downto 0); + signal fwb_addr : std_logic_vector(6 downto 0); + signal fwb_data_out : std_logic_vector(31 downto 0); + signal fwb_data_ready : std_logic; + signal fwb_invalid : std_logic; + + signal tdc_ctrl_read : std_logic; + signal last_tdc_ctrl_read : std_logic; + signal tdc_ctrl_write : std_logic; + signal tdc_ctrl_addr : std_logic_vector(1 downto 0); + signal tdc_ctrl_data_in : std_logic_vector(31 downto 0); + signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); + signal tdc_ctrl_reg : std_logic_vector(4*32-1 downto 0); + component mbs_vulom_recv is port( @@ -385,7 +434,7 @@ architecture trb3_central_arch of trb3_central is begin -- MBS Module - THE_CMB: mbs_vulom_recv + THE_MBS: mbs_vulom_recv port map ( CLK => clk_100_i, RESET_IN => reset_i, @@ -411,7 +460,7 @@ begin trigger_in_buf_i(1 downto 0) <= CLK_EXT; trigger_in_buf_i(3 downto 2) <= TRIGGER_EXT(3 downto 2); - THE_CTS: CTS + THE_CTS: CTS generic map ( EXTERNAL_TRIGGER_ID => X"60", --, fill in trigger logic enumeration id of external trigger logic TRIGGER_INPUT_COUNT => 4, @@ -530,6 +579,7 @@ process begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_LEFT, + RESET => '0', CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock @@ -883,9 +933,9 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 0, others => 0) + PORT_NUMBER => 11, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300", 10 => x"c800", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 9, 5 => 0, 6 => 7, 7 => 5, 8 => 7, 9 => 7, 10 => 2, others => 0) ) port map( CLK => clk_100_i, @@ -927,58 +977,129 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(1) => '0', BUS_UNKNOWN_ADDR_IN(1) => '0', - -- third one - IP config memory - BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, - BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, - BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, - BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, - BUS_DATAREADY_IN(2) => mb_ip_mem_ack, - BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, - BUS_NO_MORE_DATA_IN(2) => '0', - BUS_UNKNOWN_ADDR_IN(2) => '0', - - -- gk 22.04.10 - -- gbe setup - BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, - BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, - BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, - BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, - BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, - BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, - BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, - BUS_NO_MORE_DATA_IN(3) => '0', - BUS_UNKNOWN_ADDR_IN(3) => '0', - - -- CTS - BUS_ADDR_OUT(5*16-1 downto 4*16) => cts_regio_addr, - BUS_DATA_OUT(5*32-1 downto 4*32) => cts_regio_data_out, - BUS_READ_ENABLE_OUT(4) => cts_regio_read, - BUS_WRITE_ENABLE_OUT(4) => cts_regio_write, - BUS_TIMEOUT_OUT(4) => open, - BUS_DATA_IN(5*32-1 downto 4*32) => cts_regio_data_in, - BUS_DATAREADY_IN(4) => cts_regio_dataready, - BUS_WRITE_ACK_IN(4) => cts_regio_write_ack, - BUS_NO_MORE_DATA_IN(4) => '0', - BUS_UNKNOWN_ADDR_IN(4) => cts_regio_unknown_addr, - - -- Trigger and Clock Manager Settings - BUS_ADDR_OUT(6*16-1 downto 5*16) => open, - BUS_DATA_OUT(6*32-1 downto 5*32) => select_tc_data_in, - BUS_READ_ENABLE_OUT(5) => select_tc_read, - BUS_WRITE_ENABLE_OUT(5) => select_tc_write, - BUS_TIMEOUT_OUT(5) => open, - BUS_DATA_IN(6*32-1 downto 5*32) => select_tc, - BUS_DATAREADY_IN(5) => select_tc_ack, - BUS_WRITE_ACK_IN(5) => select_tc_ack, - BUS_NO_MORE_DATA_IN(5) => '0', - BUS_UNKNOWN_ADDR_IN(5) => '0', - - STAT_DEBUG => open + -- third one - IP config memory + BUS_ADDR_OUT(3*16-1 downto 2*16) => mb_ip_mem_addr, + BUS_DATA_OUT(3*32-1 downto 2*32) => mb_ip_mem_data_wr, + BUS_READ_ENABLE_OUT(2) => mb_ip_mem_read, + BUS_WRITE_ENABLE_OUT(2) => mb_ip_mem_write, + BUS_TIMEOUT_OUT(2) => open, + BUS_DATA_IN(3*32-1 downto 2*32) => mb_ip_mem_data_rd, + BUS_DATAREADY_IN(2) => mb_ip_mem_ack, + BUS_WRITE_ACK_IN(2) => mb_ip_mem_ack, + BUS_NO_MORE_DATA_IN(2) => '0', + BUS_UNKNOWN_ADDR_IN(2) => '0', + + -- gk 22.04.10 + -- gbe setup + BUS_ADDR_OUT(4*16-1 downto 3*16) => gbe_stp_reg_addr, + BUS_DATA_OUT(4*32-1 downto 3*32) => gbe_stp_reg_data_wr, + BUS_READ_ENABLE_OUT(3) => gbe_stp_reg_read, + BUS_WRITE_ENABLE_OUT(3) => gbe_stp_reg_write, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(4*32-1 downto 3*32) => gbe_stp_reg_data_rd, + BUS_DATAREADY_IN(3) => gbe_stp_reg_ack, + BUS_WRITE_ACK_IN(3) => gbe_stp_reg_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => '0', + + -- CTS + BUS_ADDR_OUT(5*16-1 downto 4*16) => cts_regio_addr, + BUS_DATA_OUT(5*32-1 downto 4*32) => cts_regio_data_out, + BUS_READ_ENABLE_OUT(4) => cts_regio_read, + BUS_WRITE_ENABLE_OUT(4) => cts_regio_write, + BUS_TIMEOUT_OUT(4) => open, + BUS_DATA_IN(5*32-1 downto 4*32) => cts_regio_data_in, + BUS_DATAREADY_IN(4) => cts_regio_dataready, + BUS_WRITE_ACK_IN(4) => cts_regio_write_ack, + BUS_NO_MORE_DATA_IN(4) => '0', + BUS_UNKNOWN_ADDR_IN(4) => cts_regio_unknown_addr, + + -- Trigger and Clock Manager Settings + BUS_ADDR_OUT(6*16-1 downto 5*16) => open, + BUS_DATA_OUT(6*32-1 downto 5*32) => select_tc_data_in, + BUS_READ_ENABLE_OUT(5) => select_tc_read, + BUS_WRITE_ENABLE_OUT(5) => select_tc_write, + BUS_TIMEOUT_OUT(5) => open, + BUS_DATA_IN(6*32-1 downto 5*32) => select_tc, + BUS_DATAREADY_IN(5) => select_tc_ack, + BUS_WRITE_ACK_IN(5) => select_tc_ack, + BUS_NO_MORE_DATA_IN(5) => '0', + BUS_UNKNOWN_ADDR_IN(5) => '0', + + --HitRegisters + BUS_READ_ENABLE_OUT(6) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(6) => hitreg_write_en, + BUS_DATA_OUT(6*32+31 downto 6*32) => open, + BUS_ADDR_OUT(6*16+6 downto 6*16) => hitreg_addr, + BUS_ADDR_OUT(6*16+15 downto 6*16+7) => open, + BUS_TIMEOUT_OUT(6) => open, + BUS_DATA_IN(6*32+31 downto 6*32) => hitreg_data_out, + BUS_DATAREADY_IN(6) => hitreg_data_ready, + BUS_WRITE_ACK_IN(6) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', + BUS_UNKNOWN_ADDR_IN(6) => hitreg_invalid, + --Status Registers + BUS_READ_ENABLE_OUT(7) => srb_read_en, + BUS_WRITE_ENABLE_OUT(7) => srb_write_en, + BUS_DATA_OUT(7*32+31 downto 7*32) => open, + BUS_ADDR_OUT(7*16+6 downto 7*16) => srb_addr, + BUS_ADDR_OUT(7*16+15 downto 7*16+7) => open, + BUS_TIMEOUT_OUT(7) => open, + BUS_DATA_IN(7*32+31 downto 7*32) => srb_data_out, + BUS_DATAREADY_IN(7) => srb_data_ready, + BUS_WRITE_ACK_IN(7) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', + BUS_UNKNOWN_ADDR_IN(7) => srb_invalid, + --Encoder Start Registers + BUS_READ_ENABLE_OUT(8) => esb_read_en, + BUS_WRITE_ENABLE_OUT(8) => esb_write_en, + BUS_DATA_OUT(8*32+31 downto 8*32) => open, + BUS_ADDR_OUT(8*16+6 downto 8*16) => esb_addr, + BUS_ADDR_OUT(8*16+15 downto 8*16+7) => open, + BUS_TIMEOUT_OUT(8) => open, + BUS_DATA_IN(8*32+31 downto 8*32) => esb_data_out, + BUS_DATAREADY_IN(8) => esb_data_ready, + BUS_WRITE_ACK_IN(8) => '0', + BUS_NO_MORE_DATA_IN(8) => '0', + BUS_UNKNOWN_ADDR_IN(8) => esb_invalid, + --Fifo Write Registers + BUS_READ_ENABLE_OUT(9) => fwb_read_en, + BUS_WRITE_ENABLE_OUT(9) => fwb_write_en, + BUS_DATA_OUT(9*32+31 downto 9*32) => open, + BUS_ADDR_OUT(9*16+6 downto 9*16) => fwb_addr, + BUS_ADDR_OUT(9*16+15 downto 9*16+7) => open, + BUS_TIMEOUT_OUT(9) => open, + BUS_DATA_IN(9*32+31 downto 9*32) => fwb_data_out, + BUS_DATAREADY_IN(9) => fwb_data_ready, + BUS_WRITE_ACK_IN(9) => '0', + BUS_NO_MORE_DATA_IN(9) => '0', + BUS_UNKNOWN_ADDR_IN(9) => fwb_invalid, + --TDC config registers + BUS_READ_ENABLE_OUT(10) => tdc_ctrl_read, + BUS_WRITE_ENABLE_OUT(10) => tdc_ctrl_write, + BUS_DATA_OUT(10*32+31 downto 10*32) => tdc_ctrl_data_in, + BUS_ADDR_OUT(10*16+1 downto 10*16) => tdc_ctrl_addr, + BUS_ADDR_OUT(10*16+15 downto 10*16+2)=> open, + BUS_TIMEOUT_OUT(10) => open, + BUS_DATA_IN(10*32+31 downto 10*32) => tdc_ctrl_data_out, + BUS_DATAREADY_IN(10) => last_tdc_ctrl_read, + BUS_WRITE_ACK_IN(10) => tdc_ctrl_write, + BUS_NO_MORE_DATA_IN(10) => '0', + BUS_UNKNOWN_ADDR_IN(10) => '0', + + STAT_DEBUG => open ); + +PROC_TDC_CTRL_REG : process begin + wait until rising_edge(clk_100_i); + tdc_ctrl_data_out <= tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32); + last_tdc_ctrl_read <= tdc_ctrl_read; + if tdc_ctrl_read = '1' then + tdc_ctrl_reg(to_integer(unsigned(tdc_ctrl_addr))*32+31 downto to_integer(unsigned(tdc_ctrl_addr))*32) <= tdc_ctrl_data_in; + end if; +end process; + --------------------------------------------------------------------------- -- SPI / Flash --------------------------------------------------------------------------- @@ -1041,6 +1162,85 @@ THE_FPGA_REBOOT : fpga_reboot PROGRAMN => PROGRAMN ); + +------------------------------------------------------------------------------- +-- TDC +------------------------------------------------------------------------------- + THE_TDC : TDC + generic map ( + CHANNEL_NUMBER => 5, -- Number of TDC channels + STATUS_REG_NR => 0, + CONTROL_REG_NR => 2) + port map ( + RESET => reset_i, + CLK_TDC => CLK_PCLK_RIGHT, -- Clock used for the time measurement + CLK_READOUT => clk_100_i, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => trigger_in_buf_i, -- Channel start signals + TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width + TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width + -- + -- Trigger signals from handler +-- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet +-- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet +-- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet +-- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet +-- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet +-- SPIKE_DETECTED_IN => trg_spike_detected_i, +-- MULTI_TMG_TRG_IN => trg_multiple_trg_i, +-- SPURIOUS_TRG_IN => trg_spurious_trg_i, +-- -- +-- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package +-- TRG_CODE_IN => trg_code_i, -- +-- TRG_INFORMATION_IN => trg_information_i, -- +-- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package +-- -- + --Response to handler +-- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal +-- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc +-- DATA_OUT => fee_data_i, -- tdc data +-- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal +-- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal + -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + --Status Registers Bus + SRB_READ_EN_IN => srb_read_en, -- bus read en strobe + SRB_WRITE_EN_IN => srb_write_en, -- bus write en strobe + SRB_ADDR_IN => srb_addr, -- bus address + SRB_DATA_OUT => srb_data_out, -- bus data + SRB_DATAREADY_OUT => srb_data_ready, -- bus data ready strobe + SRB_UNKNOWN_ADDR_OUT => srb_invalid, -- bus invalid addr + --Encoder Start Registers Bus + ESB_READ_EN_IN => esb_read_en, -- bus read en strobe + ESB_WRITE_EN_IN => esb_write_en, -- bus write en strobe + ESB_ADDR_IN => esb_addr, -- bus address + ESB_DATA_OUT => esb_data_out, -- bus data + ESB_DATAREADY_OUT => esb_data_ready, -- bus data ready strobe + ESB_UNKNOWN_ADDR_OUT => esb_invalid, -- bus invalid addr + --Fifo Write Registers Bus + FWB_READ_EN_IN => fwb_read_en, -- bus read en strobe + FWB_WRITE_EN_IN => fwb_write_en, -- bus write en strobe + FWB_ADDR_IN => fwb_addr, -- bus address + FWB_DATA_OUT => fwb_data_out, -- bus data + FWB_DATAREADY_OUT => fwb_data_ready, -- bus data ready strobe + FWB_UNKNOWN_ADDR_OUT => fwb_invalid, -- bus invalid addr + --Lost Hit Registers Bus + LHB_READ_EN_IN => '0', -- lhb_read_en, -- bus read en strobe + LHB_WRITE_EN_IN => '0', -- lhb_write_en, -- bus write en strobe + LHB_ADDR_IN => (others => '0'), -- lhb_addr, -- bus address + LHB_DATA_OUT => open, -- lhb_data_out, -- bus data + LHB_DATAREADY_OUT => open, -- lhb_data_ready, -- bus data ready strobe + LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr + -- + LOGIC_ANALYSER_OUT => open, + CONTROL_REG_IN => tdc_ctrl_reg); + --------------------------------------------------------------------------- -- Clock and Trigger Configuration @@ -1129,11 +1329,11 @@ LED_YELLOW <= link_ok; --debug(3); --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_i); - time_counter <= time_counter + 1; - end process; - +-- process +-- begin +-- wait until rising_edge(clk_100_i); +-- time_counter <= time_counter + 1; +-- end process; +-- end architecture; diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index d08948a..9ee3327 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -49,8 +49,8 @@ REGION "REGION_CTS" "R42C38D" 37 57 DEVSIZE; # UGROUP "cts_group" # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; -MULTICYCLE TO CELL "THE_CMB/trg_sync" 20 ns; -MULTICYCLE TO CELL "THE_CMB/error_reg" 20 ns; +MULTICYCLE TO CELL "THE_MBS/trg_sync" 20 ns; +MULTICYCLE TO CELL "THE_MBS/error_reg" 20 ns; #TrbNet Hub REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE; @@ -149,7 +149,7 @@ UGROUP "gbe_rx_tx" BLKNAME GBE/setup_imp_gen_SETUP; -REGION "GBE_REGION" "R50C2D" 25 35 DEVSIZE; +REGION "GBE_REGION" "R50C12D" 25 35 DEVSIZE; REGION "MED0" "R81C10D" 34 40 DEVSIZE; LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; diff --git a/tdc_releases/tdc_v1.1.1/TDC.vhd b/tdc_releases/tdc_v1.1.1/TDC.vhd index 46d8217..63952c4 100644 --- a/tdc_releases/tdc_v1.1.1/TDC.vhd +++ b/tdc_releases/tdc_v1.1.1/TDC.vhd @@ -24,19 +24,19 @@ entity TDC is TRG_WIN_POST : in std_logic_vector(10 downto 0); -- -- Trigger signals from handler - TRG_DATA_VALID_IN : in std_logic; - VALID_TIMING_TRG_IN : in std_logic; - VALID_NOTIMING_TRG_IN : in std_logic; - INVALID_TRG_IN : in std_logic; - TMGTRG_TIMEOUT_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - SPURIOUS_TRG_IN : in std_logic; + TRG_DATA_VALID_IN : in std_logic := '0'; + VALID_TIMING_TRG_IN : in std_logic := '0'; + VALID_NOTIMING_TRG_IN : in std_logic := '0'; + INVALID_TRG_IN : in std_logic := '0'; + TMGTRG_TIMEOUT_IN : in std_logic := '0'; + SPIKE_DETECTED_IN : in std_logic := '0'; + MULTI_TMG_TRG_IN : in std_logic := '0'; + SPURIOUS_TRG_IN : in std_logic := '0'; -- - TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - TRG_CODE_IN : in std_logic_vector(7 downto 0); - TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - TRG_TYPE_IN : in std_logic_vector(3 downto 0); + TRG_NUMBER_IN : in std_logic_vector(15 downto 0) := (others => '0'); + TRG_CODE_IN : in std_logic_vector(7 downto 0) := (others => '0'); + TRG_INFORMATION_IN : in std_logic_vector(23 downto 0) := (others => '0'); + TRG_TYPE_IN : in std_logic_vector(3 downto 0) := (others => '0'); -- --Response to handler TRG_RELEASE_OUT : out std_logic; diff --git a/tdc_releases/tdc_v1.1.1/tdc_constraints.lpf b/tdc_releases/tdc_v1.1.1/tdc_constraints.lpf index 2411c35..58f2c0b 100644 --- a/tdc_releases/tdc_v1.1.1/tdc_constraints.lpf +++ b/tdc_releases/tdc_v1.1.1/tdc_constraints.lpf @@ -7,48 +7,48 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# GSR_NET NET "reset_i"; -################################################################# -# Locate Serdes and media interfaces -################################################################# -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; - -REGION "MEDIA_UPLINK" "R105C109D" 10 22; -REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE; - -LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; - -MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; - - -#Jan: Placement of TrbNet components (at least, most of them) -REGION "REGION_TRBNET" "R35C109D" 70 22 DEVSIZE; -#UGROUP "TrbNet" BBOX 77 27 -# BLKNAME THE_ENDPOINT -# BLKNAME THE_ENDPOINT/THE_ENDPOINT -#LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; -LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; - +# ################################################################# +# # Locate Serdes and media interfaces +# ################################################################# +# LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +# +# REGION "MEDIA_UPLINK" "R105C109D" 10 22; +# REGION "REGION_SPI" "R2C109D" 15 22 DEVSIZE; +# +# LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +# LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +# +# LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +# +# MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +# MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +# MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 30 ns; +# +# +# #Jan: Placement of TrbNet components (at least, most of them) +# REGION "REGION_TRBNET" "R35C109D" 70 22 DEVSIZE; +# #UGROUP "TrbNet" BBOX 77 27 +# # BLKNAME THE_ENDPOINT +# # BLKNAME THE_ENDPOINT/THE_ENDPOINT +# #LOCATE UGROUP "TrbNet" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_2_gentermbuf_termbuf/TRMBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_INTERNAL_BUS_HANDLER/Bus_handler_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/MPLEX/MUX_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/the_addresses/HUBLOGIC_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_TRBNET"; +# LOCATE UGROUP "THE_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_TRBNET"; +# ################################################################# # TDC Constraints @@ -826,7 +826,7 @@ UGROUP "E&F_26" BBOX 6 25 LOCATE UGROUP "E&F_26" SITE "R96C156D" ; UGROUP "E&F_27" BBOX 6 25 BLKNAME THE_TDC/GEN_Channels_27_Channels/Channel_200_1; -LOCATE UGROUP "E&F_27" SITE "R105C131D ; +LOCATE UGROUP "E&F_27" SITE "R105C131D" ; UGROUP "E&F_28" BBOX 6 25 BLKNAME THE_TDC/GEN_Channels_28_Channels/Channel_200_1; LOCATE UGROUP "E&F_28" SITE "R105C156D" ; diff --git a/wasa/compile_padiwa_frankfurt.pl b/wasa/compile_padiwa_frankfurt.pl index dde2d8f..084cf2d 100755 --- a/wasa/compile_padiwa_frankfurt.pl +++ b/wasa/compile_padiwa_frankfurt.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_padiwa"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -39,6 +39,7 @@ my $SPEEDGRADE="8"; #create full lpf file system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); +system("cat ../tdc_releases/tdc_v1.1.1/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); diff --git a/wasa/compile_panda_dirc_wasa_frankfurt.pl b/wasa/compile_panda_dirc_wasa_frankfurt.pl index 4df50a4..abb1ef1 100755 --- a/wasa/compile_panda_dirc_wasa_frankfurt.pl +++ b/wasa/compile_panda_dirc_wasa_frankfurt.pl @@ -16,7 +16,7 @@ my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; ################################################################################### - +$ENV{'PAR_DESIGN_NAME'}=$TOPNAME; # # set_option -technology MACHXO2 diff --git a/wasa/sim/machxo.mpf b/wasa/sim/machxo.mpf index 0464cff..45f4740 100644 --- a/wasa/sim/machxo.mpf +++ b/wasa/sim/machxo.mpf @@ -60,6 +60,7 @@ mc2_lib = $MODEL_TECH/../mc2_lib machxo2 = /d/jspc29/lattice/diamond/1.4.2.105/ispfpga/vhdl/data/machxo2/mti/machxo2 work = work +ecp3 = /d/jspc29/lattice/diamond/2.01/ispfpga/vhdl/data/ecp3/mti/work [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. @@ -1645,43 +1646,47 @@ suppress = 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 18 +Project_Files_Count = 20 Project_File_0 = /d/jspc22/trb/cvs/trb3/wasa/cores/efb_define_def.v -Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1344528395 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1344528395 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_1 = /d/jspc22/trb/cvs/trbnet/trb_net_components.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346851369 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_2 = /d/jspc22/trb/cvs/trb3/wasa/source/pwm.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355218918 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355218918 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_3 = /d/jspc22/trb/cvs/trb3/tdc_test/modelsim/sim_pulsestretch.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348848169 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355306195 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/full_tb.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355226184 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355226184 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_5 = /d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346854393 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_6 = /d/jspc22/trb/cvs/trb3/wasa/version.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228266 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355493687 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_7 = /d/jspc22/trb/cvs/trb3/base/trb3_components.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1348839333 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355506570 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_8 = /d/jspc22/trb/cvs/trb3/wasa/panda_dirc_wasa.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355228319 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355487288 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = /d/jspc22/trb/cvs/trbnet/trb_net_std.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_10 = /d/jspc22/trb/cvs/trb3/wasa/source/tb/pwm_tb.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344272681 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_11 = /d/jspc22/trb/cvs/trb3/wasa/cores/UFM_WB.v -Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1355162337 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1355162337 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+/d/jspc22/trb/cvs/trb3/wasa/cores compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_12 = /d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344350049 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_13 = /d/jspc22/trb/cvs/trbnet/special/spi_ltc2600.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350664433 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_14 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355147411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1350664433 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_14 = /d/jspc22/trb/fifotest/tb_fifo_36x8k_oreg_tmpl.vhd +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355754626 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_15 = /d/jspc22/trb/cvs/trb3/wasa/cores/flashram.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344516091 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_16 = /d/jspc22/trb/cvs/trb3/wasa/cores/flash.vhd +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355147411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /d/jspc22/trb/fifotest/fifo_36x4k_oreg.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1355754876 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_18 = /d/jspc22/trb/cvs/trb3/wasa/cores/pll.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1346849713 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_19 = /d/jspc22/trb/cvs/trb3/wasa/cores/oddr16.vhd +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1344002544 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/wasa/trb3_periph_padiwa.prj b/wasa/trb3_periph_padiwa.prj index 53bf5b3..cde14cd 100644 --- a/wasa/trb3_periph_padiwa.prj +++ b/wasa/trb3_periph_padiwa.prj @@ -138,19 +138,28 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" -add_file -vhdl -lib "work" "trb3_periph_padiwa.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel_200.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd" +############### +#Change path to tdc release also in compile script! +############### +#add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Adder_304.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/bit_sync.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/BusHandler.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Channel_200.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Encoder_304_Bit.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/FIFO_32x32_OutReg.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/LogicAnalyser.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Readout.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel_200.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/Reference_Channel.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_encoder_3.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ROM_FIFO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd" +add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd" + +add_file -vhdl -lib "work" "trb3_periph_padiwa.vhd" diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index 7e9d8de..6cf5562 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -88,8 +88,8 @@ end entity; architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is --Constants - constant REGIO_NUM_STAT_REGS : integer := 5; - constant REGIO_NUM_CTRL_REGS : integer := 3; + constant REGIO_NUM_STAT_REGS : integer := 0; + constant REGIO_NUM_CTRL_REGS : integer := 2; attribute syn_keep : boolean; attribute syn_preserve : boolean; @@ -343,7 +343,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91004950", + REGIO_HARDWARE_VERSION => x"91004120", REGIO_INIT_ADDRESS => x"f306", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 100, @@ -675,7 +675,7 @@ begin ------------------------------------------------------------------------------- THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 65, -- Number of TDC channels + CHANNEL_NUMBER => 5, -- Number of TDC channels STATUS_REG_NR => REGIO_NUM_STAT_REGS, CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) port map ( -- 2.43.0