From 8cccf7f6dee700d34485c76ee29a20638f579302 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Tue, 19 Jan 2010 15:53:28 +0000
Subject: [PATCH] new

---
 etrax_interfacev2.vhd |    34 +-
 optical_dtu.vhd       |    36 +-
 simulation.pl         |   105 +-
 tdc_interfacev2.vhd   |   179 +-
 trb_v2b_fpga.stapl    | 11636 +++++++++++++++++-----------------------
 trb_v2b_fpga.ucf      |   529 +-
 trb_v2b_fpga.vhd      |   816 ++-
 trb_v2b_fpga_syn.prj  |    13 +-
 trb_v2b_fpga_tb.vhd   |   255 +-
 trigger_logic.vhd     |   805 +--
 10 files changed, 6867 insertions(+), 7541 deletions(-)

diff --git a/etrax_interfacev2.vhd b/etrax_interfacev2.vhd
index 8351c20..c75b2ce 100644
--- a/etrax_interfacev2.vhd
+++ b/etrax_interfacev2.vhd
@@ -135,7 +135,7 @@ begin
       if rising_edge(CLK)then
         if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
           etrax_data_counter                := 0;
-          data_from_etrax                     <= (others => '0');
+          data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_C(16)                <= 'Z';
           enable_transmition                  <= '1';
           etrax_std_data_counter              <= x"00";
@@ -145,6 +145,7 @@ begin
           ETRAX_DATA_BUS_C(16)                <= 'Z';
           enable_transmition                  <= '0';
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
+        --elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) = x"00" then
         elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
           data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_C(16)                <= data_to_etrax(0);
@@ -178,7 +179,7 @@ begin
       if rising_edge(CLK)then
         if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') then
           etrax_data_counter                := 0;
-          data_from_etrax                     <= (others => '0');
+          data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_E(8)                <= 'Z';
           enable_transmition                  <= '1';
           etrax_std_data_counter              <= x"00";
@@ -188,18 +189,13 @@ begin
           ETRAX_DATA_BUS_E(8)                <= 'Z';
           enable_transmition                  <= '0';
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
-        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) = x"00" then
+--        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) = x"00" then
+        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
           data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_E(8)                 <= data_to_etrax(0);
           etrax_data_counter                  := etrax_data_counter + 1;
           etrax_std_data_counter              <= etrax_std_data_counter + 1;
           enable_transmition                  <= '0';
-        elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) /= x"00" and (rw_operation_finished_pulse = '1' or time_out_pulse = '1') then
-          data_from_etrax                     <= data_from_etrax;
-          ETRAX_DATA_BUS_E(8)                 <= data_to_etrax(0);
-          etrax_data_counter                  := etrax_data_counter + 1;
-          etrax_std_data_counter              <= etrax_std_data_counter + 1;
-          enable_transmition                  <= '0';  
         elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
           data_from_etrax                     <= data_from_etrax;
           ETRAX_DATA_BUS_E(8)                <= data_to_etrax((etrax_data_counter-81) mod 32);--+reg_address*32
@@ -255,14 +251,17 @@ begin
   --abut timing
   REGISTER_ETRAX_BUS: process (CLK, RESET)
   begin 
-    if rising_edge(CLK) then 
-      if rw_operation_finished_pulse = '1' then
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        saved_external_data <= x"bad1face";
+      elsif rw_operation_finished_pulse = '1' then
         saved_external_data <= EXTERNAL_DATA_IN;
       else
         saved_external_data <= saved_external_data;
       end if;
     end if;
   end process REGISTER_ETRAX_BUS;
+  
   EXTERNAL_ADDRESS <= saved_address;
   EXTERNAL_MODE    <= saved_rw_mode(15 downto 0);
   EXTERNAL_DATA_OUT <= saved_data;
@@ -280,7 +279,8 @@ begin
         saved_rw_mode <= data_from_etrax(15 downto 0);
         saved_address <= data_from_etrax(47 downto 16);
      --   reg_address <= reg_address* (conv_integer(data_from_etrax(47 downto 16)));
-        reg_address <= conv_integer(data_from_etrax(31 downto 16));
+--        reg_address <= conv_integer(data_from_etrax(31 downto 16));
+        reg_address <= conv_integer(data_from_etrax(23 downto 16));
         --only 16 lowest bits - the 8 highest is not taken into address for
         --internal registers
         saved_data <= data_from_etrax(79 downto 48);
@@ -305,22 +305,26 @@ begin
          rw_register_i                          <= (others => '0');
       else
         case saved_rw_mode(7 downto 0) is
-          when "00000000"        =>
+          when x"00"        =>
             if saved_rw_mode(15) = '1' and etrax_std_data_counter = 80 and reg_address > 127 and reg_address < 192 then 
               saved_data_fpga <= r_register((reg_address+1-128)*32-1 downto ((reg_address-128)*32));
             elsif saved_rw_mode(15) = '1' and etrax_std_data_counter = 80 and reg_address >191 and reg_address < 256 then 
               saved_data_fpga <= rw_register_i((reg_address+1-192)*32-1 downto (reg_address-192)*32);
             elsif saved_rw_mode(15) = '0' and etrax_std_data_counter = 80 then
-               rw_register_i((reg_address+1-192)*32-1 downto (reg_address-192)*32) <= saved_data;
+              rw_register_i((reg_address+1-192)*32-1 downto (reg_address-192)*32) <= saved_data;
             else
               saved_data_fpga                           <= saved_data_fpga; 
             end if;
-          when "00000001"        =>     --DSP write read
+          when x"01"        =>          --DSP write read
             saved_data_fpga                            <= saved_external_data;
           when x"02"        =>          --sdram
             saved_data_fpga                            <= saved_external_data;
           when x"03"        =>          --ADDON board write read
             saved_data_fpga                            <= saved_external_data;
+          when x"05"        =>          --trigger interface
+            saved_data_fpga                            <= saved_external_data;
+          when x"06"        =>          --SFP read
+            saved_data_fpga                            <= saved_external_data;
           when others            =>     
             saved_data_fpga                            <= x"deadface";
         end case;
diff --git a/optical_dtu.vhd b/optical_dtu.vhd
index 527e3fd..66072ef 100644
--- a/optical_dtu.vhd
+++ b/optical_dtu.vhd
@@ -248,10 +248,12 @@ begin
         DTU_LVL1_CURRENT                   <= IDLE;
         OPT_DTU_DEBUG_REGISTER_00(7 downto 4) <= (others => '0');
         OPT_DTU_DEBUG_REGISTER_01   <= (others => '0');
+        lvl1_trigger_pulse <= '0';
       else
         DTU_LVL1_CURRENT                   <= DTU_LVL1_NEXT;
         OPT_DTU_DEBUG_REGISTER_00(7 downto 4) <= opt_dtu_debug_register_00_i(7 downto 4);
         OPT_DTU_DEBUG_REGISTER_01   <= opt_dtu_debug_register_01_i;
+        lvl1_trigger_pulse <= lvl1_trigger_i;
       end if;
     end if;
   end process DTU_LVL1_CLK;
@@ -267,18 +269,21 @@ begin
         else
           DTU_LVL1_NEXT                      <= IDLE;
         end if;
+        
       when SEND_LVL1_A            =>
         opt_dtu_debug_register_00_i(7 downto 4) <= x"2";
         lvl1_trigger_i                       <= '1';
         DTU_LVL1_NEXT                        <= SEND_LVL1_B;
+        
       when SEND_LVL1_B            =>
         opt_dtu_debug_register_00_i(7 downto 4) <= x"3";
-        lvl1_trigger_i                       <= '1';
+        lvl1_trigger_i                       <= '0';  --was '1'
         if LVL1_BUSY = '1' then
           DTU_LVL1_NEXT                      <= WAIT_FOR_LVL1_BUSY_END;
         else
           DTU_LVL1_NEXT                      <= SEND_LVL1_B;
         end if;
+        
       when WAIT_FOR_LVL1_BUSY_END =>
         opt_dtu_debug_register_00_i(7 downto 4) <= x"4";
         lvl1_trigger_i                       <= '0';
@@ -288,19 +293,36 @@ begin
         else
           DTU_LVL1_NEXT                      <= WAIT_FOR_LVL1_BUSY_END;
         end if;
+        
       when others                 =>
         opt_dtu_debug_register_00_i(7 downto 4) <= x"0";
         lvl1_trigger_i                       <= '0';
         DTU_LVL1_NEXT                        <= IDLE;
     end case;
   end process DTU_LVL1_PROC;
+
+  COUNT_LVL1_BUSY : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        opt_dtu_debug_register_00_i(31 downto 24) <= (others => '0');
+        OPT_DTU_DEBUG_REGISTER_00(31 downto 24) <= (others => '0');
+      elsif lvl1_busy_end_pulse = '1' then
+        opt_dtu_debug_register_00_i(31 downto 24) <= opt_dtu_debug_register_00_i(31 downto 24) +1;
+        OPT_DTU_DEBUG_REGISTER_00(31 downto 24) <= opt_dtu_debug_register_00_i(31 downto 24);
+      else
+        opt_dtu_debug_register_00_i(31 downto 24) <= opt_dtu_debug_register_00_i(31 downto 24);
+        OPT_DTU_DEBUG_REGISTER_00(31 downto 24) <= opt_dtu_debug_register_00_i(31 downto 24);
+      end if;
+    end if;
+  end process COUNT_LVL1_BUSY;
   
-  LVL1_TRIGGER_PULSE_PROC : edge_to_pulse
-    port map (
-        clock  => CLK,
-        en_clk => '1',
-        signal_in  => lvl1_trigger_i,
-        pulse  => lvl1_trigger_pulse);
+--  LVL1_TRIGGER_PULSE_PROC : edge_to_pulse
+--    port map (
+--        clock  => CLK,
+--        en_clk => '1',
+--        signal_in  => lvl1_trigger_i,
+--        pulse  => lvl1_trigger_pulse);
   
   LVL1_TRIGGER <= lvl1_trigger_pulse;
 
diff --git a/simulation.pl b/simulation.pl
index acfbe5c..2702a48 100755
--- a/simulation.pl
+++ b/simulation.pl
@@ -30,15 +30,17 @@ my $fh = new FileHandle("< trb_v2b_fpga_cts.vhd");
 my $fh1 = new FileHandle("> temp_perl.vhd");
 my $exchange_a ="trb_v2b_fpga";
 my $exchange_to_a = "trb_v2b_fpga_cts";
+my $exchange_to_aa = "trb_v2b_fpga_simple_cts";
 my $exchange_to_b = "trb_v2b_fpga_mdc_or_shower";
 my $exchange_to_c = "trb_v2b_fpga_endpoint";
+my $exchange_to_cc = "trb_v2b_fpga_simple_endpoint";
 my $exchange_b = "--*no sim";
 my $temptext;
 
 while(<$fh>)
 {
     $temptext = $_;
-    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 5 := /TRBV2_TYPE           : integer range 0 to 5 := 5;--/;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 7 := /TRBV2_TYPE           : integer range 0 to 7 := 5;--/;
     $temptext  =~ s/$exchange_a/$exchange_to_a/g;
     print {$fh1} $temptext;
 }
@@ -53,7 +55,7 @@ my $fh3 = new FileHandle("> temp_perl.vhd");
 while(<$fh2>)
 {
     $temptext = $_;
-    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 5 := /TRBV2_TYPE           : integer range 0 to 5 := 1;--/;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 7 := /TRBV2_TYPE           : integer range 0 to 7 := 1;--/;
     $temptext  =~ s/$exchange_a/$exchange_to_b/g;
     print {$fh3} $temptext;
 }
@@ -116,6 +118,7 @@ $fh9 -> close;
 $c="cp temp_perl.vhd trb_net16_med_tlk.vhd";
 system($c);
 
+#next file
 $c="cp trb_v2b_fpga.vhd trb_v2b_fpga_endpoint.vhd";
 system($c);
 my $fh10 = new FileHandle("< trb_v2b_fpga_endpoint.vhd");
@@ -125,7 +128,7 @@ while(<$fh10>)
 {
     $temptext = $_;
     $temptext  =~ s/TRBNET_ENABLE        : integer range 0 to 3   :=/TRBNET_ENABLE        : integer range 0 to 3   :=1;--/;
-    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 5   :=/TRBV2_TYPE           : integer range 0 to 5   :=0;--/;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 7   :=/TRBV2_TYPE           : integer range 0 to 7   :=0;--/;
     $temptext  =~ s/ENABLE_DMA           : integer range 1 to 2   :=/ENABLE_DMA           : integer range 1 to 2   :=2;--/;
     $temptext  =~ s/$exchange_a/$exchange_to_c/g;
     print {$fh11} $temptext;
@@ -134,4 +137,100 @@ $fh10 -> close;
 $fh11 -> close;
 $c="cp temp_perl.vhd trb_v2b_fpga_endpoint.vhd";
 system($c);
+#next file
 
+$c="cp trb_v2b_fpga.vhd trb_v2b_fpga_simple_endpoint.vhd";
+system($c);
+my $fh12 = new FileHandle("< trb_v2b_fpga_simple_endpoint.vhd");
+my $fh13 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh12>)
+{
+    $temptext = $_;
+    $temptext  =~ s/TRBNET_ENABLE        : integer range 0 to 3   :=/TRBNET_ENABLE        : integer range 0 to 3   :=0;--/;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 7   :=/TRBV2_TYPE           : integer range 0 to 7   :=7;--/;
+    $temptext  =~ s/ENABLE_DMA           : integer range 1 to 2   :=/ENABLE_DMA           : integer range 1 to 2   :=1;--/;
+    $temptext  =~ s/$exchange_a/$exchange_to_cc/g;
+    print {$fh13} $temptext;
+}
+$fh12 -> close;
+$fh13 -> close;
+$c="cp temp_perl.vhd trb_v2b_fpga_simple_endpoint.vhd";
+system($c);
+
+
+#next file
+$c="cp trb_v2b_fpga.vhd trb_v2b_fpga_simple_cts.vhd";
+system($c);
+my $fh14 = new FileHandle("< trb_v2b_fpga_simple_cts.vhd");
+my $fh15 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh14>)
+{
+    $temptext = $_;
+    $temptext  =~ s/TRBV2_TYPE           : integer range 0 to 7   := /TRBV2_TYPE          : integer range 0 to 7 := 6;--/;
+    $temptext  =~ s/TRBNET_ENABLE        : integer range 0 to 3   :=/TRBNET_ENABLE        : integer range 0 to 3   :=0;--/;
+    $temptext  =~ s/ENABLE_DMA           : integer range 1 to 2   :=/ENABLE_DMA           : integer range 1 to 2   :=1;--/;
+    $temptext  =~ s/$exchange_a/$exchange_to_aa/g;
+    print {$fh15} $temptext;
+}
+$fh15 -> close;
+$fh14 -> close;
+$c="cp temp_perl.vhd trb_v2b_fpga_simple_cts.vhd";
+system($c);
+
+
+my $fh16 = new FileHandle("< sdram_fpga_interface.vhd");
+my $fh17 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh16>)
+{
+    $temptext = $_;
+    $temptext  =~ s/--sim--//;
+    if($temptext =~ /--no_sim--/)
+    {
+	$temptext  = "--".$temptext;
+    }
+    print {$fh17} $temptext;
+}
+$fh16 -> close;
+$fh17 -> close;
+$c="cp temp_perl.vhd sdram_fpga_interface.vhd";
+system($c);
+
+
+my $fh18 = new FileHandle("< sdramcntl.vhd");
+my $fh19 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh18>)
+{
+    $temptext = $_;
+    $temptext  =~ s/--sim--//;
+    if($temptext =~ /--no_sim--/)
+    {
+	$temptext  = "--".$temptext;
+    }
+    print {$fh19} $temptext;
+}
+$fh18 -> close;
+$fh19 -> close;
+$c="cp temp_perl.vhd sdramcntl.vhd";
+system($c);
+
+my $fh20 = new FileHandle("< sdram_controller.vhd");
+my $fh21 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh20>)
+{
+    $temptext = $_;
+    $temptext  =~ s/--sim--//;
+    if($temptext =~ /--no_sim--/)
+    {
+	$temptext  = "--".$temptext;
+    }
+    print {$fh21} $temptext;
+}
+$fh20 -> close;
+$fh21 -> close;
+$c="cp temp_perl.vhd sdram_controller.vhd";
+system($c);
diff --git a/tdc_interfacev2.vhd b/tdc_interfacev2.vhd
index d91f6ed..418b848 100644
--- a/tdc_interfacev2.vhd
+++ b/tdc_interfacev2.vhd
@@ -9,7 +9,8 @@ entity tdc_interfacev2 is
   generic (
     ENABLE_DMA : positive;
     NUMBER_OFF_ADD_DATA : natural;
-    TRBV2_TYPE : natural
+    TRBV2_TYPE : natural;
+    USE_EXTERNAL_SDRAM : natural
     );
   port (
     CLK                               : in  std_logic;
@@ -53,9 +54,9 @@ entity tdc_interfacev2 is
     TDC_DATA_OUT                      : out std_logic_vector (31 downto 0);  --data to ETRAX (LVL2)
     TDC_DATA_VALID                    : out std_logic;  -- The TDC_DATA_OUT can be written
     ETRAX_IS_READY_TO_READ            : in  std_logic;
-    ETRAX_IS_BUSY          : in std_logic;
-    LVL1_BUSY                    : out std_logic;
-    LVL2_BUSY                   : out std_logic;
+    ETRAX_IS_BUSY                     : in std_logic;
+    LVL1_BUSY                       : out std_logic;
+    LVL2_BUSY                       : out std_logic;
     TDC_REGISTER_00                 : out std_logic_vector(31 downto 0);
     TDC_REGISTER_01                 : out std_logic_vector(31 downto 0);
     TDC_REGISTER_02                 : out std_logic_vector(31 downto 0);
@@ -72,12 +73,19 @@ entity tdc_interfacev2 is
     TRB_ID                   : in std_logic_vector(31 downto 0);    
     LVL1_FINISHED     : out std_logic;
     LVL2_FINISHED     : out std_logic;
-    TRBNET_HEADER_BUILD    : in  std_logic
+    TRBNET_HEADER_BUILD    : in  std_logic;
+    RD_EN               : out  std_logic;
+    WR_EN               : out  std_logic;
+    WR_READY            : in std_logic;
+    RD_READY            : in std_logic;
+    DATA_IN             : in  std_logic_vector(31 downto 0);
+    DATA_OUT            : out std_logic_vector(31 downto 0);
+    SDRAM_BUSY          : in std_logic
     );
 end tdc_interfacev2;
 
 architecture tdc_interfacev2 of tdc_interfacev2 is
-  
+
   component header_add_data_fifo_4kW
     port (
       din           : IN  std_logic_VECTOR(33 downto 0);
@@ -153,13 +161,15 @@ architecture tdc_interfacev2 of tdc_interfacev2 is
   signal lvl1_busy_i : std_logic;
   signal lvl1_busy_i_not : std_logic;  
   signal lvl1_memory_busy_i : std_logic;
+  signal lvl1_memory_busy_mem : std_logic;
   signal lvl1_trigger_pulse : std_logic;
   signal lvl1_tdc_trigg_i : std_logic;
   signal lvl1_tdc_token_i : std_logic;
   signal lvl1_buffer_in : std_logic_vector(31 downto 0);
   signal lvl1_busy_end_pulse : std_logic;
-  signal test_counter_0 : std_logic_vector(7 downto 0);  --lvl1 started
+  signal test_counter_0 : std_logic_vector(15 downto 0);  --lvl1 started
   signal test_counter_1 : std_logic_vector(7 downto 0);  --lvl` finished
+  signal start_tdc_readout_pulse : std_logic;
   --lvl2
   type LVL2_START_FSM is
     (IDLE,WAIT_FOR_BUSY_END,READOUT_HEADER_MARKER_1,READOUT_HEADER_MARKER_2,SEND_HEADERS_AND_DATA,READOUT_DATA_MARKER_1,READOUT_DATA_MARKER_2,SEND_DATA);
@@ -167,7 +177,7 @@ architecture tdc_interfacev2 of tdc_interfacev2 is
   signal lvl2_busy_i : std_logic;
   signal not_lvl2_busy : std_logic;
   signal lvl2_busy_end_pulse : std_logic;
-  signal test_counter_2 : std_logic_vector(7 downto 0);  --lvl2 started 
+  signal test_counter_2 : std_logic_vector(15 downto 0);  --lvl2 started 
   signal test_counter_3 : std_logic_vector(7 downto 0);  --lvl2 finished
   
   --debug registers
@@ -247,6 +257,11 @@ architecture tdc_interfacev2 of tdc_interfacev2 is
   signal wait_for_trigg_up   : std_logic;
   signal wait_for_trigg_cntr : std_logic_vector(7 downto 0);
 
+  --
+  signal rd_en_i : std_logic;
+  signal wr_en_i : std_logic;
+  signal sdram_busy_i : std_logic;
+  signal word_counter : std_logic_vector(15 downto 0);
 begin
   
   TDC_REGISTER : process (CLK, RESET)
@@ -256,18 +271,20 @@ begin
       TDC_REGISTER_00(1)            <= B_TDC_ERROR;
       TDC_REGISTER_00(2)            <= C_TDC_ERROR;
       TDC_REGISTER_00(3)            <= D_TDC_ERROR;
-      TDC_REGISTER_00(13 downto 4)  <= (others => '0');
+      TDC_REGISTER_00(11 downto 4)  <= test_counter_0(15 downto 8);
+      TDC_REGISTER_00(13 downto 12) <= (others => '0');
       TDC_REGISTER_00(14)           <= lvl1_busy_i;
       TDC_REGISTER_00(15)           <= lvl1_memory_busy_i;    
       TDC_REGISTER_00(30)           <= '0';
       TDC_REGISTER_00(31)           <= lvl2_busy_i;
-      TDC_REGISTER_00(29 downto 16) <= (others => '0');
+      TDC_REGISTER_00(23 downto 16) <= test_counter_2(15 downto 8);
+      TDC_REGISTER_00(29 downto 24) <= (others => '0');
       TDC_REGISTER_01(27 downto 0)  <= lvl2_debug & trigger_register_00_i(5 downto 2) & "00" & trigger_register_00_i(1 downto 0)& words_in_event(15 downto 0);
       TDC_REGISTER_01(30 downto 28) <= (others => '0');
       TDC_REGISTER_01(31)           <= ETRAX_IS_BUSY;
       TDC_REGISTER_02(31 downto 0)  <=  hd_full_i & hd_empty_i & hd_wr_en_i & hd_dout_i(32) & hd_rd_data_count_i & data_full_i & data_empty_i & data_wr_en_i  & data_dout_i(32) & data_rd_data_count_i(11 downto 0);
       TDC_REGISTER_03(31 downto 0)  <= x"0"& LVL1_CODE & LVL1_TAG(7 downto 0) & x"0" & lvl1_code_i & lvl1_tag_minus1;
-      TDC_REGISTER_04(31 downto 0)  <= test_counter_3 & test_counter_2 & test_counter_1 & test_counter_0;
+      TDC_REGISTER_04(31 downto 0)  <= test_counter_3 & test_counter_2(7 downto 0) & test_counter_1 & test_counter_0(7 downto 0);
     end if;
   end process TDC_REGISTER;
 
@@ -279,10 +296,10 @@ begin
          tdc_ready      <= '0';
          lvl1_buffer_in <= (others => '0');
          received_tdc_token_i <= '0';
-        else
-          tdc_ready      <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
-          lvl1_buffer_in <= TDC_DATA_IN;
-          received_tdc_token_i <= RECEIVED_TDC_TOKEN;
+       else
+         tdc_ready      <= A_TDC_READY or B_TDC_READY or C_TDC_READY or D_TDC_READY;
+         lvl1_buffer_in <= TDC_DATA_IN;
+         received_tdc_token_i <= RECEIVED_TDC_TOKEN;
        end if;
      end if;
    end process SYNC_TDC_DATA;
@@ -313,23 +330,31 @@ begin
    end process SEND_BUNCH_RESET;
 
   -- LVL1 logic
+
+  LVL1_PULSER : edge_to_pulse
+     port map (
+       clock     => CLK,
+       en_clk    => '1',
+       signal_in => START_TDC_READOUT,
+       pulse     => start_tdc_readout_pulse);
   
   SELECT_TRIGGER : process (CLK, RESET)
   begin  
     if rising_edge(CLK) then  
-      if RESET = '1' then
+      if RESET = '1' or lvl1_trigger_hades_or_not_pulse = '1' then
         lvl1_trigger_hades_or_not <= '0';
-      elsif TRIGGER_WITH_GEN_EN = '0' then
-        lvl1_trigger_hades_or_not <= START_TDC_READOUT;
+      elsif start_tdc_readout_pulse = '1' then
+        lvl1_trigger_hades_or_not <= '1';
       else
-        lvl1_trigger_hades_or_not <= TRIGGER_WITH_GEN_EN  and TRIGGER_WITH_GEN and  (not lvl1_busy_i) and (not lvl2_busy_i);
+        lvl1_trigger_hades_or_not <= lvl1_trigger_hades_or_not;
+--        lvl1_trigger_hades_or_not <= TRIGGER_WITH_GEN_EN  and TRIGGER_WITH_GEN and  (not lvl1_busy_i) and (not lvl2_busy_i);
       end if;
     end if;
   end process SELECT_TRIGGER;
 
-  LVL1_PULSER : edge_to_pulse
+  TDC_LVL1_PULSER : edge_to_pulse
      port map (
-       clock     =>  TDC_CLK,
+       clock     => TDC_CLK,
        en_clk    => '1',
        signal_in => lvl1_trigger_hades_or_not,
        pulse     => lvl1_trigger_hades_or_not_pulse);
@@ -367,8 +392,9 @@ begin
         UP_IN     => wait_for_trigg_up,
         DOWN_IN   => '0');
   
-  LVL1_DATA_FIFO: lvl1_buffer_32kW
-    port map (
+  INTERNAL_BUFFER: if USE_EXTERNAL_SDRAM = 0 generate
+    LVL1_DATA_FIFO: lvl1_buffer_32kW
+      port map (
         din           => data_din_i,
         rd_clk        => CLK,
         rd_en         => data_rd_en_i,
@@ -380,6 +406,63 @@ begin
         full          => data_full_i,
         rd_data_count => data_rd_data_count_i,
         wr_data_count => data_wr_data_count_i);
+    RD_EN <= '0';
+    WR_EN <= '0';
+    sdram_busy_i <= '0';
+  end generate INTERNAL_BUFFER;
+
+  EXTERNAL_BUFFER: if USE_EXTERNAL_SDRAM = 1 generate
+    
+    WRITE_DATA : process (TDC_CLK, RESET)
+    begin
+      if rising_edge(TDC_CLK) then
+        if RESET = '1' then
+          DATA_OUT <= (others => '0');
+          WR_EN <= '0';
+        elsif LVL1_START_fsm_currentstate = SEND_AND_WAIT_FOR_TOKEN then
+          DATA_OUT <= data_din_i(31 downto 0);
+          WR_EN <= data_wr_en_i;
+        else
+          DATA_OUT <= data_din_i(31 downto 0);
+          WR_EN <= '0';
+        end if;
+      end if;
+    end process WRITE_DATA;
+
+--    DATA_OUT <= data_din_i(31 downto 0);
+--    WR_EN <= data_wr_en_i;
+
+    data_dout_i(31 downto 0) <= DATA_IN;
+    SEND_READ_REQUEST : process (CLK, RESET)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          RD_EN <= '0';
+        elsif LVL2_START_fsm_currentstate = SEND_DATA then
+          RD_EN <= data_rd_en_i;
+        else
+          RD_EN <= '0';
+        end if;
+      end if;
+    end process SEND_READ_REQUEST;
+    
+    sdram_busy_i <= SDRAM_BUSY;
+    data_dout_i(32) <= '1';
+
+    WORD_COUNTER_PROC : process (CLK, RESET)
+    begin
+      if rising_edge(CLK) then
+        if RESET = '1' then
+          word_counter <= (others => '0');
+        elsif LVL2_START_fsm_currentstate = READOUT_HEADER_MARKER_1 and hd_dout_i(32) = '1' then
+          word_counter <= hd_dout_i(15 downto 0);
+        elsif ETRAX_IS_READY_TO_READ = '1' then
+          word_counter <= word_counter - 1;
+        end if;
+      end if;
+    end process WORD_COUNTER_PROC;
+    
+  end generate EXTERNAL_BUFFER;
 
   HEADER_DATA_FIFO: header_add_data_fifo_4kW
     port map (
@@ -441,7 +524,7 @@ begin
       when IDLE =>
         trigger_register_00_i(5 downto 2) <= x"1";
         lvl1_busy_i_fsm          <= '0';
-        if (lvl1_trigger_tdc = '1'and LVL1_CODE /= x"d") then
+        if (lvl1_trigger_tdc = '1') then
           LVL1_START_fsm_nextstate <= WAIT_BEFORE_TRIGG;
         else
           LVL1_START_fsm_nextstate <= IDLE;
@@ -570,7 +653,11 @@ begin
 
       when WAIT_FOR_EMPTYING_BUFFERS => 
         trigger_register_00_i(5 downto 2) <= x"d";
-        if lvl1_memory_busy_i = '0'  then
+        if lvl1_memory_busy_i = '0' then -- and SDRAM_BUSY = '0' then  --when
+                                                               --USE_EXTERNAL_SDRAM=0
+                                                               --then
+                                                               --sdram_busy = 0
+                                                               --from external
           LVL1_START_fsm_nextstate   <= IDLE;
         else
           LVL1_START_fsm_nextstate   <= WAIT_FOR_EMPTYING_BUFFERS;
@@ -630,7 +717,7 @@ begin
     if rising_edge(CLK) then
       if RESET = '1' or lvl1_tdc_trigg_i = '1' then
         add_data_counter <= x"0" & HOW_MANY_ADD_DATA(3 downto 0);
-      elsif add_data_pulse = '1' then
+      elsif  LVL1_START_fsm_nextstate = SAVE_ADD_DATA then
         add_data_counter <= add_data_counter -1 ;
       end if;
     end if;
@@ -669,16 +756,20 @@ begin
       elsif TRIGGER_WITH_GEN_EN = '1' then
         lvl1_tag_minus1 <= trigger_counter;
         lvl1_code_i <= x"1";
-      else
+      elsif TDC_REGISTER_05(30)='1' then
+        lvl1_tag_minus1 <= LVL1_TAG(7 downto 0) - 1;
+        lvl1_code_i <= LVL1_CODE;
+      else 
         lvl1_tag_minus1 <= LVL1_TAG(7 downto 0);
         lvl1_code_i <= LVL1_CODE;
+
       end if;
     end if;
   end process SAVE_CODE_AND_TAG;
   
   -----------------------------------------------------------------------------
   ----------------------------------------------------------------------------
-  -- LVL2 logic (only CLK domain)
+  -- LVL2 logic (only CLK domain) 
   -----------------------------------------------------------------------------
   -----------------------------------------------------------------------------
   
@@ -763,7 +854,7 @@ begin
          lvl2_debug <= x"6";
          if data_dout_i(32) = '0' then
            data_rd_en_i_fsm <= '1';
-           LVL2_START_fsm_nextstate <= READOUT_DATA_MARKER_2;
+           LVL2_START_fsm_nextstate <= READOUT_DATA_MARKER_2;  
          else
            data_rd_en_i_fsm <= '0';
            LVL2_START_fsm_nextstate <= SEND_DATA;
@@ -775,10 +866,12 @@ begin
          
        when SEND_DATA =>
          lvl2_debug <= x"8";
-         data_rd_en_i_fsm <= ETRAX_IS_READY_TO_READ;  
-         tdc_data_valid_i_fsm <=  data_dout_i(32);
+         data_rd_en_i_fsm <= ETRAX_IS_READY_TO_READ;
+         tdc_data_valid_i_fsm <=  (data_dout_i(32) and (not lvl1_busy_i));-- or SDRAM_BUSY;
+--         --for external sdram acces for writing buffer
+--was before sdram         tdc_data_valid_i_fsm <=  data_dout_i(32);
          TDC_DATA_OUT <= data_dout_i(31 downto 0);
-         if data_dout_i(32) = '0' then
+         if data_dout_i(32) = '0' or (USE_EXTERNAL_SDRAM = 1 and word_counter = x"0000" ) then
            LVL2_START_fsm_nextstate <= IDLE;
          else
            LVL2_START_fsm_nextstate <= SEND_DATA;
@@ -791,6 +884,7 @@ begin
      end case;
    end process START_LVL2_FSM;
 
+  
 
   TDC_DATA_VALID <= tdc_data_valid_i;  
   not_lvl2_busy <= not lvl2_busy_i;
@@ -818,9 +912,10 @@ begin
   LVL2_BUSY <= lvl2_busy_i;
   LVL2_READOUT_COMPLETED <= lvl2_busy_end_pulse;
   
+  
   LVL1_STARTED_CNTR: up_down_counter
     generic map (
-        NUMBER_OF_BITS => 8)
+        NUMBER_OF_BITS => 16)
     port map (
         CLK       => TDC_CLK,
         RESET     => RESET,
@@ -850,7 +945,7 @@ begin
     
   LVL2_STARTED_CNTR: up_down_counter
     generic map (
-        NUMBER_OF_BITS => 8)
+        NUMBER_OF_BITS => 16)
     port map (
         CLK       => CLK,
         RESET     => RESET,
@@ -875,7 +970,7 @@ begin
     if rising_edge(CLK) then  
       if RESET = '1' then
         lvl1_memory_busy_i <= '0';     
-      elsif (data_wr_data_count_i(14 downto 13)= "11") or (hd_wr_data_count_i(11 downto 2) = "1111111111") then
+      elsif ((data_wr_data_count_i(14 downto 13)= "11") and USE_EXTERNAL_SDRAM = 0) or (hd_wr_data_count_i(11 downto 2) = "1111111111") then
         lvl1_memory_busy_i <= '1';           
       else
         lvl1_memory_busy_i <= '0';     
@@ -883,6 +978,18 @@ begin
     end if;
   end process LVL1_MEMOMRY_BUSY_PROC;
 
+--  LVL1_MEMORY_BUSY_END : process (CLK, RESET)
+--  begin
+--    if rising_edge(CLK) then
+--      if RESET = '1' then
+--        lvl1_memory_busy_end = '0';
+--      elsif data_wr_data_count_i(14 downto 7) = x"ff" then
+--        lvl1_memory_busy_end = '1';
+--      else
+--        lvl1_memory_busy_end = '0'     
+--      end if;
+--    end if;
+--  end process LVL1_MEMORY_BUSY_END;
    
   
   REGISTERING_SIGNALS: process (CLK, RESET)
@@ -891,7 +998,7 @@ begin
       if RESET = '1' then  
         LVL1_BUSY <= '0';
       else
-        LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i;  --here
+        LVL1_BUSY <= lvl1_busy_i or lvl1_memory_busy_i or sdram_busy_i;--lvl1_busy_i or lvl1_memory_busy_i;--lvl1_or_lvl2_is_busy;--lvl1_busy_i;  --here
       end if;
     end if;
   end process REGISTERING_SIGNALS;
diff --git a/trb_v2b_fpga.stapl b/trb_v2b_fpga.stapl
index 0e5c19e..4190c6e 100644
--- a/trb_v2b_fpga.stapl
+++ b/trb_v2b_fpga.stapl
@@ -1,5 +1,5 @@
 NOTE "CREATOR" "Xilinx iMPACT Software";
-NOTE "DATE" "2009/08/14";
+NOTE "DATE" "2010/01/19";
 NOTE "STAPL_VERSION" "JESD71";
 NOTE "ALG_VERSION" "1";
 NOTE "DEVICE" "UNSPECIFIED";
@@ -1255,5962 +1255,4600 @@ IF (!X) THEN GOTO F;
 '  which might exceed the capacity of your run-time environment.
 '  WARNING: This STAPL file describes a data shift of more than 16K bits
 '  which might exceed the capacity of your run-time environment.
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 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@r200m0000GePMG0c1040W0000W210000O00108
-0000WH00000208102Y00XG0W880G240e020C0X6ZPmWa6O86W4G0W00Ge48n1300e4000003
-0C0010000030e00ZUm000eyggJuZUm000B1vEy3
+@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@hm0000mpmWKZo00
+20G0000WY00000Ca1W10c000004a001H0WG80G4408120K0106WGZnCaGI3C43W10W0010WG
+H060G0020000q47Cm00200000C0G1H0O0000GoNLdWd1040W0000WDtXV0m@@3
  ;
 ' // Loading device with a `jstart` instruction. 
 IRSCAN 10, $03cc
  ;
-' // INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
-' // INFO :  increased to ensure correct operation of generated System Ace files.
-D = 1200;
+D = 12;
 WAIT D CYCLES;
 ' //Loading device with 'bypass' instruction.
 IRSCAN 10, $03ff
@@ -8008,9 +6288,7 @@ POSTDR 0 ;
 ' // Loading device with a `jstart` instruction. 
 IRSCAN 10, $03cc
  ;
-' // INFO : The bitgen DCI match_cycle setting required that the RUNTEST wait time be
-' // INFO :  increased to ensure correct operation of generated System Ace files.
-D = 1200;
+D = 12;
 WAIT D CYCLES;
 ' //Checking done pin status.
 ' //Loading device with 'Bypass' instruction.
@@ -8059,4 +6337,4 @@ IF D > 2500 THEN CALL ADJUST_BIG_DELAY;
 IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY;
 ENDPROC;
 
-CRC 1C6B;
+CRC C912;
diff --git a/trb_v2b_fpga.ucf b/trb_v2b_fpga.ucf
index 625d27e..f3941d5 100644
--- a/trb_v2b_fpga.ucf
+++ b/trb_v2b_fpga.ucf
@@ -1,8 +1,8 @@
   # NET  +<1>	  LOC = AE28;
   # NET  +<2>	  LOC ="L2| IOSTANDARD = "LVTTL";
   # NET  +<3>	  LOC ="AJ18| IOSTANDARD = "LVTTL";
-   NET  ADDON_TO_TRB_CLKINN	  LOC ="G16";
-   NET  ADDON_TO_TRB_CLKINP	  LOC ="G17";
+   NET  ADDON_TO_TRB_CLKINN	  LOC ="G16"| IOSTANDARD="LVDS_25";
+   NET  ADDON_TO_TRB_CLKINP	  LOC ="G17"| IOSTANDARD="LVDS_25";
    NET "ADDON_TO_TRB_CLKINP" TNM_NET = ADDON_TO_TRB_CLKINP;
 #   TIMESPEC TS_ADDON_TO_TRB_CLKINP =PERIOD "ADDON_TO_TRB_CLKINP" 9 ns; #
   # ADDON_CONSTRAINTS
@@ -71,6 +71,7 @@
    NET  ADO_LVDS_OUT<7>	  LOC ="AP26";#| IOSTANDARD="LVDS_25";
    NET  ADO_LVDS_OUT<8>	  LOC ="AJ27";#| IOSTANDARD="LVDS_25";
    NET  ADO_LVDS_OUT<9>	  LOC ="AH27";#| IOSTANDARD="LVDS_25";
+
 #   NET  ADO_TTL	  LOC ="AL11"| IOSTANDARD = "LVTTL";
    NET  ADO_TTL<0>	  LOC ="AL11"| IOSTANDARD = "LVTTL";
    NET  ADO_TTL<1>	  LOC ="AL10"| IOSTANDARD = "LVTTL";
@@ -125,8 +126,8 @@
    NET  A_RESERVED	  LOC ="J11"| IOSTANDARD = "LVTTL";
    NET  A_SCK	  LOC ="H3";
    NET  A_SCKB	  LOC ="H2";
-   NET  A_SDI	  LOC ="F1";
-   NET  A_SDIB	  LOC ="G1";
+   NET  A_SDI	  LOC ="F1"| IOSTANDARD="LVDS_25";
+   NET  A_SDIB	  LOC ="G1"| IOSTANDARD="LVDS_25";
    NET  A_SDO	  LOC ="J4";
    NET  A_SDOB	  LOC ="K4";
    NET  A_TDC_BU_RESET	  LOC ="AK27";
@@ -148,8 +149,8 @@
    NET  B_RESERVED	  LOC ="C7"| IOSTANDARD = "LVTTL";
    NET  B_SCK	  LOC ="C4";
    NET  B_SCKB	  LOC ="C3";
-   NET  B_SDI	  LOC ="R11";
-   NET  B_SDIB	  LOC ="T11";
+   NET  B_SDI	  LOC ="R11"| IOSTANDARD="LVDS_25";
+   NET  B_SDIB	  LOC ="T11"| IOSTANDARD="LVDS_25";
    NET  B_SDO	  LOC ="G3";
    NET  B_SDOB	  LOC ="G2";
    NET  B_TDC_BU_RESET	  LOC ="AG25";
@@ -171,8 +172,8 @@
    NET  C_RESERVED	  LOC ="F8"| IOSTANDARD = "LVTTL";
    NET  C_SCK	  LOC ="P7";
    NET  C_SCKB	  LOC ="P6";
-   NET  C_SDI	  LOC ="D1";
-   NET  C_SDIB	  LOC ="E1";
+   NET  C_SDI	  LOC ="D1"| IOSTANDARD="LVDS_25";
+   NET  C_SDIB	  LOC ="E1"| IOSTANDARD="LVDS_25";
    NET  C_SDO	  LOC ="F4";
    NET  C_SDOB	  LOC ="F3";
    NET  C_TDC_BU_RESET	  LOC ="AP31";
@@ -192,148 +193,148 @@
    NET  DBAD	  LOC ="M28"| IOSTANDARD = "LVTTL";
    NET  DGOOD	  LOC ="H34"| IOSTANDARD = "LVTTL";
    NET  DINT	  LOC ="L31"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<0>	  LOC ="AA23"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<1>	  LOC ="AA24"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<2>	  LOC ="AJ34"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<3>	  LOC ="AH34"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<4>	  LOC ="AD27"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<5>	  LOC ="AC27"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<6>	  LOC ="AB25"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<7>	  LOC ="AB26"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<8>	  LOC ="AG30"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<9>	  LOC ="AG31"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<10>	  LOC ="AH32"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<11>	  LOC ="AH33"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<12>	  LOC ="AF29"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<13>	  LOC ="AF30"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<14>	  LOC ="AA28"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<15>	  LOC ="AA29"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<16>	  LOC ="W24"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<17>	  LOC ="Y24"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<18>	  LOC ="AB30"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<19>	  LOC ="AA30"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<20>	  LOC ="W25"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<21>	  LOC ="Y26"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<22>	  LOC ="AE33"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<23>	  LOC ="AE34"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<24>	  LOC ="AC32"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<25>	  LOC ="AC33"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<26>	  LOC ="AC29"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<27>	  LOC ="AC30"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<28>	  LOC ="AD34"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<29>	  LOC ="AC34"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<30>	  LOC ="AH18"| IOSTANDARD = "LVTTL";
-#   NET  DSPADDR<31>	  LOC ="AK18"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<0>	  LOC ="AA25"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<1>	  LOC ="AA26"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<2>	  LOC ="AE32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<3>	  LOC ="AD32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<4>	  LOC ="AC28"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<5>	  LOC ="AB28"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<6>	  LOC ="AD30"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<7>	  LOC ="AD31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<8>	  LOC ="AG32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<9>	  LOC ="AG33"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<10>	  LOC ="AF33"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<11>	  LOC ="AF34"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<12>	  LOC ="AE29"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<13>	  LOC ="AD29"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<14>	  LOC ="AF31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<15>	  LOC ="AE31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<16>	  LOC ="AK31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<17>	  LOC ="AK32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<18>	  LOC ="AK33"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<19>	  LOC ="AK34"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<20>	  LOC ="AM32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<21>	  LOC ="AM33"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<22>	  LOC ="AJ31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<23>	  LOC ="AJ32"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<24>	  LOC ="AB22"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<25>	  LOC ="AB23"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<26>	  LOC ="AL33"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<27>	  LOC ="AL34"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<28>	  LOC ="AM31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<29>	  LOC ="AL31"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<30>	  LOC ="AJ30"| IOSTANDARD = "LVTTL";
-#   NET  DSPDAT<31>	  LOC ="AH30"| IOSTANDARD = "LVTTL";
-#   NET  DSP_ACK	  LOC ="AB15"| IOSTANDARD = "LVTTL";
-#   NET  DSP_BM	  LOC ="AH19"| IOSTANDARD = "LVTTL";
-#   NET  DSP_BMS	  LOC ="AF15"| IOSTANDARD = "LVTTL";
-#   NET  DSP_BOFF	  LOC ="AK14"| IOSTANDARD = "LVTTL";
-#   NET  DSP_BRST	  LOC ="AN20"| IOSTANDARD = "LVTTL";
-  # NET  DSP_BUSLOCK	  LOC ="AC19"| IOSTANDARD = "LVTTL";
-  # NET  DSP_DMAR<0>	  LOC ="AD17"| IOSTANDARD = "LVTTL";
-  # NET  DSP_DMAR<1>	  LOC ="AC17"| IOSTANDARD = "LVTTL";
-  # NET  DSP_DMAR<2>	  LOC ="AM20"| IOSTANDARD = "LVTTL";
-  # NET  DSP_DMAR<3>	  LOC ="AL19"| IOSTANDARD = "LVTTL";
-  # NET  DSP_FLAG<0>	  LOC ="AE21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_FLAG<1>	  LOC ="AF21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_FLAG<2>	  LOC ="AP15"| IOSTANDARD = "LVTTL";
-  # NET  DSP_FLAG<3>	  LOC ="AN15"| IOSTANDARD = "LVTTL";
-#   NET  DSP_HBG	  LOC ="AD16"| IOSTANDARD = "LVTTL";
-#   NET  DSP_HBR	  LOC ="AB18"| IOSTANDARD = "LVTTL";
-  # NET  DSP_IOEN	  LOC ="AL18"| IOSTANDARD = "LVTTL";
-  # NET  DSP_IORD	  LOC ="AB16"| IOSTANDARD = "LVTTL";
-  # NET  DSP_IOWR	  LOC ="AB17"| IOSTANDARD = "LVTTL";
-#   NET  DSP_IRQ<0>	  LOC ="AG21"| IOSTANDARD = "LVTTL";
-#   NET  DSP_IRQ<1>	  LOC ="AF20"| IOSTANDARD = "LVTTL";
-#   NET  DSP_IRQ<2>	  LOC ="AF14"| IOSTANDARD = "LVTTL";
-#   NET  DSP_IRQ<3>	  LOC ="AG13"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIP<0>	  LOC ="AK29"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0ACKI	  LOC ="AM18"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1ACKO	  LOC ="AM15"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0BCMPI	  LOC ="AM16"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0BCMPO	  LOC ="AD21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIN<0>	  LOC ="AJ29"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1BCMPO	  LOC ="AJ20"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATOP<0>	  LOC ="AK21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATON<0>	  LOC ="AM23"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0ACKO	  LOC ="AM17"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1CLKINN	  LOC ="AL30"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1CLKOUTP	  LOC ="K18"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIN<0>	  LOC ="AM25"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0CLKINP	  LOC ="AP29"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1CLKOUTN	  LOC ="K17"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1BCMPI	  LOC ="AL15"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0CLKOUTN	  LOC ="AL25"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1CLKINP	  LOC ="AM30"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATOP<0>	  LOC ="AL23"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1ACKI	  LOC ="AD20"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0CLKINN	  LOC ="AN29"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIP<0>	  LOC ="AN25"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATON<0>	  LOC ="AL21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0CLKOUTP	  LOC ="AL24"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIN<1>	  LOC ="AN24"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIP<1>	  LOC ="AF28"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIN<1>	  LOC ="AE27"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATON<1>	  LOC ="AN23"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATOP<1>	  LOC ="AN22"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATOP<1>	  LOC ="AH28"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIP<1>	  LOC ="AP24"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATON<1>	  LOC ="AH29"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATON<2>	  LOC ="AH25"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATOP<2>	  LOC ="AJ25"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIP<2>	  LOC ="AF26"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATOP<2>	  LOC ="AP30"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIP<2>	  LOC ="AM26"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIN<2>	  LOC ="AE26"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATON<2>	  LOC ="AN30"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIN<2>	  LOC ="AM27"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIP<3>	  LOC ="AN32"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIP<3>	  LOC ="AP21"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATOP<3>	  LOC ="AL26"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATIN<3>	  LOC ="AP22"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATON<3>	  LOC ="AG28"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATOP<3>	  LOC ="AG27"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L1DATIN<3>	  LOC ="AN33"| IOSTANDARD = "LVTTL";
-  # NET  DSP_L0DATON<3>	  LOC ="AK26"| IOSTANDARD = "LVTTL";
-  # NET  DSP_MSH	  LOC ="AL14"| IOSTANDARD = "LVTTL";
-#   NET  DSP_RD	  LOC ="AJ22"| IOSTANDARD = "LVTTL";
-#   NET  DSP_RESET	  LOC ="AG22"| IOSTANDARD = "LVTTL";
-#   NET  DSP_RESET_OUT	  LOC ="AH22"| IOSTANDARD = "LVTTL";
-  # NET  DSP_TMROE	  LOC ="AP20"| IOSTANDARD = "LVTTL";
-#   NET  DSP_WRH	  LOC ="AJ21"| IOSTANDARD = "LVTTL";
-#   NET  DSP_WRL	  LOC ="AC15"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<0>	  LOC ="AA23"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<1>	  LOC ="AA24"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<2>	  LOC ="AJ34"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<3>	  LOC ="AH34"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<4>	  LOC ="AD27"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<5>	  LOC ="AC27"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<6>	  LOC ="AB25"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<7>	  LOC ="AB26"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<8>	  LOC ="AG30"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<9>	  LOC ="AG31"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<10>	  LOC ="AH32"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<11>	  LOC ="AH33"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<12>	  LOC ="AF29"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<13>	  LOC ="AF30"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<14>	  LOC ="AA28"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<15>	  LOC ="AA29"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<16>	  LOC ="W24"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<17>	  LOC ="Y24"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<18>	  LOC ="AB30"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<19>	  LOC ="AA30"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<20>	  LOC ="W25"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<21>	  LOC ="Y26"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<22>	  LOC ="AE33"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<23>	  LOC ="AE34"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<24>	  LOC ="AC32"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<25>	  LOC ="AC33"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<26>	  LOC ="AC29"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<27>	  LOC ="AC30"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<28>	  LOC ="AD34"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<29>	  LOC ="AC34"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<30>	  LOC ="AH18"| IOSTANDARD = "LVTTL";
+   NET  DSPADDR<31>	  LOC ="AK18"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<0>	  LOC ="AA25"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<1>	  LOC ="AA26"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<2>	  LOC ="AE32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<3>	  LOC ="AD32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<4>	  LOC ="AC28"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<5>	  LOC ="AB28"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<6>	  LOC ="AD30"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<7>	  LOC ="AD31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<8>	  LOC ="AG32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<9>	  LOC ="AG33"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<10>	  LOC ="AF33"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<11>	  LOC ="AF34"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<12>	  LOC ="AE29"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<13>	  LOC ="AD29"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<14>	  LOC ="AF31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<15>	  LOC ="AE31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<16>	  LOC ="AK31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<17>	  LOC ="AK32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<18>	  LOC ="AK33"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<19>	  LOC ="AK34"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<20>	  LOC ="AM32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<21>	  LOC ="AM33"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<22>	  LOC ="AJ31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<23>	  LOC ="AJ32"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<24>	  LOC ="AB22"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<25>	  LOC ="AB23"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<26>	  LOC ="AL33"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<27>	  LOC ="AL34"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<28>	  LOC ="AM31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<29>	  LOC ="AL31"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<30>	  LOC ="AJ30"| IOSTANDARD = "LVTTL";
+   NET  DSPDAT<31>	  LOC ="AH30"| IOSTANDARD = "LVTTL";
+   NET  DSP_ACK	  LOC ="AB15"| IOSTANDARD = "LVTTL";
+   NET  DSP_BM	  LOC ="AH19"| IOSTANDARD = "LVTTL";
+   NET  DSP_BMS	  LOC ="AF15"| IOSTANDARD = "LVTTL";
+   NET  DSP_BOFF	  LOC ="AK14"| IOSTANDARD = "LVTTL";
+   NET  DSP_BRST	  LOC ="AN20"| IOSTANDARD = "LVTTL";
+ # NET  DSP_BUSLOCK	  LOC ="AC19"| IOSTANDARD = "LVTTL";
+ # NET  DSP_DMAR<0>	  LOC ="AD17"| IOSTANDARD = "LVTTL";
+ # NET  DSP_DMAR<1>	  LOC ="AC17"| IOSTANDARD = "LVTTL";
+ # NET  DSP_DMAR<2>	  LOC ="AM20"| IOSTANDARD = "LVTTL";
+ # NET  DSP_DMAR<3>	  LOC ="AL19"| IOSTANDARD = "LVTTL";
+ # NET  DSP_FLAG<0>	  LOC ="AE21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_FLAG<1>	  LOC ="AF21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_FLAG<2>	  LOC ="AP15"| IOSTANDARD = "LVTTL";
+ # NET  DSP_FLAG<3>	  LOC ="AN15"| IOSTANDARD = "LVTTL";
+   NET  DSP_HBG	  LOC ="AD16"| IOSTANDARD = "LVTTL";
+   NET  DSP_HBR	  LOC ="AB18"| IOSTANDARD = "LVTTL";
+ # NET  DSP_IOEN	  LOC ="AL18"| IOSTANDARD = "LVTTL";
+ # NET  DSP_IORD	  LOC ="AB16"| IOSTANDARD = "LVTTL";
+ # NET  DSP_IOWR	  LOC ="AB17"| IOSTANDARD = "LVTTL";
+   NET  DSP_IRQ<0>	  LOC ="AG21"| IOSTANDARD = "LVTTL";
+   NET  DSP_IRQ<1>	  LOC ="AF20"| IOSTANDARD = "LVTTL";
+   NET  DSP_IRQ<2>	  LOC ="AF14"| IOSTANDARD = "LVTTL";
+   NET  DSP_IRQ<3>	  LOC ="AG13"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIP<0>	  LOC ="AK29"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0ACKI	  LOC ="AM18"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1ACKO	  LOC ="AM15"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0BCMPI	  LOC ="AM16"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0BCMPO	  LOC ="AD21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIN<0>	  LOC ="AJ29"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1BCMPO	  LOC ="AJ20"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATOP<0>	  LOC ="AK21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATON<0>	  LOC ="AM23"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0ACKO	  LOC ="AM17"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1CLKINN	  LOC ="AL30"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1CLKOUTP	  LOC ="K18"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIN<0>	  LOC ="AM25"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0CLKINP	  LOC ="AP29"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1CLKOUTN	  LOC ="K17"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1BCMPI	  LOC ="AL15"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0CLKOUTN	  LOC ="AL25"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1CLKINP	  LOC ="AM30"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATOP<0>	  LOC ="AL23"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1ACKI	  LOC ="AD20"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0CLKINN	  LOC ="AN29"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIP<0>	  LOC ="AN25"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATON<0>	  LOC ="AL21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0CLKOUTP	  LOC ="AL24"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIN<1>	  LOC ="AN24"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIP<1>	  LOC ="AF28"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIN<1>	  LOC ="AE27"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATON<1>	  LOC ="AN23"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATOP<1>	  LOC ="AN22"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATOP<1>	  LOC ="AH28"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIP<1>	  LOC ="AP24"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATON<1>	  LOC ="AH29"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATON<2>	  LOC ="AH25"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATOP<2>	  LOC ="AJ25"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIP<2>	  LOC ="AF26"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATOP<2>	  LOC ="AP30"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIP<2>	  LOC ="AM26"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIN<2>	  LOC ="AE26"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATON<2>	  LOC ="AN30"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIN<2>	  LOC ="AM27"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIP<3>	  LOC ="AN32"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIP<3>	  LOC ="AP21"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATOP<3>	  LOC ="AL26"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATIN<3>	  LOC ="AP22"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATON<3>	  LOC ="AG28"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATOP<3>	  LOC ="AG27"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L1DATIN<3>	  LOC ="AN33"| IOSTANDARD = "LVTTL";
+ # NET  DSP_L0DATON<3>	  LOC ="AK26"| IOSTANDARD = "LVTTL";
+ # NET  DSP_MSH	  LOC ="AL14"| IOSTANDARD = "LVTTL";
+   NET  DSP_RD	  LOC ="AJ22"| IOSTANDARD = "LVTTL";
+   NET  DSP_RESET	  LOC ="AG22"| IOSTANDARD = "LVTTL";
+   NET  DSP_RESET_OUT	  LOC ="AH22"| IOSTANDARD = "LVTTL";
+ # NET  DSP_TMROE	  LOC ="AP20"| IOSTANDARD = "LVTTL";
+   NET  DSP_WRH	  LOC ="AJ21"| IOSTANDARD = "LVTTL";
+   NET  DSP_WRL	  LOC ="AC15"| IOSTANDARD = "LVTTL";
    NET  DWAIT	  LOC ="H33"| IOSTANDARD = "LVTTL";
    NET  D_CSB	  LOC ="M2";
    NET  D_CS	  LOC ="M3";
@@ -341,8 +342,8 @@
    NET  D_RESERVED	  LOC ="G8"| IOSTANDARD = "LVTTL";
    NET  D_SCK	  LOC ="M6";
    NET  D_SCKB	  LOC ="M5";
-   NET  D_SDI	  LOC ="K3";
-   NET  D_SDIB	  LOC ="L3";
+   NET  D_SDI	  LOC ="K3"| IOSTANDARD="LVDS_25";
+   NET  D_SDIB	  LOC ="L3"| IOSTANDARD="LVDS_25";
    NET  D_SDO	  LOC ="K2";
    NET  D_SDOB	  LOC ="K1";
    NET  D_TDC_BU_RESET	  LOC ="K6";
@@ -476,8 +477,8 @@
   # NET  N<46481444>	  LOC ="AE19"| IOSTANDARD = "LVTTL";
   # NET  N<46736961>	  LOC ="AC25"| IOSTANDARD = "LVTTL";
   # NET  N<46741878>	  LOC ="AD26"| IOSTANDARD = "LVTTL";
-   NET  REF_TDC_CLK	  LOC ="F18";
-   NET  REF_TDC_CLKB	  LOC ="G18";
+   NET  REF_TDC_CLK	  LOC ="F18"| IOSTANDARD="LVDS_25";
+   NET  REF_TDC_CLKB	  LOC ="G18"| IOSTANDARD="LVDS_25";
    NET  RESET_VIRT	  LOC ="AF16"| IOSTANDARD = "LVTTL";
    NET  SFP_LOS	  LOC ="M27"| IOSTANDARD = "LVTTL";
  # NET  SFP_MOD<0>	  LOC ="R23"| IOSTANDARD = "LVTTL";
@@ -527,7 +528,7 @@
    NET  TDC_RESET	  LOC ="C5"| IOSTANDARD = "LVTTL";
     NET  TLK_CLK	  LOC ="AG16"| IOSTANDARD = "LVTTL";
     NET "TLK_CLK" TNM_NET =TLK_CLK;
-   TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9.5 ns;
+   TIMESPEC TS_TLK_CLK =PERIOD "TLK_CLK" 9 ns;
     NET  TLK_ENABLE	  LOC ="R24"| IOSTANDARD = "LVTTL";
     NET  TLK_LCKREFN	  LOC ="L28"| IOSTANDARD = "LVTTL";
     NET  TLK_LOOPEN	  LOC ="R19"| IOSTANDARD = "LVTTL";
@@ -550,7 +551,7 @@
     NET  TLK_RXD<15>	  LOC ="G33"| IOSTANDARD = "LVTTL";
     NET  TLK_RX_CLK	  LOC ="AF18"| IOSTANDARD = "LVTTL";
     NET "TLK_RX_CLK" TNM_NET =TLK_RX_CLK;
-   TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9.5 ns;
+   TIMESPEC TS_TLK_RX_CLK =PERIOD "TLK_RX_CLK" 9 ns;
     NET  TLK_RX_DV	  LOC ="M30"| IOSTANDARD = "LVTTL";
     NET  TLK_RX_ER	  LOC ="P20"| IOSTANDARD = "LVTTL";
     NET  TLK_TXD<0>	  LOC ="H27"| IOSTANDARD = "LVTTL";
@@ -582,64 +583,160 @@
    NET  VIRT_TRST	  LOC ="N29"| IOSTANDARD = "LVTTL";
    NET  VIR_TRIG	  LOC ="E3"| IOSTANDARD="LVDS_25";
    NET  VIR_TRIGB	  LOC ="E2"| IOSTANDARD="LVDS_25";
-#   NET  VSD_A<0>	  LOC ="F23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<1>	  LOC ="E23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<2>	  LOC ="D26"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<3>	  LOC ="E26"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<4>	  LOC ="F24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<5>	  LOC ="E24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<6>	  LOC ="D27"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<7>	  LOC ="E27"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<8>	  LOC ="G23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<9>	  LOC ="H24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<10>	  LOC ="A28"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<11>	  LOC ="A29"| IOSTANDARD = "LVTTL";
-#   NET  VSD_A<12>	  LOC ="B25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_BA<0>	  LOC ="C25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_BA<1>	  LOC ="J25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_CAS	  LOC ="G28"| IOSTANDARD = "LVTTL";
-#   NET  VSD_CKE	  LOC ="D30"| IOSTANDARD = "LVTTL";
-#   NET  VSD_CLOCK	  LOC ="B28"| IOSTANDARD = "LVTTL";
-#   NET  VSD_CSEH	  LOC ="G27"| IOSTANDARD = "LVTTL";
-#   NET  VSD_CSEL	  LOC ="D31"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<0>	  LOC ="B23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<1>	  LOC ="A23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<2>	  LOC ="A26"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<3>	  LOC ="B26"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<4>	  LOC ="A24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<5>	  LOC ="A25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<6>	  LOC ="G25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<7>	  LOC ="H25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<8>	  LOC ="C23"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<9>	  LOC ="C24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<10>	  LOC ="F25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<11>	  LOC ="F26"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<12>	  LOC ="D24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<13>	  LOC ="D25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<14>	  LOC ="B27"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<15>	  LOC ="C27"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<16>	  LOC ="C22"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<17>	  LOC ="B22"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<18>	  LOC ="A30"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<19>	  LOC ="B30"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<20>	  LOC ="K24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<21>	  LOC ="J24"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<22>	  LOC ="C29"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<23>	  LOC ="C30"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<24>	  LOC ="B21"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<25>	  LOC ="A21"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<26>	  LOC ="E28"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<27>	  LOC ="F28"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<28>	  LOC ="A31"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<29>	  LOC ="B31"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<30>	  LOC ="E31"| IOSTANDARD = "LVTTL";
-#   NET  VSD_D<31>	  LOC ="F31"| IOSTANDARD = "LVTTL";
-#   NET  VSD_DQML<0>	  LOC ="F30"| IOSTANDARD = "LVTTL";
-#   NET  VSD_DQML<1>	  LOC ="D29"| IOSTANDARD = "LVTTL";
-#   NET  VSD_DQML<2>	  LOC ="E29"| IOSTANDARD = "LVTTL";
-#   NET  VSD_DQML<3>	  LOC ="L25"| IOSTANDARD = "LVTTL";
-#   NET  VSD_RAS	  LOC ="F29"| IOSTANDARD = "LVTTL";
-#   NET  VSD_WE	  LOC ="K26"| IOSTANDARD = "LVTTL";
+
+   NET  VSD_A<0>	  LOC ="F23"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<1>	  LOC ="E23"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<2>	  LOC ="D26"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<3>	  LOC ="E26"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<4>	  LOC ="F24"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<5>	  LOC ="E24"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<6>	  LOC ="D27"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<7>	  LOC ="E27"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<8>	  LOC ="G23"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<9>	  LOC ="H24"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<10>	  LOC ="A28"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<11>	  LOC ="A29"| IOSTANDARD = "LVTTL";
+   NET  VSD_A<12>	  LOC ="B25"| IOSTANDARD = "LVTTL";
+   NET  VSD_BA<0>	  LOC ="C25"| IOSTANDARD = "LVTTL";
+   NET  VSD_BA<1>	  LOC ="J25"| IOSTANDARD = "LVTTL";
+   NET  VSD_CAS	  LOC ="G28"| IOSTANDARD = "LVTTL";
+   NET  VSD_CKE	  LOC ="D30"| IOSTANDARD = "LVTTL";
+   NET  VSD_CLOCK	  LOC ="B28"| IOSTANDARD = "LVTTL";
+   NET  VSD_CSEH	  LOC ="G27"| IOSTANDARD = "LVTTL";
+   NET  VSD_CSEL	  LOC ="D31"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<0>	  LOC ="B23"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<1>	  LOC ="A23"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<2>	  LOC ="A26"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<3>	  LOC ="B26"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<4>	  LOC ="A24"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<5>	  LOC ="A25"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<6>	  LOC ="G25"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<7>	  LOC ="H25"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<8>	  LOC ="C23"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<9>	  LOC ="C24"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<10>	  LOC ="F25"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<11>	  LOC ="F26"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<12>	  LOC ="D24"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<13>	  LOC ="D25"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<14>	  LOC ="B27"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<15>	  LOC ="C27"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<16>	  LOC ="C22"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<17>	  LOC ="B22"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<18>	  LOC ="A30"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<19>	  LOC ="B30"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<20>	  LOC ="K24"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<21>	  LOC ="J24"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<22>	  LOC ="C29"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<23>	  LOC ="C30"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<24>	  LOC ="B21"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<25>	  LOC ="A21"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<26>	  LOC ="E28"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<27>	  LOC ="F28"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<28>	  LOC ="A31"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<29>	  LOC ="B31"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<30>	  LOC ="E31"| IOSTANDARD = "LVTTL";
+   NET  VSD_D<31>	  LOC ="F31"| IOSTANDARD = "LVTTL";
+   NET  VSD_DQML<0>	  LOC ="F30"| IOSTANDARD = "LVTTL";
+   NET  VSD_DQML<1>	  LOC ="D29"| IOSTANDARD = "LVTTL";
+   NET  VSD_DQML<2>	  LOC ="E29"| IOSTANDARD = "LVTTL";
+   NET  VSD_DQML<3>	  LOC ="L25"| IOSTANDARD = "LVTTL";
+   NET  VSD_RAS	          LOC ="F29"| IOSTANDARD = "LVTTL";
+   NET  VSD_WE	          LOC ="K26"| IOSTANDARD = "LVTTL";
+
+   NET  VSD_A<0>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<1>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<2>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<3>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<4>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<5>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<6>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<7>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<8>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<9>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<10>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<11>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_A<12>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_BA<0>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_BA<1>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_CAS	          TNM =SDRAM_OUT_GROUP;
+   NET  VSD_CKE	          TNM =SDRAM_OUT_GROUP;
+   NET  VSD_CLOCK	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_CSEH	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_CSEL	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<0>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<1>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<2>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<3>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<4>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<5>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<6>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<7>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<8>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<9>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<10>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<11>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<12>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<13>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<14>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<15>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<16>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<17>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<18>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<19>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<20>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<21>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<22>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<23>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<24>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<25>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<26>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<27>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<28>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<29>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<30>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_D<31>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_DQML<0>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_DQML<1>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_DQML<2>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_DQML<3>	  TNM =SDRAM_OUT_GROUP;
+   NET  VSD_RAS	          TNM =SDRAM_OUT_GROUP;
+   NET  VSD_WE	          TNM =SDRAM_OUT_GROUP;
+
+   NET  VSD_D<0>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<1>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<2>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<3>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<4>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<5>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<6>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<7>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<8>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<9>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<10>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<11>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<12>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<13>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<14>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<15>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<16>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<17>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<18>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<19>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<20>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<21>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<22>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<23>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<24>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<25>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<26>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<27>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<28>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<29>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<30>	  TNM =SDRAM_IN_GROUP;
+   NET  VSD_D<31>	  TNM =SDRAM_IN_GROUP;
+
+TIMEGRP "SDRAM_OUT_GROUP" OFFSET = OUT 2 ns BEFORE "VIRT_CLK" HIGH;
+TIMEGRP "SDRAM_IN_GROUP" OFFSET = IN 3 ns BEFORE "VIRT_CLK" HIGH;
 # OFFSET=OUT 2 ns BEFORE "VIRT_CLK" HIGH;
 # OFFSET=IN 6 ns BEFORE "VIRT_CLK" HIGH;
 
@@ -647,12 +744,12 @@
 # OFFSET=OUT 2 ns BEFORE "REF_TDC_CLK" HIGH;
 
  NET "VIRT_CLK" TNM_NET =VIRT_CLK;
- TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9.5 ns;
+ TIMESPEC TS_VIRT_CLK =PERIOD "VIRT_CLK" 9 ns;
  NET "REF_TDC_CLK" TNM_NET = REF_TDC_CLK;
  TIMESPEC TS_REF_TDC_CLK = PERIOD "REF_TDC_CLK" 22 ns;
 
  NET "CLK" TNM_NET=CLK;
- TIMESPEC TS_CLK =PERIOD "CLK" 9.5 ns;
+ TIMESPEC TS_CLK =PERIOD "CLK" 9 ns;
 
  NET "A_DATA_READY" TNM = TDC_NET_GROUP ;
  NET "B_DATA_READY" TNM = TDC_NET_GROUP ;
diff --git a/trb_v2b_fpga.vhd b/trb_v2b_fpga.vhd
index 6ec9dcc..c1cbc73 100644
--- a/trb_v2b_fpga.vhd
+++ b/trb_v2b_fpga.vhd
@@ -13,14 +13,19 @@ use work.trb_net_std.all;
 entity trb_v2b_fpga is
   generic (
     RW_SYSTEM            : integer range 1 to 2   := 1;  --1 -trb, 2 -addon with portE 10 9 as rw
-    TRBV2_TYPE           : integer range 0 to 5   := 5;
-                                   -- 0 - trbv2 + RPC or TOF or FWALL or Start or Veto,
+    TRBV2_TYPE           : integer range 0 to 5   := 0;
+                                   -- 0 - trbv2 + RPC or TOF or FWALL or Start or
+                                   -- Veto (one board !),
                                    -- 1 - MDC,
                                    -- 2 - SHOWER,
                                    -- 3 - RICH
-                                   -- 4 - CTS+VULOM
-                                   -- 5 - CTS only, lvl2 is automatic
-    TRBNET_ENABLE        : integer range 0 to 3   := 2;  -- 0 - disable,
+                                   -- 4 - CTS+VULOM (trbent)
+                                   -- 5 - CTS only, lvl2 is automatic (trbent)
+                                   -- 6 - CTS plus TDC readout and waits for
+                                   -- external busy without trbnet
+                                   -- 7 - '6' is the source of the triggers
+                                   -- 8 - for tdc EUGEN readout
+    TRBNET_ENABLE        : integer range 0 to 3   := 0;  -- 0 - disable,
                                                          -- 1 - end point
                                                          -- 2 - cts
                                                          -- 3 - slow ctrl
@@ -36,17 +41,23 @@ entity trb_v2b_fpga is
                                                          --accesed by trbnet or
                                                          --etrax (read/write) -
                                                          --control
-    R_REGISTERS_NUMBER   : integer range 0 to 40  := 22;  --only read  - status
-    ENABLE_DMA           : integer range 1 to 2   := 1;  --1- DMA , 2 - no DMA
+    R_REGISTERS_NUMBER   : integer range 0 to 40  := 25;  --only read  - status
+    ENABLE_DMA           : integer range 1 to 2   := 2;  --1- DMA , 2 - no DMA
                                                          --2- also for trbnet
                                                          --end point !
     NUMBER_OFF_ADD_DATA  : integer range 0 to 255 := 8;
     REGIO_NUM_STAT_REGS  : integer range 0 to 255 := 2;
     REGIO_NUM_CTRL_REGS  : integer range 0 to 255 := 3;
-    DEBUG_OPTION         : integer range 0 to 8   := 2   --0 no debug
+    DEBUG_OPTION         : integer range 0 to 8   := 5;  --0 no debug
                                                          --1 trbnet enpoit
                                                          --2 trbent cts
                                                          --3 sfp
+                                                         --4 stand alone
+                                                         --5 stand alone plus adrram
+    TRIGGER_RW_REGISTERS_NUMBER  : integer range 0 to 40  := 4;
+    TRIGGER_R_REGISTERS_NUMBER  : integer range 0 to 40  := 4;
+    TRIGGER_INPUTS_NUMBER : integer range 0 to 60 := 51;
+    USE_EXTERNAL_SDRAM : integer range 0 to 1 := 1
     );
   port (
     -------------------------------------------------------------------------
@@ -327,7 +338,7 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       DEBUG          : out   std_logic_vector(31 downto 0);
       SFP_ADDRESS    : in    std_logic_vector(31 downto 0));
   end component;
-
+  
 
   component cts
     generic (
@@ -369,14 +380,17 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       CTS_STASUS_0UT_1           : out std_logic_vector(31 downto 0);
       CTS_STASUS_0UT_2           : out std_logic_vector(31 downto 0);
       CTS_CTRL_IN_0              : in  std_logic_vector(31 downto 0);
-      CTS_CTRL_IN_1              : in  std_logic_vector(31 downto 0));
+      CTS_CTRL_IN_1              : in  std_logic_vector(31 downto 0);
+      CTS_CTRL_IN_2              : in  std_logic_vector(31 downto 0)
+      );
   end component;
 
   component tdc_interfacev2
     generic (
       ENABLE_DMA          : natural;
       NUMBER_OFF_ADD_DATA : natural;
-      TRBV2_TYPE          : natural
+      TRBV2_TYPE          : natural;
+      USE_EXTERNAL_SDRAM  : natural
       );
     port (
       CLK                    : in  std_logic;
@@ -425,7 +439,15 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       TRB_ID                 : in  std_logic_vector(31 downto 0);
       LVL1_FINISHED          : out std_logic;
       LVL2_FINISHED          : out std_logic;
-      TRBNET_HEADER_BUILD    : in  std_logic
+      TRBNET_HEADER_BUILD    : in  std_logic;
+      RD_EN               : out  std_logic;
+      WR_EN               : out  std_logic;
+      WR_READY            : in std_logic;
+      RD_READY            : in std_logic;
+      DATA_IN             : in  std_logic_vector(31 downto 0);
+      DATA_OUT            : out std_logic_vector(31 downto 0);
+      SDRAM_BUSY          : in std_logic
+
       );
   end component;
 
@@ -523,7 +545,74 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       );
   end component;
 
-
+  component sdram_controller
+    port (
+      CLK               : in    std_logic;
+      RESET             : in    std_logic;
+      DATA_CLK_IN       : in    std_logic;
+      DATA_WRITE        : in    std_logic;
+      WRITE_READY       : out   std_logic;
+      WRITE_DATA_IN     : in    std_logic_vector(31 downto 0);
+      WRITE_BUSY        : out   std_logic;
+      DATA_READ         : in    std_logic;
+      DATA_READ_REQUEST : in    std_logic;
+      READ_READY        : out   std_logic;
+      READ_DATA_OUT     : out   std_logic_vector(31 downto 0);
+      READ_BUSY         : out   std_logic;
+      RAM_DEBUG_00      : out   std_logic_vector(31 downto 0);
+      RAM_DEBUG_01      : out   std_logic_vector(31 downto 0);
+      RAM_DEBUG_02      : out   std_logic_vector(31 downto 0);
+      SDARM_CLK         : out   std_logic;
+      CKE               : out   std_logic;
+      CE                : out   std_logic;
+      RAS               : out   std_logic;
+      CAS               : out   std_logic;
+      WE                : out   std_logic;
+      BA                : out   std_logic_vector(1 downto 0);
+      ADDR              : out   std_logic_vector(12 downto 0);
+      DATA              : inout std_logic_vector(31 downto 0);
+      DQMH              : out   std_logic;
+      DQML              : out   std_logic);
+  end component;
+  
+  component sdram_fpga_interface
+    generic (
+      USE_EXTERNAL_SDRAM : natural);
+    port (
+      CLK                 : in  std_logic;
+      READOUT_CLK         : in  std_logic;
+      RESET               : in  std_logic;
+      RD_EN               : in  std_logic;
+      WR_EN               : in  std_logic;
+      WR_READY            : out std_logic;
+      RD_READY            : out std_logic;
+      DATA_IN             : in  std_logic_vector(31 downto 0);
+      DATA_OUT            : out std_logic_vector(31 downto 0);
+      SDRAM_BUSY          : out std_logic;
+      INTERNAL_STROBE    : in    std_logic;
+      INTERNAL_DATA_IN   : in    std_logic_vector(31 downto 0);
+      INTERNAL_DATA_OUT  : out   std_logic_vector(31 downto 0);
+      INTERNAL_ADDRESS   : in    std_logic_vector(31 downto 0);
+      INTERNAL_MODE      : in    std_logic_vector(15 downto 0);  
+      INTERNAL_VALID     : out   std_logic;
+      SDRAM_DEBUG_00         : out std_logic_vector(31 downto 0);
+      SDRAM_DEBUG_01         : out std_logic_vector(31 downto 0);
+      SDRAM_DEBUG_02         : out std_logic_vector(31 downto 0);
+      CLK_SDRAM          : out   std_logic;
+      CKE                : out   std_logic;
+      CS                 : out   std_logic;
+      RAS                : out   std_logic;
+      CAS                : out   std_logic;
+      WE                 : out   std_logic;
+      DQM                : out   std_logic_vector(3 downto 0);
+      BA                 : out   std_logic_vector (1 downto 0);
+      A                  : out   std_logic_vector(12 downto 0);
+      DQ                 : inout std_logic_vector(31 downto 0);
+      DQMH               : out   std_logic;
+      DQML               : out   std_logic
+      );
+  end component;
+  
   component dsp_interface
     port (
       -- signal to/from dsp
@@ -973,9 +1062,42 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
       signal_in : in  std_logic;
       pulse     : out std_logic);
   end component;
+
+  -----------------------------------------------------------------------------
+  -- trigger logic interface
+  -----------------------------------------------------------------------------
+  component trigger_interface
+    generic (
+      TRIGGER_RW_REGISTERS_NUMBER : natural;
+      TRIGGER_R_REGISTERS_NUMBER  : natural;
+      TRIGGER_INPUTS_NUMBER : natural
+      );
+    port (
+      RESET                  : in  std_logic;
+      CLK_100                : in  std_logic;
+      CLK_50                 : in  std_logic;
+      CLK_300                : in  std_logic;
+      DETECTOR_SIGNALS_IN    : in  std_logic_vector(21 downto 0);
+      TRIGGER_SIGNALS_OUT    : out std_logic_vector(21 downto 0);
+      TRIGGER_DATA_OUT       : out std_logic_vector(31 downto 0);
+      TRIGGER_DATA_VALID_OUT : out std_logic;
+      TRIGGER_BUSY_OUT       : out std_logic;
+      TRIGGER_BUSY_IN        : in  std_logic;
+      RW_DATA_IN             : in  std_logic_vector(31 downto 0);
+      RW_DATA_OUT            : out std_logic_vector(31 downto 0);
+      RW_ADDRESS_IN          : in  std_logic_vector(31 downto 0);
+      RW_MODE_IN             : in  std_logic_vector(15 downto 0);
+      RW_VALID_OUT           : out std_logic;
+      RW_ACK_IN              : in  std_logic;
+      DISP_A                 : out std_logic_vector(6 downto 0);
+      DISP_D                 : out std_logic_vector(1 downto 0);
+      DISP_WR                : out std_logic);
+  end component;
+  
 -------------------------------------------------------------------------------
 -- SIGNALS
 -------------------------------------------------------------------------------
+
 --  constant VaaaaaaaaaERSION_NUMBER_TIME : integer := 1245150983;  --interface
   constant HOW_MANY_CHANNELS : integer := 1;
 
@@ -1046,7 +1168,11 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal lvl1_trigger_i           : std_logic;
   signal lvl2_trigger_code_i      : std_logic_vector(3 downto 0)  := x"0";
   signal lvl2_trigger_tag_i       : std_logic_vector(15 downto 0) := x"0000";
-  signal lvl2_local_busy_i        : std_logic;
+  signal lvl2_local_busy_i        : std_logic:='0';
+  signal lvl1_local_busy_i        : std_logic:='0';
+  signal lvl1_external_busy_i : std_logic;
+  signal lvl2_external_busy_i : std_logic;
+
   --etrax 
   signal etrax_bus_busy_i         : std_logic;  --should go to busy logic !? 
   signal etrax_is_ready_to_read_i : std_logic;
@@ -1126,10 +1252,21 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
 
   --sdram
   signal sdram_register_00_i    : std_logic_vector(31 downto 0);
-  signal sdram_external_valid_i : std_logic;
+  signal sdram_external_valid_i : std_logic:='0';
   signal sdram_data_out_i       : std_logic_vector(31 downto 0);
   signal vsd_cs_i               : std_logic;
-
+  signal dqmh_i : std_logic;
+  signal dqml_i : std_logic;
+  signal rd_en_i       : std_logic;
+  signal wr_en_i       : std_logic;
+  signal wr_ready_i    : std_logic;
+  signal rd_ready_i    : std_logic;
+  signal data_in_i     : std_logic_vector(31 downto 0);
+  signal data_out_i    : std_logic_vector(31 downto 0);
+  signal sdram_busy_i  : std_logic;
+  signal sdram_debug_i : std_logic_vector(31 downto 0);
+  signal readout_sdram_int_clk : std_logic;
+  signal sdram_data_ready_i : std_logic;
   --scalers
   type   scaler_counter_arr is array(0 to 7) of std_logic_vector(31 downto 0);
   signal scaler_counter : scaler_counter_arr;
@@ -1177,6 +1314,13 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal not_ipu_dataready_out_i     : std_logic;
   signal ipu_dataready_out_end_pulse : std_logic;
   signal dummy_lvl1_trigger          : std_logic;
+  signal dummy_lvl2_trigger          : std_logic;
+  signal clk40_a : std_logic;
+  signal clk40_b : std_logic;
+  signal clk40_c : std_logic;
+  signal not_tdc_clk : std_logic;
+  signal counter_for_clk : std_logic_vector(7 downto 0);
+  
   --lvl1
   signal trg_send_in_i               : std_logic;
   signal trg_type_in_i               : std_logic_vector (3 downto 0);
@@ -1294,10 +1438,26 @@ architecture trb_v2b_fpga of trb_v2b_fpga is
   signal ref_time_counter        : std_logic_vector(7 downto 0);
 
 
+  
   signal lvl1_cts_busy_out_i   : std_logic;
   signal lvl2_cts_busy_out_i   : std_logic;
   signal lvl1_rnd_number_out_i : std_logic_vector(7 downto 0);
   signal lvl2_rnd_number_out_i : std_logic_vector(7 downto 0);
+  signal lvl1_in_chain_busy : std_logic;
+  signal lvl2_in_chain_busy : std_logic;
+  signal lvl1_in_chain_busy_end : std_logic;
+  signal lvl2_in_chain_busy_end : std_logic;
+  signal lvl1_all_busy_or : std_logic;
+  signal lvl2_all_busy_or : std_logic;
+  
+  --lvl1 trigger logic
+  signal trigger_rw_valid_out_i : std_logic;
+  signal trigger_rw_data_out_i : std_logic_vector(31 downto 0);
+  
+  signal save_lvl2_finished : std_logic;
+
+  --trb tester
+  signal trb_tester_busy : std_logic;
 begin
 
 
@@ -1310,6 +1470,9 @@ begin
       if global_reset_counter < x"e" then
         global_reset_counter <= global_reset_counter + 1;
         reset_i              <= '1';
+      elsif (med_stat_op_in_i(13) = '1' or med_stat_op_in_i(14) = '1') and  TRBNET_ENABLE > 0  then
+        global_reset_counter <= x"0";
+        reset_i              <= '0';
       else
         global_reset_counter <= global_reset_counter;
         reset_i              <= '0';
@@ -1349,7 +1512,7 @@ begin
   -- AddOn clk ----------------------------------------------------------------
   IBUFGDS_ADDCLK : IBUFDS
     generic map (
-      IOSTANDARD => "LVDS_25_DCI")
+      DIFF_TERM => true)
     port map (
       O  => addon_clk,                  --CLK,
       I  => ADDON_TO_TRB_CLKINP,
@@ -1359,90 +1522,65 @@ begin
   -- TDC ----------------------------------------------------------------------
   IBUFGDS_TDC_CLK : IBUFGDS
     generic map (
-      IOSTANDARD => "LVDS_25_DCI")      --_DCI
+      DIFF_TERM => true)      --
     port map (
       O  => tdc_clk,
       I  => REF_TDC_CLK,
       IB => REF_TDC_CLKB  -- Diff_n clock buffer input (connect to top-level port)
       );
-  IBUFDS_TRIGG_A       : OBUFDS port map (O             => A_TRIGGER, OB => A_TRIGGERB, I => a_trigg);
-  IBUFDS_TRIGG_B       : OBUFDS port map (O             => B_TRIGGER, OB => B_TRIGGERB, I => b_trigg);
-  IBUFDS_TRIGG_C       : OBUFDS port map (O             => C_TRIGGER, OB => C_TRIGGERB, I => c_trigg);
-  IBUFDS_TRIGG_D       : OBUFDS port map (O             => D_TRIGGER, OB => D_TRIGGERB, I => d_trigg);
-  OBUFDS_BUNCH_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_TDC_BU_RESET, OB => A_TDC_BU_RESETB , I => bunch_reset_i);
-  OBUFDS_EVENT_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_TDC_EV_RESET, OB => A_TDC_EV_RESETB , I => event_reset_i);
-  OBUFDS_BUNCH_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_TDC_BU_RESET, OB => B_TDC_BU_RESETB, I => bunch_reset_i);
-  OBUFDS_EVENT_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_TDC_EV_RESET, OB => B_TDC_EV_RESETB, I => event_reset_i);
-  OBUFDS_BUNCH_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_TDC_BU_RESET, OB => C_TDC_BU_RESETB, I => bunch_reset_i);
-  OBUFDS_EVENT_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_TDC_EV_RESET, OB => C_TDC_EV_RESETB, I => event_reset_i);
-  OBUFDS_BUNCH_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_TDC_BU_RESET, OB => D_TDC_BU_RESETB, I => bunch_reset_i);
-  OBUFDS_EVENT_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_TDC_EV_RESET, OB => D_TDC_EV_RESETB, I => event_reset_i);
+  IBUFDS_TRIGG_A       : OBUFDS port map (O => A_TRIGGER, OB => A_TRIGGERB, I => a_trigg);
+  IBUFDS_TRIGG_B       : OBUFDS port map (O => B_TRIGGER, OB => B_TRIGGERB, I => b_trigg);
+  IBUFDS_TRIGG_C       : OBUFDS port map (O => C_TRIGGER, OB => C_TRIGGERB, I => c_trigg);
+  IBUFDS_TRIGG_D       : OBUFDS port map (O => D_TRIGGER, OB => D_TRIGGERB, I => d_trigg);
+  OBUFDS_BUNCH_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => A_TDC_BU_RESET, OB => A_TDC_BU_RESETB, I => bunch_reset_i);
+  OBUFDS_EVENT_RESET_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => A_TDC_EV_RESET, OB => A_TDC_EV_RESETB, I => event_reset_i);
+  OBUFDS_BUNCH_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => B_TDC_BU_RESET, OB => B_TDC_BU_RESETB, I => bunch_reset_i);
+  OBUFDS_EVENT_RESET_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => B_TDC_EV_RESET, OB => B_TDC_EV_RESETB, I => event_reset_i);
+  OBUFDS_BUNCH_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => C_TDC_BU_RESET, OB => C_TDC_BU_RESETB, I => bunch_reset_i);
+  OBUFDS_EVENT_RESET_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => C_TDC_EV_RESET, OB => C_TDC_EV_RESETB, I => event_reset_i);
+  OBUFDS_BUNCH_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => D_TDC_BU_RESET, OB => D_TDC_BU_RESETB, I => bunch_reset_i);
+  OBUFDS_EVENT_RESET_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => D_TDC_EV_RESET, OB => D_TDC_EV_RESETB, I => event_reset_i);
 
   --fast trigg-----------------------------------------------------------------
-  IBUFDS_FAST_TRIGGER : IBUFDS generic map (DIFF_TERM => true)
-    port map (I => VIR_TRIG, IB => VIR_TRIGB, O => fast_ref_trigger);
+  IBUFDS_FAST_TRIGGER : IBUFDS generic map (DIFF_TERM => true)   port map (I => VIR_TRIG, IB => VIR_TRIGB, O => fast_ref_trigger);
 
   -- SPI ----------------------------------------------------------------------
 
   --A
-  OBUFDS_SCK_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_SCK, OB => A_SCKB, I => spi_sck_a);
-  OBUFDS_SDO_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_SDO, OB => A_SDOB, I => spi_sdo_a);
-  OBUFDS_CS_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_CS, OB => A_CSB, I => spi_cs_a);
-  IBUFDS_SDI_A : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map (I => A_SDI, IB => A_SDIB, O => spi_sdi_a);
+  OBUFDS_SCK_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => A_SCK, OB => A_SCKB, I => spi_sck_a);
+  OBUFDS_SDO_A : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => A_SDO, OB => A_SDOB, I => spi_sdo_a);
+  OBUFDS_CS_A  : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => A_CS,  OB => A_CSB,  I => spi_cs_a);
+  IBUFDS_SDI_A : IBUFDS generic map (DIFF_TERM => true)              port map (I => A_SDI, IB => A_SDIB, O => spi_sdi_a);
   spi_sck_a             <= fpga_register_07_i(0);
   spi_sdo_a             <= fpga_register_07_i(1);
   spi_cs_a              <= fpga_register_07_i(2);
   fpga_register_08_i(0) <= spi_sdi_a;
 
   --B
-  OBUFDS_SCK_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_SCK, OB => B_SCKB, I => spi_sck_b);
-  OBUFDS_SDO_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_SDO, OB => B_SDOB, I => spi_sdo_b);
-  OBUFDS_CS_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_CS, OB => B_CSB, I => spi_cs_b);
-  IBUFDS_SDI_B : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map (I => B_SDI, IB => B_SDIB, O => spi_sdi_b);
+  OBUFDS_SCK_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => B_SCK, OB => B_SCKB, I => spi_sck_b);
+  OBUFDS_SDO_B : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => B_SDO, OB => B_SDOB, I => spi_sdo_b);
+  OBUFDS_CS_B : OBUFDS generic map  (IOSTANDARD => "LVDS_25")        port map (O => B_CS, OB => B_CSB, I => spi_cs_b);
+  IBUFDS_SDI_B : IBUFDS generic map (DIFF_TERM => true)              port map (I => B_SDI, IB => B_SDIB, O => spi_sdi_b);
   spi_sck_b             <= fpga_register_07_i(3);
   spi_sdo_b             <= fpga_register_07_i(4);
   spi_cs_b              <= fpga_register_07_i(5);
   fpga_register_08_i(1) <= spi_sdi_b;
 
   --C
-  OBUFDS_SCK_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_SCK, OB => C_SCKB, I => spi_sck_c);
-  OBUFDS_SDO_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_SDO, OB => C_SDOB, I => spi_sdo_c);
-  OBUFDS_CS_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_CS, OB => C_CSB, I => spi_cs_c);
-  IBUFDS_SDI_C : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map (I => C_SDI, IB => C_SDIB, O => spi_sdi_c);
+  OBUFDS_SCK_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => C_SCK, OB => C_SCKB, I => spi_sck_c);
+  OBUFDS_SDO_C : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => C_SDO, OB => C_SDOB, I => spi_sdo_c);
+  OBUFDS_CS_C : OBUFDS generic map  (IOSTANDARD => "LVDS_25")        port map (O => C_CS, OB => C_CSB, I => spi_cs_c);
+  IBUFDS_SDI_C : IBUFDS generic map (DIFF_TERM => true)              port map (I => C_SDI, IB => C_SDIB, O => spi_sdi_c);
   spi_sck_c             <= fpga_register_07_i(6);
   spi_sdo_c             <= fpga_register_07_i(7);
   spi_cs_c              <= fpga_register_07_i(8);
   fpga_register_08_i(2) <= spi_sdi_c;
 
   --D
-  OBUFDS_SCK_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_SCK, OB => D_SCKB, I => spi_sck_d);
-  OBUFDS_SDO_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_SDO, OB => D_SDOB, I => spi_sdo_d);
-  OBUFDS_CS_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_CS, OB => D_CSB, I => spi_cs_d);
-  IBUFDS_SDI_D : IBUFDS generic map (IOSTANDARD => "LVDS_25_DCI")
-    port map (I => D_SDI, IB => D_SDIB, O => spi_sdi_d);
+  OBUFDS_SCK_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => D_SCK, OB => D_SCKB, I => spi_sck_d);
+  OBUFDS_SDO_D : OBUFDS generic map (IOSTANDARD => "LVDS_25")        port map (O => D_SDO, OB => D_SDOB, I => spi_sdo_d);
+  OBUFDS_CS_D : OBUFDS generic map (IOSTANDARD =>  "LVDS_25")        port map (O => D_CS, OB => D_CSB, I => spi_cs_d);
+  IBUFDS_SDI_D : IBUFDS generic map (DIFF_TERM => true)              port map (I => D_SDI, IB => D_SDIB, O => spi_sdi_d);
   spi_sck_d             <= fpga_register_07_i(9);
   spi_sdo_d             <= fpga_register_07_i(10);
   spi_cs_d              <= fpga_register_07_i(11);
@@ -1452,22 +1590,14 @@ begin
   -----------------------------------------------------------------------------
   -- Test signals
   -----------------------------------------------------------------------------
-  OBUFDS_TEST_A1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_TEST1, OB => A_TEST1B, I => test_a1);
-  OBUFDS_TEST_A2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => A_TEST2, OB => A_TEST2B, I => test_a2);
-  OBUFDS_TEST_B1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_TEST1, OB => B_TEST1B, I => test_b1);
-  OBUFDS_TEST_B2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => B_TEST2, OB => B_TEST2B, I => test_b2);
-  OBUFDS_TEST_C1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_TEST1, OB => C_TEST1B, I => test_c1);
-  OBUFDS_TEST_C2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => C_TEST2, OB => C_TEST2B, I => test_c2);
-  OBUFDS_TEST_D1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_TEST1, OB => D_TEST1B, I => test_d1);
-  OBUFDS_TEST_D2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")
-    port map (O => D_TEST2, OB => D_TEST2B, I => test_d2);
+  OBUFDS_TEST_A1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => A_TEST1, OB => A_TEST1B, I => test_a1);
+  OBUFDS_TEST_A2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => A_TEST2, OB => A_TEST2B, I => test_a2);
+  OBUFDS_TEST_B1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => B_TEST1, OB => B_TEST1B, I => test_b1);
+  OBUFDS_TEST_B2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => B_TEST2, OB => B_TEST2B, I => test_b2);
+  OBUFDS_TEST_C1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => C_TEST1, OB => C_TEST1B, I => test_c1);
+  OBUFDS_TEST_C2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => C_TEST2, OB => C_TEST2B, I => test_c2);
+  OBUFDS_TEST_D1 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => D_TEST1, OB => D_TEST1B, I => test_d1);
+  OBUFDS_TEST_D2 : OBUFDS generic map (IOSTANDARD => "LVDS_25")    port map (O => D_TEST2, OB => D_TEST2B, I => test_d2);
   --i should be able to switch on off 1 or 2
   COUNTER_FOR_TEST_1 : process (CLK, reset_i, test_counter_1)
   begin
@@ -1658,6 +1788,7 @@ begin
         TIMER_US_TICK_OUT         => open,
         STAT_DEBUG_1              => stat_debug_1_i,
         STAT_DEBUG_2              => stat_debug_2_i);
+        lvl2_local_busy_i <= lvl1_busy_i or lvl2_busy_i;
   end generate TRBnet_CTS;
 
 -------------------------------------------------------------------------------
@@ -1709,7 +1840,7 @@ begin
 -- cts
 -------------------------------------------------------------------------------
 
-  CTS_GENERATE : if TRBNET_ENABLE /= 1 generate
+  CTS_GENERATE : if TRBNET_ENABLE /= 1 and TRBV2_TYPE /=7 and DTU_ENABLE = 0 generate
     THE_CTS : cts
       generic map (
         TRBNET_ENABLE => TRBNET_ENABLE
@@ -1721,13 +1852,13 @@ begin
         LVL1_LVDS_TRIGGER_IN       => lvds_add_on_data(4 downto 0),
         LVL1_TTL_TRIGGER_IN        => ADO_TTL(20 downto 16),
         LVL1_FAST_TRIGG_IN         => fast_ref_trigger,
-        LVL1_TIMING_TRIGGER_OUT    => ado_lv_out_i(0),
-        LVL1_APV_TRIGGER_OUT       => ado_lv_out_i(1),
-        LVL1_VULOM_TRIGGER_IN      => lvl1_vulom_trigger,
-        LVL1_VULOM_TRIGGER_CODE_IN => vulom_lvl1_trigger_code_i,
-        LVL1_VULOM_TRIGGER_TAG_IN  => vulom_lvl1_trigger_tag_i,
+        LVL1_TIMING_TRIGGER_OUT    => open,--ado_lv_out_i(0),
+        LVL1_APV_TRIGGER_OUT       => open,--ado_lv_out_i(1),
+        LVL1_VULOM_TRIGGER_IN      => '0',--lvl1_vulom_trigger,
+        LVL1_VULOM_TRIGGER_CODE_IN => x"0",--vulom_lvl1_trigger_code_i,
+        LVL1_VULOM_TRIGGER_TAG_IN  => x"0000",--vulom_lvl1_trigger_tag_i,
         LVL1_VULOM_BUSY_IN         => '0',   --vulom_busy,
-        LVL1_LOCAL_BUSY            => '0',   --lvl1_busy_i,
+        LVL1_LOCAL_BUSY            => lvl1_local_busy_i,   --lvl1_busy_i,
         LVL1_TRBNET_BUSY           => trg_busy_out_i,
         LVL1_CTS_BUSY_OUT          => lvl1_cts_busy_out_i,
         LVL1_TRIGGER_OUT           => lvl1_trigger_i,
@@ -1751,18 +1882,29 @@ begin
         CTS_STASUS_0UT_1           => r_register_i(18),
         CTS_STASUS_0UT_2           => r_register_i(19),
         CTS_CTRL_IN_0              => rw_register_i(5),
-        CTS_CTRL_IN_1              => rw_register_i(6)
+        CTS_CTRL_IN_1              => rw_register_i(6),
+        CTS_CTRL_IN_2              => rw_register_i(7)
         );
 
+    ado_lv_out_i <= (others => '0');    
+    
   end generate CTS_GENERATE;
+  
+  
+  ENABLE_CTS_SIGNALS: if TRBNET_ENABLE = 2 generate
+    
+    ado_lv_out_i(2)   <= lvl1_cts_busy_out_i;
+    ado_lv_out_i(3)   <= lvl2_cts_busy_out_i;
+    ado_lv_out_i(4)   <= tdc_clk;--counter_for_clk(0);-- xor clk40_a;    
+    
+  end generate ENABLE_CTS_SIGNALS;
+
 
-  lvl2_local_busy_i <= lvl1_busy_i or lvl2_busy_i;
-  ado_lv_out_i(2)   <= lvl1_cts_busy_out_i;
-  ado_lv_out_i(3)   <= lvl2_cts_busy_out_i;
-  ado_lv_out_i(4)   <= TDC_CLK;
 
   ENABLE_DEBUG_CTS : if DEBUG_OPTION = 2 generate
-    ADO_TTL(0)           <= lvl1_trigger_i;
+    
+
+    ADO_TTL(0)           <= lvl1_trigger_i;--TDC_CLK;
     ADO_TTL(1)           <= lvl1_cts_busy_out_i;
     ADO_TTL(2)           <= lvl2_local_busy_i;
     ADO_TTL(3)           <= lvl1_finished_i;
@@ -1772,14 +1914,15 @@ begin
     ADO_TTL(7)           <= ipu_dataready_out_i;
     ADO_TTL(15 downto 8) <= ipu_data_out_i(31 downto 24);
   end generate ENABLE_DEBUG_CTS;
---    cts debug
---  
---    endpoint debug
---    ADO_TTL(7) <= ipu_dataready_in_i;
---    ADO_TTL(15 downto 0) <= ipu_dataready_in_i;
 
+  
+  STAND_ALONE_TRB: if TRBV2_TYPE = 0 generate
+    lvl1_local_busy_i <= lvl1_busy_i;
+    lvl2_local_busy_i <= lvl2_busy_i;
+  end generate STAND_ALONE_TRB;
 
-  RATE_DIODS_EN : if TRBNET_ENABLE = 1 generate
+ 
+  RATE_DIODS_EN : if TRBNET_ENABLE = 1 or TRBV2_TYPE = 7 generate
     
     THE_CTS : cts
       generic map (
@@ -1811,10 +1954,10 @@ begin
         LVL2_LOCAL_TRIGGER_IN      => '0',   --lvl2_local_trigger_in_i,
         LVL2_LOCAL_TRIGGER_CODE_IN => x"0",  --lvl2_local_trigger_code_in_i,
         LVL2_LOCAL_TRIGGER_TAG_IN  => x"0000",  --lvl2_local_trigger_tag_in_i,
-        LVL2_LOCAL_BUSY            => '0',
+        LVL2_LOCAL_BUSY            => dummy_lvl2_trigger,
         LVL2_TRBNET_BUSY           => '0',
         LVL2_CTS_BUSY_OUT          => open,
-        LVL2_TRIGGER_OUT           => open,
+        LVL2_TRIGGER_OUT           => dummy_lvl2_trigger,
         LVL2_TRIGGER_CODE_OUT      => open,
         LVL2_TRIGGER_TAG_OUT       => open,
         LVL2_RND_NUMBER_OUT        => open,
@@ -1822,11 +1965,87 @@ begin
         CTS_STASUS_0UT_1           => r_register_i(18),
         CTS_STASUS_0UT_2           => r_register_i(19),
         CTS_CTRL_IN_0              => x"00000400",
-        CTS_CTRL_IN_1              => (others => '0')
+        CTS_CTRL_IN_1              => (others => '0'),
+        CTS_CTRL_IN_2              => (others => '0')
         );
 
   end generate RATE_DIODS_EN;
 
+  
+  -- simple dtu without trbnet
+  
+  SIMPLE_DTU_SYSTEM: if TRBNET_ENABLE = 0 and TRBV2_TYPE =  7 generate
+
+    LVL1_TRIGGER_GENERATE : process (CLK, reset_i)
+    begin
+      if rising_edge(CLK) then
+        if reset_i = '1' then
+          lvl1_trigger_i <= '0';
+          lvl1_trigger_tag_i <= (others => '0');
+          lvl1_trigger_code_i <= (others => '0');
+        elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"1" then
+          lvl1_trigger_i <= '1';
+          lvl1_trigger_tag_i <= x"00" & med_data_out_i(7 downto 0);
+          lvl1_trigger_code_i <= med_data_out_i(11 downto 8);
+        else
+          lvl1_trigger_i <= '0';
+          lvl1_trigger_tag_i <= lvl1_trigger_tag_i; 
+          lvl1_trigger_code_i <= lvl1_trigger_code_i;
+        end if;
+      end if;
+    end process LVL1_TRIGGER_GENERATE;
+
+    LVL2_TRIGGER_GENERATE : process (CLK, reset_i)
+    begin
+      if rising_edge(CLK) then
+        if reset_i = '1' then
+          lvl2_trigger_i <= '0';
+        elsif med_dataready_out_i(0) = '1' and med_data_out_i(15 downto 12) = x"2" then
+          lvl2_trigger_i <= '1';
+        else
+          lvl2_trigger_i <= '0';
+        end if;
+      end if;
+    end process LVL2_TRIGGER_GENERATE;
+
+    SEND_LVL1_LVL2_ACK : process (CLK, reset_i)
+    begin
+      if rising_edge(CLK) then
+        if reset_i = '1' then
+          med_dataready_in_i(0) <= '0';
+          med_data_in_i <= x"0000";
+          save_lvl2_finished <= '0';
+        elsif lvl1_finished_i = '1' and lvl2_finished_i = '1' then
+           med_dataready_in_i(0) <= '1';
+           med_data_in_i <= x"1000";
+           save_lvl2_finished <= '1';
+        elsif lvl1_finished_i = '1' and lvl2_finished_i = '0' then
+           med_dataready_in_i(0) <= '1';
+           med_data_in_i <= x"1000";
+           save_lvl2_finished <= '0';
+        elsif lvl1_finished_i = '0' and lvl2_finished_i = '1' then
+           med_dataready_in_i(0) <= '0';
+           med_data_in_i <= x"0000";
+           save_lvl2_finished <= '1';
+        elsif lvl1_finished_i = '0' and lvl2_finished_i = '0' and save_lvl2_finished = '1' then
+           med_dataready_in_i(0) <= '1';
+           med_data_in_i <= x"2000";
+           save_lvl2_finished <= '0';
+        else
+          med_dataready_in_i(0) <= '0';
+          med_data_in_i <= x"0000";
+          save_lvl2_finished <= '0';
+        end if;
+      end if;
+    end process SEND_LVL1_LVL2_ACK;
+    med_read_in_i(0) <= '1';
+    ado_lv_out_i <= (others => '0');
+    
+  end generate SIMPLE_DTU_SYSTEM;
+  
+
+  -- trbnet end point
+    
   TRBnet_END_POINT : if TRBNET_ENABLE = 1 generate
     
     THE_TRBNET_END_POINT : trb_net16_endpoint_hades_full
@@ -1972,6 +2191,8 @@ begin
 --   -- media to api, api to media
 --   -----------------------------------------------------------------------------
 
+  TRBnet_MEDIA : if TRBNET_ENABLE > 0 or TRBV2_TYPE = 7 or (TRBV2_TYPE=0 and DTU_ENABLE=2)generate
+    
   TLK_RX_CLK_BUFR : BUFR
     port map(
       CE  => '1',
@@ -2019,7 +2240,8 @@ begin
       STAT_OP            => med_stat_op_in_i,
       CTRL_OP            => x"0000");
   DGOOD <= not med_stat_op_in_i(9);
-
+  end generate TRBnet_MEDIA;
+  
   DINT <= lvds_add_on_data(0) and
           lvds_add_on_data(1) and
           lvds_add_on_data(2) and
@@ -2045,8 +2267,41 @@ begin
           lvds_add_on_data(22) and
           lvds_add_on_data(23) and
           lvds_add_on_data(24) and
-          lvds_add_on_data(25);
-
+          lvds_add_on_data(25) and
+          addon_clk ;
+  
+-------------------------------------------------------------------------------
+-- lvl1 trigger logic
+-------------------------------------------------------------------------------
+  
+  THE_TRIGGER_INTERFACE: trigger_interface
+    generic map (
+      TRIGGER_RW_REGISTERS_NUMBER => TRIGGER_RW_REGISTERS_NUMBER,
+      TRIGGER_R_REGISTERS_NUMBER  => TRIGGER_R_REGISTERS_NUMBER,
+      TRIGGER_INPUTS_NUMBER       => TRIGGER_INPUTS_NUMBER)
+    port map (
+      RESET                  => reset_i,
+      CLK_100                => CLK,
+      CLK_50                 => '0',
+      CLK_300                => '0',
+      DETECTOR_SIGNALS_IN    => (others => '0'),
+      TRIGGER_SIGNALS_OUT    => open,
+      TRIGGER_DATA_OUT       => open,--TRIGGER_DATA_OUT,
+      TRIGGER_DATA_VALID_OUT => open,--TRIGGER_DATA_VALID_OUT,
+      TRIGGER_BUSY_OUT       => open,--TRIGGER_BUSY_OUT,
+      TRIGGER_BUSY_IN        => '0',--TRIGGER_BUSY_IN,
+      RW_DATA_IN             => external_data_out_i,
+      RW_DATA_OUT            => trigger_rw_data_out_i,
+      RW_ADDRESS_IN          => external_address_i,
+      RW_MODE_IN             => external_mode_i,
+      RW_VALID_OUT           => trigger_rw_valid_out_i,
+      RW_ACK_IN              => external_ack_i,
+      DISP_A                 => open,--DISP_A,
+      DISP_D                 => open,--DISP_D,
+      DISP_WR                => open--DISP_WR
+      );
+  
+  
 --------------------------------------------------------------------------- 
 -- tdc interface 
 ---------------------------------------------------------------------------
@@ -2054,12 +2309,12 @@ begin
 
 --    ADO_TTL(0) <= not_hades_trigger;
 --    ADO_TTL(1) <= trigger_to_tdc_i;
---    ADO_TTL(2) <= lvl1_busy_i;
+--
 --    ADO_TTL(3) <= A_DATA_READY;
 --    ADO_TTL(4) <= B_DATA_READY;
 --    ADO_TTL(5) <= C_DATA_READY;
 --    ADO_TTL(6) <= D_DATA_READY;
---    ADO_TTL(7) <= token_out_i;
+
 --    ADO_TTL(8) <= TOKEN_IN;
 --    ADO_TTL(9) <= lvl2_busy_i;
 --    ADO_TTL(10) <= bunch_reset_i;
@@ -2070,9 +2325,12 @@ begin
   TDC_RESET <= '0';  --fpga_register_06_i(5);--'0';
 
   --TDC TRB
-  TDC_INT_FOR_DIFF_PLATFORMSa : if TRBV2_TYPE = 0 generate
+  TDC_INT_FOR_DIFF_PLATFORMSa : if TRBV2_TYPE = 0 or TRBV2_TYPE = 6 or TRBV2_TYPE = 7  generate
+    ADO_TTL(7) <= lvl1_busy_i;--token_out_i;
+    ADO_TTL(2) <= lvl1_busy_i;      
     start_tdc_readout_i <= lvl1_trigger_i;
     tdc_clk_i           <= TDC_CLK;
+    readout_sdram_int_clk <= TDC_CLK;
     tdc_data_in_i       <= TDC_OUT;
     a_data_ready_i      <= A_DATA_READY;
     b_data_ready_i      <= B_DATA_READY;
@@ -2086,6 +2344,7 @@ begin
   TDC_INT_FOR_DIFF_PLATFORMSb : if TRBV2_TYPE = 1 or TRBV2_TYPE = 2 generate
     start_tdc_readout_i <= lvl1_trigger_i;
     tdc_clk_i           <= addon_clk;
+    readout_sdram_int_clk <= addon_clk;
     tdc_data_in_i       <= ADO_TTL(38 downto 7);
     a_data_ready_i      <= ADO_TTL(3);
     b_data_ready_i      <= ADO_TTL(3);
@@ -2114,6 +2373,7 @@ begin
   TDC_INT_FOR_DIFF_PLATFORMSc : if TRBV2_TYPE = 4 generate
     start_tdc_readout_i <= lvl1_trigger_i;
     tdc_clk_i           <= CLK;
+    readout_sdram_int_clk <= CLK;     
     tdc_data_in_i       <= vulom_event;
     a_data_ready_i      <= vulom_event_valid;  --start_readout_i;
     b_data_ready_i      <= vulom_event_valid;  --start_readout_i;
@@ -2137,6 +2397,7 @@ begin
         pulse     => ipu_dataready_out_end_pulse);
 
     tdc_clk_i      <= CLK;
+    readout_sdram_int_clk <= CLK;
     tdc_data_in_i  <= ipu_data_out_i;
     a_data_ready_i <= ipu_dataready_out_i;
     b_data_ready_i <= ipu_dataready_out_i;
@@ -2148,11 +2409,40 @@ begin
   end generate TDC_INT_FOR_DIFF_PLATFORMSd;
 
 
+  DEBUG_STAND_ALONE: if DEBUG_OPTION = 4 generate
+    ADO_TTL(0) <= lvl1_trigger_i;
+    ADO_TTL(1) <= lvl1_finished_i;
+    MAKE_BUSY_FOR_TRB_TESTER : process (CLK, reset_i)
+    begin
+      if rising_edge(CLK) then
+        if reset_i = '1' or lvl2_finished_i = '1' then
+          trb_tester_busy <= '0';
+        elsif lvl1_busy_i = '1' then
+          trb_tester_busy <= '1';
+        end if;
+      end if;
+    end process MAKE_BUSY_FOR_TRB_TESTER;
+    
+    ADO_TTL(2) <= trb_tester_busy;--lvl1_busy_i; 
+    ADO_TTL(3) <= A_DATA_READY;
+    ADO_TTL(4) <= B_DATA_READY;
+    ADO_TTL(5) <= C_DATA_READY;
+    ADO_TTL(6) <= D_DATA_READY;
+    ADO_TTL(7) <= token_out_i;
+    ADO_TTL(8) <= TOKEN_IN;
+    ADO_TTL(9) <= lvl2_trigger_i;
+    ADO_TTL(10) <= bunch_reset_i;
+    ADO_TTL(11) <= event_reset_i;
+    ADO_TTL(12) <= TDC_CLK;
+  end generate DEBUG_STAND_ALONE;
+
+
   TDC_INT : tdc_interfacev2
     generic map (
       ENABLE_DMA          => ENABLE_DMA,
       NUMBER_OFF_ADD_DATA => NUMBER_OFF_ADD_DATA,
-      TRBV2_TYPE          => TRBV2_TYPE
+      TRBV2_TYPE          => TRBV2_TYPE,
+      USE_EXTERNAL_SDRAM  => USE_EXTERNAL_SDRAM
       )
     port map (
       CLK                    => CLK,
@@ -2201,9 +2491,128 @@ begin
       TRB_ID                 => rw_register_i(4),
       LVL1_FINISHED          => lvl1_finished_i,
       LVL2_FINISHED          => lvl2_finished_i,
-      TRBNET_HEADER_BUILD    => rw_register_i(3)(31)
+      TRBNET_HEADER_BUILD    => rw_register_i(3)(31),
+      RD_EN       => rd_en_i,
+      WR_EN       => wr_en_i,
+      WR_READY    => wr_ready_i,
+      RD_READY    => rd_ready_i,
+      DATA_IN     => data_out_i,
+      DATA_OUT    => data_in_i,
+      SDRAM_BUSY  => sdram_busy_i
       );
 
+  -----------------------------------------------------------------------------
+  -- sdram to tdc interface
+  -----------------------------------------------------------------------------
+--  THE_SDRAM_FPGA_INTERFACE : sdram_fpga_interface
+--    generic map
+--      (
+--      USE_EXTERNAL_SDRAM => USE_EXTERNAL_SDRAM
+--      )
+--    port map (
+--      CLK               => CLK,
+--      READOUT_CLK       => TDC_CLK,     --readout_sdram_int_clk,
+--      RESET             => reset_i,
+--      RD_EN             => rd_en_i,
+--      WR_EN             => wr_en_i,
+--      WR_READY          => wr_ready_i,
+--      RD_READY          => rd_ready_i,
+--      DATA_IN           => data_in_i,
+--      DATA_OUT          => data_out_i,
+--      SDRAM_BUSY        => sdram_busy_i,
+--      INTERNAL_STROBE   => external_ack_i,
+--      INTERNAL_DATA_IN  => external_data_out_i,
+--      INTERNAL_DATA_OUT => sdram_data_out_i,
+--      INTERNAL_ADDRESS  => external_address_i,
+--      INTERNAL_MODE     => external_mode_i,
+--      INTERNAL_VALID    => sdram_external_valid_i,
+--      SDRAM_DEBUG_00    => r_register_i(22),
+--      SDRAM_DEBUG_01    => r_register_i(23),
+--      SDRAM_DEBUG_02    => r_register_i(24),
+--      CLK_SDRAM         => VSD_CLOCK,
+--      CKE               => VSD_CKE,
+--      CS                => vsd_cs_i,
+--      RAS               => VSD_RAS,
+--      CAS               => VSD_CAS,
+--      WE                => VSD_WE,
+--      BA                => VSD_BA,
+--      A                 => VSD_A,
+--      DQ                => VSD_D,
+--      DQMH              => dqmh_i,
+--      DQML              => dqml_i
+--      );
+
+  THE_SDRAM_CONTROLLER: sdram_controller
+    port map (
+      CLK               => CLK,
+      RESET             => reset_i,
+      DATA_CLK_IN       => TDC_CLK,
+      DATA_WRITE        => wr_en_i,
+      WRITE_READY       => open,
+      WRITE_DATA_IN     => data_in_i,
+      WRITE_BUSY        => open,
+      DATA_READ         => sdram_data_ready_i,
+      DATA_READ_REQUEST => rd_en_i,
+      READ_READY        => sdram_data_ready_i,
+      READ_DATA_OUT     => data_out_i,
+      READ_BUSY         => open,
+      RAM_DEBUG_00      => r_register_i(22),
+      RAM_DEBUG_01      => r_register_i(23),
+      RAM_DEBUG_02      => r_register_i(24),
+      SDARM_CLK         => VSD_CLOCK,
+      CKE               => VSD_CKE,
+      CE                => vsd_cs_i,
+      RAS               => VSD_RAS,
+      CAS               => VSD_CAS,
+      WE                => VSD_WE,
+      BA                => VSD_BA,
+      ADDR              => VSD_A,
+      DATA              => VSD_D,
+      DQMH              => dqmh_i,
+      DQML              => dqml_i);
+  
+  sdram_busy_i <= '0';
+  VSD_DQML(0) <= dqml_i;
+  VSD_DQML(1) <= dqmh_i;
+  VSD_DQML(2) <= dqml_i;
+  VSD_DQML(3) <= dqmh_i;
+  
+  VSD_CSEH <= vsd_cs_i;
+  VSD_CSEL <= vsd_cs_i;
+
+  ENABLE_DEBUG_SDRAM_READOUT : if DEBUG_OPTION = 5 generate
+
+    ADO_TTL(0)           <= r_register_i(23)(4);  --write data from tdc
+    ADO_TTL(1)           <= r_register_i(23)(1);  --read fifo to sdram
+--    ADO_TTL(2)           <= lvl2_local_busy_i; 
+    ADO_TTL(3)           <= r_register_i(23)(0);   --read fifo from sdram
+    ADO_TTL(4)           <= r_register_i(22)(28);  --write fifo from sdram
+    ADO_TTL(5)           <= r_register_i(23)(6);   -- read state
+    ADO_TTL(6)           <= r_register_i(23)(7);  --write state
+--    ADO_TTL(7)           <= ipu_dataready_out_i;
+--    ADO_TTL(8) <=  r_register_i(23)(6);
+--    ADO_TTL(11 downto 9)              <= r_register_i(22)(15 downto 13);
+    ADO_TTL(15 downto 8)  <= r_register_i(22)(23 downto 16);
+--    ADO_TTL(11 downto 8)   <= r_register_i(22)(27 downto 24);
+--    ADO_TTL(9)             <= r_register_i(23)(3);
+--    ADO_TTL(10)            <= r_register_i(22)(30);
+--    ADO_TTL(11)            <= r_register_i(23)(2);
+--    ADO_TTL(15 downto 8) <= r_register_i(23)(7 downto 0);
+--    ADO_TTL(8)            <= r_register_i(22)(19);
+--    ADO_TTL(9)            <= r_register_i(22)(29);
+--    ADO_TTL(10)           <= r_register_i(22)(21);
+--    ADO_TTL(11)           <= r_register_i(22)(25);
+--    ADO_TTL(12)           <= r_register_i(22)(8);
+    --ADO_TTL(12)           <= lvl1_trigger_i;
+    --ADO_TTL(13)           <= lvl2_trigger_i;
+
+--    ADO_TTL(13)           <= r_register_i(23)(0);
+--    ADO_TTL(14)           <= r_register_i(24)(0);
+--    ADO_TTL(15)           <= r_register_i(23)(25);
+
+  end generate ENABLE_DEBUG_SDRAM_READOUT;
+  
+
   -----------------------------------------------------------------------------
   -- lvl1 trigger logic 
   -----------------------------------------------------------------------------
@@ -2251,9 +2660,6 @@ begin
   c_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
   d_trigg <= trigger_to_tdc_i;  --fast_ref_trigger_pulse_synch;-- and enable_trigger_synch;--trigger_to_tdc_i;
 
-
-
-
   BLINK_TDC_DIODS_ON_TRBv2c : process (CLK, reset_i)
   begin
     if rising_edge(CLK) then
@@ -2278,7 +2684,7 @@ begin
 
   DBAD  <= lvl1_busy_i;
 --  DINT         <= TDC_CLK;--tdc_data_valid_i;
-  DWAIT <= addon_clk;
+  DWAIT <= lvl2_busy_i;
   -- DGOOD        <= lvl2_busy_i;
 
   LVL1_TAG_COUNT : up_down_counter
@@ -2311,6 +2717,8 @@ begin
 -- MULTIPLEX_DATA_TO_ETRAX
 -----------------------------------------------------------------------------
 
+
+  
   MULTIPLEX_DATA_TO_ETRAX : process(CLK, reset_i, external_mode_i)
   begin
     if rising_edge(CLK) then
@@ -2320,10 +2728,12 @@ begin
         external_data_in_i <= dsp_data_out_i;
       elsif external_mode_i(7 downto 0) = x"02" then
         external_data_in_i <= sdram_data_out_i;
+      elsif external_mode_i(7 downto 0) = x"05" then
+         external_data_in_i <= trigger_rw_data_out_i;
       elsif external_mode_i(7 downto 0) = x"06" then
          external_data_in_i <= x"0000" & sfp_data_out;
       else
-        external_data_in_i <= x"0000"&external_mode_i;
+        external_data_in_i <= x"babe" & external_mode_i;
       end if;
     end if;
   end process MULTIPLEX_DATA_TO_ETRAX;
@@ -2331,13 +2741,14 @@ begin
   --\@@##$$%%^^&&**(((  put dsp_strobe to the dsp interface (extarnal mode has
   -- to be there)
 --       sdram_strobe_i <= '1' when external_mode_i(7 downto 0) = x"02" and external_ack_i = '1' else '0';  
-       external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or sfp_external_valid;
+--       external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or sfp_external_valid;
+  external_valid_i <= dsp_external_valid_i or sdram_external_valid_i or trigger_rw_valid_out_i or sfp_external_valid ;
 -------------------------------------------------------------------------------
 -- sfp interface
 -------------------------------------------------------------------------------
   Sfp_Interface_1: Sfp_Interface
     generic map (
-      I2C_SPEED => X"0200")
+      I2C_SPEED => X"0050")             --for 100MHz CLK it is ~ 312.5kz 
     port map (
       CLK_IN         => CLK,
       RST_IN         => reset_i,
@@ -2350,7 +2761,7 @@ begin
       READ_DONE      => sfp_external_valid,           --external_valid_i
       DEBUG          => r_register_i(21),
       SFP_ADDRESS    => external_address_i);
-  
+  r_register_i(20)(15 downto 0) <= sfp_data_out;
 --  Sfp_Interface_1 : Sfp_Interface
 --    generic map (
 --      device_add        => "1010001",
@@ -2522,42 +2933,69 @@ begin
         VALID_DATA_SENT    => dsp_external_valid_i,
         ACKNOWLEDGE        => dsp_strobe_i,
         DEBUGSTATE_MACHINE => dsp_register_00_i);
+    
   end generate DSP_EN;
+  
+  DSP_DISABLE: if DSP_INT_ENABLE = 0 generate
+    dsp_external_valid_i <= '0';
+    DSPDAT              <= (others => 'Z');
+    DSP_WRH                       <= 'Z';
+    DSP_WRL                       <= 'Z';   --in for virtex to read dsp(it's out =0 if I
+                                --write into dsp)
+--OUT
+    DSP_HBR                   <= '1';
+    DSPADDR                   <= (others => 'Z');
+    DSP_RD                    <= 'Z';
+    DSP_BRST                  <= 'Z';
+  end generate DSP_DISABLE;
 
 
 -------------------------------------------------------------------------------
 -- sdram interface
 -------------------------------------------------------------------------------
 
-  SDRAM_EN : if SDRAM_INT_ENABLE = 1 generate
-    SDRAM_INTERFACE_LOGIC : sdram_interface
-      port map (
-        CLK_SDRAM          => VSD_CLOCK,
-        CKE                => VSD_CKE,
-        CS                 => vsd_cs_i,
-        RAS                => VSD_RAS,
-        CAS                => VSD_CAS,
-        WE                 => VSD_WE,
-        DQM                => VSD_DQML,
-        BA                 => VSD_BA,
-        A                  => VSD_A,
-        DQ                 => VSD_D,
-        CLK                => CLK,
-        RESET              => reset_i,
-        TRIGGER            => external_ack_i,
-        INTERNAL_DATA_IN   => external_data_out_i,
-        INTERNAL_DATA_OUT  => sdram_data_out_i,
-        INTERNAL_ADDRESS   => external_address_i,
-        INTERNAL_MODE      => external_mode_i,
-        VALID_DATA_SENT    => sdram_external_valid_i,
-        DEBUGSTATE_MACHINE => sdram_register_00_i);
-
-    VSD_CSEH <= vsd_cs_i;
-    VSD_CSEL <= vsd_cs_i;
---     ADO_TTL(18) <= '1';
---     ADO_TTL(15 downto 0) <= (others => 'Z');
-  end generate SDRAM_EN;
-
+--  SDRAM_EN : if SDRAM_INT_ENABLE = 1 generate
+--    SDRAM_INTERFACE_LOGIC : sdram_interface
+--      port map (
+--        CLK_SDRAM          => VSD_CLOCK,
+--        CKE                => VSD_CKE,
+--        CS                 => vsd_cs_i,
+--        RAS                => VSD_RAS,
+--        CAS                => VSD_CAS,
+--        WE                 => VSD_WE,
+--        DQM                => VSD_DQML,
+--        BA                 => VSD_BA,
+--        A                  => VSD_A,
+--        DQ                 => VSD_D,
+--        CLK                => CLK,
+--        RESET              => reset_i,
+--        TRIGGER            => external_ack_i,
+--        INTERNAL_DATA_IN   => external_data_out_i,
+--        INTERNAL_DATA_OUT  => sdram_data_out_i,
+--        INTERNAL_ADDRESS   => external_address_i,
+--        INTERNAL_MODE      => external_mode_i,
+--        VALID_DATA_SENT    => sdram_external_valid_i,
+--        DEBUGSTATE_MACHINE => sdram_register_00_i);
+
+--    VSD_CSEH <= vsd_cs_i;
+--    VSD_CSEL <= vsd_cs_i;
+----     ADO_TTL(18) <= '1';
+----     ADO_TTL(15 downto 0) <= (others => 'Z');
+--  end generate SDRAM_EN;
+
+--  SDRAM_DISABLE: if SDRAM_INT_ENABLE = 0 generate
+--    sdram_external_valid_i <= '0';
+--    VSD_CLOCK <= '0';
+--    VSD_CSEL <= '1';
+--    VSD_CSEH <= '1';
+--    VSD_RAS <= '1';
+--    VSD_CAS <= '1';
+--    VSD_WE  <= '1';
+--    VSD_DQML <= x"0";
+--    VSD_A(12 downto 0) <= (others => '0');
+--    VSD_D <= (others => 'Z');
+--    VSD_BA <= "00";
+--  end generate SDRAM_DISABLE;
 
 -------------------------------------------------------------------------------
 -- opt dtu
@@ -2572,47 +3010,62 @@ begin
     TLK_ENABLE  <= '1';
     TLK_PRBSEN  <= '0';
 
-    TLK_RX_CLK_BUFR : BUFR
-      port map(
-        CE  => '1',
-        CLR => '0',
-        I   => TLK_RX_CLK,
-        O   => tlk_rx_clk_r(0)
-        );
-
-    TLK_CLK_BUFR : BUFR
-      port map(
-        CE  => '1',
-        CLR => '0',
-        I   => TLK_CLK,
-        O   => tlk_clk_r(0)
-        );
+--    TLK_RX_CLK_BUFR : BUFR
+--      port map(
+--        CE  => '1',
+--        CLR => '0',
+--        I   => TLK_RX_CLK,
+--        O   => tlk_rx_clk_r(0)
+--        );
+--    tlk_rx_clk_r(0) <= TLK_RX_CLK;
+
+--    TLK_CLK_BUFR : BUFR
+--      port map(
+--        CE  => '1',
+--        CLR => '0',
+--        I   => TLK_CLK,
+--        O   => tlk_clk_r(0)
+--        );
 
     DTU_EN : if TRBV2_TYPE < 4 generate
       DTU_OPT_INST : optical_dtu
         port map (
           CLK                       => CLK,
-          RX_CLK                    => tlk_rx_clk_r(0),
-          TX_CLK                    => tlk_clk_r(0),
+          RX_CLK                    => CLK,--tlk_rx_clk_r(0),
+          TX_CLK                    => CLK,--tlk_clk_r(0),
           RESET                     => reset_i,
-          OPT_DATA_IN               => TLK_RXD,
-          OPT_DATA_OUT              => TLK_TXD,
-          OPT_DATA_VALID_IN         => TLK_RX_DV,
-          OPT_DATA_ERR              => TLK_RX_ER,
-          OPT_DATA_SEND             => TLK_TX_EN,
+          OPT_DATA_IN               => med_data_out_i,--TLK_RXD,
+          OPT_DATA_OUT              => med_data_in_i,--TLK_TXD,
+          OPT_DATA_VALID_IN         => med_dataready_out_i(0),--TLK_RX_DV,
+          OPT_DATA_ERR              => '0',--TLK_RX_ER,
+          OPT_DATA_SEND             => med_dataready_in_i(0),--TLK_TX_EN,
           LVL1_TRIGGER              => lvl1_trigger_i,
           LVL1_TRIGGER_CODE         => lvl1_trigger_code_i,
           LVL1_TRIGGER_TAG          => lvl1_trigger_tag_i(7 downto 0),
           LVL2_TRIGGER              => lvl2_trigger_i,
           LVL2_TRIGGER_CODE         => lvl2_trigger_code_i(3),
           LVL2_TRIGGER_TAG          => lvl2_trigger_tag_i(7 downto 0),
-          LVL1_BUSY                 => busy_or_error,
+          LVL1_BUSY                 => lvl1_busy_i,--busy_or_error,
           LVL2_BUSY                 => lvl2_busy_i,
           OPT_DTU_DEBUG_REGISTER_00 => fpga_register_0d_i,
           OPT_DTU_DEBUG_REGISTER_01 => fpga_register_0b_i
           );
---    busy_or_error <= trigger_miss_match or lvl1_busy_i;
-      busy_or_error       <= lvl1_busy_i;
+      med_read_in_i(0) <= '1';
+      SEND_PACKET_NUM : process (CLK, reset_i)
+      begin
+        if rising_edge(CLK) then
+          if reset_i = '1' then
+            med_packet_num_in_i <= "001";
+          elsif med_dataready_out_i(0)='1' then
+            med_packet_num_in_i <= med_packet_num_in_i+1;
+          else
+            med_packet_num_in_i <= med_packet_num_in_i;
+          end if;
+        end if;
+      end process SEND_PACKET_NUM;
+      ado_lv_out_i <= (others => '0');
+    busy_or_error <= trigger_miss_match or lvl1_busy_i;
+--      busy_or_error       <= lvl1_busy_i;
       ADO_TTL(0)          <= TLK_RX_ER;
       ADO_TTL(1)          <= TLK_RX_DV;
       ADO_TTL(5 downto 2) <= TLK_RXD(15 downto 12);
@@ -2623,6 +3076,7 @@ begin
       ADO_TTL(10)         <= FS_PB_17;
       ADO_TTL(11)         <= tdc_data_valid_i;
       ADO_TTL(12)         <= lvl2_trigger_code_i(3);
+--      ADO_TTL(15 downto 0) <= (others => '0');
 
     end generate DTU_EN;
 
@@ -2670,6 +3124,7 @@ begin
     BUSY_SELECT : if TRBV2_TYPE = 4 generate
       not_lvl1_busy_opt <= opt_lvl1_busy_i or vulom_busy;
     end generate BUSY_SELECT;
+    
     SUB_SYSTEM_SELECT : if TRBV2_TYPE = 5 generate
       
       not_lvl1_busy_opt <= not opt_lvl1_busy_i;
@@ -2762,6 +3217,7 @@ begin
 -----------------------------------------------------------------------------
 
   TLK_ISE : if DTU_ENABLE = 0 and TRBV2_TYPE < 4 and TRBNET_ENABLE = 0 generate
+    
     TLK_TX_ER       <= '0';
     SFP_TX_DIS      <= '0';             --fpga_register_06_i(15);
     TLK_LOOPEN      <= '0';
diff --git a/trb_v2b_fpga_syn.prj b/trb_v2b_fpga_syn.prj
index 919adb1..1d5d261 100644
--- a/trb_v2b_fpga_syn.prj
+++ b/trb_v2b_fpga_syn.prj
@@ -13,7 +13,11 @@ add_file -vhdl -lib work "sfp_interface.vhd"
 
 add_file -vhdl -lib work "cts.vhd"
 add_file -vhdl -lib work "cts_fifo.vhd"
-
+add_file -vhdl -lib work "sdram_fpga_interface.vhd"
+add_file -vhdl -lib work "sdram_controller.vhd"
+add_file -vhdl -lib work "sdramcntl.vhd"
+add_file -vhdl -lib work "common.vhd"
+add_file -vhdl -lib work "small512Words.vhd"
 add_file -vhdl -lib work "version.vhd"
 add_file -vhdl -lib work "up_down_counter.vhd"
 add_file -vhdl -lib work "etrax_interface.vhd"
@@ -36,10 +40,13 @@ add_file -vhdl -lib work "trbv2_link_fifo.vhd"
 add_file -vhdl -lib work "DCM_100MHz_to_200MHz.vhd"
 add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
 add_file -vhdl -lib work "../trbnet/optical_link/media_interface.vhd"
-add_file -vhdl -lib work "../trbnet/optical_link/flexi_PCS_synch.vhd"
-add_file -vhdl -lib work "../trbnet/optical_link/flexi_PCS_channel_synch.vhd"
 add_file -vhdl -lib work "header_add_data_fifo_4kW.vhd"
 add_file -vhdl -lib work "lvl1_buffer_32kW.vhd"
+add_file -vhdl -lib work "trigger_interface.vhd"
+add_file -vhdl -lib work "small_1kW.vhd"
+add_file -vhdl -lib work "data_address_to_sdram_fifo.vhd"
+add_file -vhdl -lib work "fifo_from_sdram.vhd"
+
 #######cts first level components #1 second level #2-- ....###########
 #0
 
diff --git a/trb_v2b_fpga_tb.vhd b/trb_v2b_fpga_tb.vhd
index 233984d..394b411 100644
--- a/trb_v2b_fpga_tb.vhd
+++ b/trb_v2b_fpga_tb.vhd
@@ -11,7 +11,8 @@ END trb_v2b_fpga_tb;
 --simulate at lest for 100 us
 ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   
-  component trb_v2b_fpga
+--component trb_v2b_fpga
+    component trb_v2b_fpga_simple_cts --tof
     port (
       VIRT_CLK        : in    std_logic;
       VIRT_CLKB       : in    std_logic;
@@ -164,6 +165,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       SFP_LOS         : in    std_logic;
       SFP_TX_DIS      : out   std_logic;
       SFP_TX_FAULT    : in    std_logic;
+      SCL             : inout std_logic;
+      SDA             : inout std_logic;
       ADO_LVDS_IN          : in    std_logic_vector(51 downto 0);
       ADO_LVDS_OUT                    : out std_logic_vector(9 downto 0);
       ADDON_TO_TRB_CLKINN       : in std_logic;
@@ -176,7 +179,9 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       VIRT_TMS        : out   std_logic;
       VIRT_TRST       : out   std_logic);
   end component;
-    component trb_v2b_fpga_endpoint
+  
+-- component trb_v2b_fpga_endpoint
+    component trb_v2b_fpga_simple_endpoint --tof
     port (
       VIRT_CLK        : in    std_logic;
       VIRT_CLKB       : in    std_logic;
@@ -333,6 +338,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
       ADO_LVDS_OUT                    : out std_logic_vector(9 downto 0);
       ADDON_TO_TRB_CLKINN       : in std_logic;
      ADDON_TO_TRB_CLKINP       : in std_logic;
+     SCL              : inout std_logic;
+     SDA              : inout std_logic;
       ADO_TTL         : inout std_logic_vector(46 downto 0);
 --      ADO_TTL         : inout std_logic_vector(15 downto 0);
       VIRT_TCK        : out   std_logic;
@@ -516,6 +523,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal CTS_VIRT_TRST       : std_logic;
   signal CTS_ADDON_TO_TRB_CLKINN       :  std_logic;
   signal CTS_ADDON_TO_TRB_CLKINP       :  std_logic;
+  signal CTS_SDA : std_logic;
+  signal CTS_SCL : std_logic;
 -------------------------------------------------------------------------------
 -- trb signals
 -------------------------------------------------------------------------------
@@ -681,7 +690,8 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal VIRT_TRST       : std_logic;
   signal ADDON_TO_TRB_CLKINN       :  std_logic;
   signal ADDON_TO_TRB_CLKINP       :  std_logic;
-
+  signal SCL : std_logic;
+  signal SDA : std_logic;
   
   signal test_synch_00 : std_logic;
   signal dtu_clk : std_logic;
@@ -707,8 +717,11 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS
   signal end_data : std_logic_vector(31 downto 0);
   signal etrax_busy_counter : std_logic_vector(15 downto 0);
   signal etrax_busy : std_logic;
+  signal sfp_counter : std_logic_vector(7 downto 0):=x"00";
 BEGIN
-  trb_cts: trb_v2b_fpga
+
+    trb_cts: trb_v2b_fpga_simple_cts --tof
+  --trb_cts: trb_v2b_fpga
     port map (
         VIRT_CLK        => VIRT_CLK,
         VIRT_CLKB       => VIRT_CLKB,
@@ -861,7 +874,9 @@ BEGIN
         SFP_LOS         => CTS_SFP_LOS,
         SFP_TX_DIS      => CTS_SFP_TX_DIS,
         SFP_TX_FAULT    => CTS_SFP_TX_FAULT,
-        ADO_LVDS_OUT          => CTS_ADO_LVDS_OUT,
+        SDA             => CTS_SDA,
+        SCL             => CTS_SCL,
+        ADO_LVDS_OUT      => CTS_ADO_LVDS_OUT,
         ADO_LVDS_IN       => CTS_ADO_LVDS_IN,
         ADO_TTL         => CTS_ADO_TTL,
         ADDON_TO_TRB_CLKINN => CTS_ADDON_TO_TRB_CLKINN,
@@ -872,7 +887,8 @@ BEGIN
         VIRT_TMS        => CTS_VIRT_TMS,
         VIRT_TRST       => CTS_VIRT_TRST);
   
-  trb_end: trb_v2b_fpga_endpoint
+  trb_end: trb_v2b_fpga_simple_endpoint
+--  trb_end: trb_v2b_fpga_endpoint
     port map (
         VIRT_CLK        => VIRT_CLK,
         VIRT_CLKB       => VIRT_CLKB,
@@ -1025,6 +1041,8 @@ BEGIN
         SFP_LOS         => SFP_LOS,
         SFP_TX_DIS      => SFP_TX_DIS,
         SFP_TX_FAULT    => SFP_TX_FAULT,
+        SDA             => SDA,
+        SCL             => SCL,
         ADO_LVDS_OUT          => ADO_LVDS_OUT,
         ADO_LVDS_IN       => ADO_LVDS_IN,
         ADO_TTL         => ADO_TTL,
@@ -1316,11 +1334,54 @@ BEGIN
     wait for 100 ns;
     CTS_FS_PC(17) <= '0';
 
+     ---------------------------------------------------------------------------
+    -- writing register - test vulom registers
+    ---------------------------------------------------------------------------
+    rw_mode <= x"0005";
+    address <= x"000000c1";
+    data <= x"5555aaaa";
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 1000 ns;
+    for rw_mode_counter in 0 to 15 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= rw_mode(rw_mode_counter);
+    end loop;
+    wait for 300 ns;
+    for address_counter in 0 to 31 loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= address(address_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= address(address_counter);
+    end loop;
+    wait for 300 ns;
+    for data_counter in 0 to 31  loop
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '0';
+      CTS_FS_PC(16) <= data(data_counter);
+      wait for 100 ns;
+      CTS_FS_PC(17) <= '1';
+      CTS_FS_PC(16) <= data(data_counter);
+    end loop;
+    wait for 300 ns;
+    CTS_FS_PC(17) <= '0';
+    CTS_FS_PC(16) <= '0';
+    wait for 400 ns;
+    CTS_FS_PC(17) <= '1';
+    wait for 100 ns;
+    CTS_FS_PC(17) <= '0';
+    
     ---------------------------------------------------------------------------
     -- reading register
     ---------------------------------------------------------------------------
-    rw_mode <= x"8000";
-    address <= x"000000c0";
+    rw_mode <= x"8005";
+    address <= x"000000c1";
     data <= x"f000f00f";
     CTS_FS_PC(17) <= '0';
     CTS_FS_PC(16) <= '0';
@@ -1358,6 +1419,8 @@ BEGIN
     wait for 100 ns;
     CTS_FS_PC(17) <= '0';
 
+  
+
     
     wait for 300 ns;
     for data_to_etrax_counter in 0 to 31  loop
@@ -1371,9 +1434,22 @@ BEGIN
 
     
   end process etrax_int_test;
-
-        
-
+  
+--  SFP_INT: process
+--  begin 
+   CTS_SDA <= '0';
+--   for clock_counter in 0 to 8 loop
+--     wait on VIRT_CLK;
+--   end loop;
+--   SDA <= '0';
+--   wait on VIRT_CLK;;
+   
+--   for clock_counter in 0 to 8 loop
+--     wait on VIRT_CLK;
+--   end loop;
+ 
+--  end process SFP_INT;
+  
         clock_gclk : process
         begin
         VIRT_CLK <= '0';
@@ -1486,8 +1562,8 @@ BEGIN
         -----------------------------------------------------------------------
         -- TDC and etrax readout
         -----------------------------------------------------------------------
-        TDC_OUT <= tdc_data_i;--x"00000000";--tdc_data_i;
-
+        TDC_OUT <= tdc_data_i;
+                   
         TDC_DATA_CHANGE: process(REF_TDC_CLK, RESET_VIRT)
         begin
           if rising_edge(REF_TDC_CLK) then
@@ -1511,134 +1587,163 @@ BEGIN
           wait for 12.5 ns;
           end loop;
         end process;
+        
         trigger_lvl1 : process
           variable valid_time : integer :=0;
         begin
---          ADO_TTL(7) <= '0';
           A_DATA_READY <= '0';
           B_DATA_READY <= '0';
           C_DATA_READY <= '0';
           D_DATA_READY <= '0';
           TOKEN_IN  <= '0';
- --           A_TEMP <= '0';
---           wait for 50 ns;
---           A_TEMP <= '1';
---           wait for 10 ns;
---           A_TEMP <= '0';
---           wait for 10 ns;
           wait on REF_TDC_CLK until TOKEN_OUT = '1';
           wait on REF_TDC_CLK until TOKEN_OUT = '0';
           wait for 10 ns;
---          ADO_TTL(7) <= '0';
           A_DATA_READY <= '1';
---          wait for 50 ns;
-          wait for ((valid_time mod 2)*50*3+2*25)*ns;
+          wait for ((valid_time mod 2)*50*4+2*25)*ns;
           A_DATA_READY <= '0';
           B_DATA_READY <= '1';
---          wait for 50 ns;
           wait for ((valid_time mod 3 )*50*2+2*25)*ns;
           B_DATA_READY <= '0';
           C_DATA_READY <= '1';
---          wait for 50 ns;
-          wait for ((valid_time mod 5 )*50+2*25)*ns;
---          ADO_TTL(7) <= '0';
+          wait for ((valid_time mod 4 )*50+2*25)*ns;
           C_DATA_READY <= '0';
           D_DATA_READY <= '1';
-          --wait for 50 ns;
           wait for ((valid_time mod 7 )*50+2*25)*ns;
           D_DATA_READY <= '0';
           wait for 0 ns;
---          ADO_TTL(6) <= '1';
           TOKEN_IN <= '1';
           wait for 50 ns;
---          ADO_TTL(6) <= '0';
           TOKEN_IN <= '0';
-    --      wait on REF_TDC_CLK until DBAD = '0';
           valid_time := valid_time*3/2 +1; 
          end process;
 
-        ETRAX_HAS_NO_DMA_CTS: if ENABLE_DMA = 2 generate
+          ETRAX_HAS_NO_DMA: if ENABLE_DMA = 2 generate
           ETRAX_BUSY_PROC: process
             variable etrax_busy_time : integer :=0;
-          begin  -- process ETRAX_BUSY
-            CTS_FS_PB_17 <= '0';
-            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+          begin  
+            FS_PB_17 <= '0';
+            wait on VIRT_CLK until FS_PB(16) ='1';
             wait for 20 ns;
-            CTS_FS_PB_17 <= '1';
+            FS_PB_17 <= '1';
             wait for 80 ns;
             wait on VIRT_CLK until etrax_busy  ='0';
             etrax_busy_time := etrax_busy_time*3/2 +1;
           end process ETRAX_BUSY_PROC;
             
-        end generate ETRAX_HAS_NO_DMA_CTS;
+        end generate ETRAX_HAS_NO_DMA;
 
-        ETRAX_HAS_DMA_CTS: if ENABLE_DMA = 1 generate
+        ETRAX_HAS_DMA: if ENABLE_DMA = 1 generate
           ETRAX_BUSY_PROC: process
             variable etrax_busy_time : integer :=0;
-          begin  -- process ETRAX_BUSY
-            CTS_FS_PB_17 <= '0';
-            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+          begin  
+            FS_PB_17 <= '0';
+            wait on VIRT_CLK until FS_PB(16) ='1';
             wait for 20 ns;
-            CTS_FS_PB_17 <= '1';
+            FS_PB_17 <= '1';
             wait for 680 ns;
             etrax_busy_time := etrax_busy_time*3/2 +1;
           end process ETRAX_BUSY_PROC;
             
-        end generate ETRAX_HAS_DMA_CTS;
+        end generate ETRAX_HAS_DMA;
 
-         ETRAX_HAS_NO_DMA: if ENABLE_DMA = 2 generate
-          ETRAX_BUSY_PROC: process
-            variable etrax_busy_time : integer :=0;
-          begin  -- process ETRAX_BUSY
-            FS_PB_17 <= '0';
+          WAIT_FOR_TRANSFER_END: process
+            variable wait_int : integer range 0 to 65535;
+          begin
+            etrax_busy <= '0';
             wait on VIRT_CLK until FS_PB(16) ='1';
+            etrax_busy <= '1';
+            wait for 37*10 ns;
+          end process WAIT_FOR_TRANSFER_END;
+
+        -----------------------------------------------------------------------
+        -- TDC and etrax readout
+        -----------------------------------------------------------------------
+        CTS_TDC_OUT <= tdc_data_i;--x"00000000";--tdc_data_i;
+        cts_clock_tdcclk : process
+        begin
+          wait for 12 ns;
+          loop
+          CTS_REF_TDC_CLK  <= '0';
+          CTS_REF_TDC_CLKB <= '1';
+          wait for 12.5 ns;
+          CTS_REF_TDC_CLK  <= '1';
+          CTS_REF_TDC_CLKB <= '0';
+          wait for 12.5 ns;
+          end loop;
+        end process;
+        
+        cts_trigger_lvl1 : process
+          variable valid_time : integer :=0;
+        begin
+          CTS_A_DATA_READY <= '0';
+          CTS_B_DATA_READY <= '0';
+          CTS_C_DATA_READY <= '0';
+          CTS_D_DATA_READY <= '0';
+          CTS_TOKEN_IN  <= '0';
+          wait on CTS_REF_TDC_CLK until CTS_TOKEN_OUT = '1';
+          wait on CTS_REF_TDC_CLK until CTS_TOKEN_OUT = '0';
+          wait for 10 ns;
+          CTS_A_DATA_READY <= '1';
+          wait for ((valid_time mod 2)*50*3+2*25)*ns;
+          CTS_A_DATA_READY <= '0';
+          CTS_B_DATA_READY <= '1';
+          wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+          CTS_B_DATA_READY <= '0';
+          CTS_C_DATA_READY <= '1';
+          wait for ((valid_time mod 5 )*50+2*25)*ns;
+          CTS_C_DATA_READY <= '0';
+          CTS_D_DATA_READY <= '1';
+          wait for ((valid_time mod 7 )*50+2*25)*ns;
+          CTS_D_DATA_READY <= '0';
+          wait for 0 ns;
+          CTS_TOKEN_IN <= '1';
+          wait for 50 ns;
+          CTS_TOKEN_IN <= '0';
+          valid_time := valid_time*3/2 +1; 
+         end process;
+
+        CTS_ETRAX_HAS_NO_DMA_CTS: if ENABLE_DMA = 2 generate
+          CTS_ETRAX_BUSY_PROC: process
+            variable etrax_busy_time : integer :=0;
+          begin  
+            CTS_FS_PB_17 <= '0';
+            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
             wait for 20 ns;
-            FS_PB_17 <= '1';
+            CTS_FS_PB_17 <= '1';
             wait for 80 ns;
             wait on VIRT_CLK until etrax_busy  ='0';
             etrax_busy_time := etrax_busy_time*3/2 +1;
-          end process ETRAX_BUSY_PROC;
+          end process CTS_ETRAX_BUSY_PROC;
             
-        end generate ETRAX_HAS_NO_DMA;
+        end generate CTS_ETRAX_HAS_NO_DMA_CTS;
 
-        ETRAX_HAS_DMA: if ENABLE_DMA = 1 generate
-          ETRAX_BUSY_PROC: process
+        CTS_ETRAX_HAS_DMA_CTS: if ENABLE_DMA = 1 generate
+          CTS_ETRAX_BUSY_PROC: process
             variable etrax_busy_time : integer :=0;
-          begin  -- process ETRAX_BUSY
-            FS_PB_17 <= '0';
-            wait on VIRT_CLK until FS_PB(16) ='1';
+          begin  
+            CTS_FS_PB_17 <= '0';
+            wait on VIRT_CLK until CTS_FS_PB(16) ='1';
             wait for 20 ns;
-            FS_PB_17 <= '1';
+            CTS_FS_PB_17 <= '1';
             wait for 680 ns;
             etrax_busy_time := etrax_busy_time*3/2 +1;
-          end process ETRAX_BUSY_PROC;
+          end process CTS_ETRAX_BUSY_PROC;
             
-        end generate ETRAX_HAS_DMA;
+        end generate CTS_ETRAX_HAS_DMA_CTS;
+
+         
 
         
 
-          WAIT_FOR_TRANSFER_END: process
+          CTS_WAIT_FOR_TRANSFER_END: process
             variable wait_int : integer range 0 to 65535;
           begin
             etrax_busy <= '0';
             wait on VIRT_CLK until CTS_FS_PB(16) ='1';
             etrax_busy <= '1';
---            etrax_busy_counter <= CTS_FS_PC(15 downto 0);
---            wait for  to_integer(unsigned(etrax_busy_counter(15 downto 0)))*10 ns+ 40 ns;
             wait for 37*10 ns;
-          end process WAIT_FOR_TRANSFER_END;
---         trigger_lvl2 : process
---         begin
---           B_TEMP <= '0';
---           C_TEMP <= '0';
---           wait until DBAD = '1';
---           wait until DBAD = '0';
---           wait for 30 ns;
---           wait on VIRT_CLK until DGOOD = '0';
---           B_TEMP <= '0';
---           C_TEMP <= '1';
---           wait for 30 ns;
---         end process;
+          end process CTS_WAIT_FOR_TRANSFER_END;
 
         -----------------------------------------------------------------------
         -- DTU
diff --git a/trigger_logic.vhd b/trigger_logic.vhd
index eb0140b..48c5dfe 100755
--- a/trigger_logic.vhd
+++ b/trigger_logic.vhd
@@ -1,369 +1,520 @@
 library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-use IEEE.NUMERIC_STD.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 
---use work.support.all;
- library UNISIM;
- use UNISIM.VCOMPONENTS.all;
-
--- --  Uncomment the following lines to use the declarations that are
--- --  provided for instantiating Xilinx primitive components.
--- library UNISIM;
--- use UNISIM.VComponents.all;
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
 
 entity trigger_logic is
-
-  port (
-    CLK                  : in  std_logic;
-    TDC_CLK              : in  std_logic;
-    RESET                : in  std_logic;
-    LVL1_TRIGGER_CODE    : in  std_logic_vector(3 downto 0);
-    LVL1_TRIGGER_TAG     : in  std_logic_vector(7 downto 0);
-    TDC_CODE             : out std_logic_vector(3 downto 0);
-    TDC_TAG              : out std_logic_vector(7 downto 0);
-    LVL2_TRIGGER         : in  std_logic_vector(1 downto 0);  --0 trigger, 1 value
-    LVL2_TRIGGER_CODE    : in  std_logic_vector(3 downto 0);
-    LVL1_TRIGGER         : in  std_logic;
-    LVL1_TDC_TRIGG       : out std_logic;
-    LVL2_TDC_TRIGG       : out std_logic_vector(1 downto 0);
-    TRIGG_WITHOUT_HADES  : in  std_logic;
-    TDC_CONTROL_REGISTER : in  std_logic_vector(7 downto 0);
-    DELAY_TRIGGER        : in  std_logic_vector(7 downto 0);
-    LVL1_BUSY            : in  std_logic;
-    LVL2_BUSY            : in  std_logic;
-    TRB_ACK_LVL1         : out std_logic;
-    TRB_ACK_LVL2         : out std_logic;
-    TRIGGER_TO_TDC       : out std_logic;
-    TRIGGER_REGISTER_00  : out std_logic_vector(31 downto 0);
-    LVL2_BUSY_ALL        : in std_logic
+  generic (
+    TRIGGER_INPUTS_NUMBER : natural :=51
     );
+  port (
+        clk_50MHz                    : in    std_logic;
+        clk_300MHz                   : in    std_logic;
+        CLK                          : in    std_logic;
+        RESET                        : in    std_logic;
+        TRIGGER_IN                   : in    std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+        SIGNAL_IN                    : in    std_logic_vector(7 downto 0);
+        SIGNAL_OUT                   : out   std_logic_vector(15 downto 0);
+        INPUT_ENABLE                 : in    std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+        DOWNSCALE_REGISTER           : in    std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+        DELAY_TRIGGER_REGISTER       : in    std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+        WIDTH_REGISTER               : in    std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+        TS_GATING_DISABLE            : in    std_logic_vector((TRIGGER_INPUTS_NUMBER-1) downto 0);
+        MDC_TOF_GATING_DISABLE       : in    std_logic_vector((TRIGGER_INPUTS_NUMBER-1) downto 0);
+        DOWNSCALE_REGISTER_CLOCK     : in    std_logic_vector(3 downto 0);
+        TRIGGER_OUT_EN               : in    std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+        MULTIPLEXER_SELECT           : in    std_logic_vector(8*3-1 downto 0);
+        DELAY_TRIGGER_TO_SAVE        : in    std_logic_vector(2*8-1 downto 0);
+        LENGTH_TRIGGER_TO_SAVE       : in    std_logic_vector(2*8-1 downto 0);
+        LVL1_TIMING_OUT              : out   std_logic;
+        SCALER_OUT                   : out   std_logic_vector((TRIGGER_INPUTS_NUMBER*32-1) downto 0);
+        DTU_CODE_SELECT              : in    std_logic_vector(4 downto 0);
+   --trigger interface to CTS
+        LVL1_BUSY_IN                 : in std_logic;
+        LVL1_TRIGGER_TAG             : out std_logic_vector(15 downto 0);
+        LVL1_TRIGGER_CODE            : out std_logic_vector(3 downto 0);
+        LVL1_TRIGGER_OUT             : out std_logic;
+        TRIGGER_LOGIC_DEBUG          : out std_logic_vector(31 downto 0)
+      );
 end trigger_logic;
 
 architecture trigger_logic of trigger_logic is
-  component edge_to_pulse
+
+  component up_down_counter
+    generic (
+      NUMBER_OF_BITS : positive);
     port (
-      clock                           : in  std_logic;
-      en_clk                          : in  std_logic;
-      signal_in                       : in  std_logic;
-      pulse                           : out std_logic);
-    end component;
-    component up_counter_17bit
-      port (
-        QOUT : out std_logic_vector(16 downto 0);
-        UP   : in  std_logic;
-        CLK  : in  std_logic;
-        CLR  : in  std_logic);
-    end component;
-    
-  type DELAY_FSM_TRIGG is
-    (IDLE ,DELAY_1,DELAY_2,DELAY_3,DELAY_4,DELAY_5);
-  signal delay_fsm_currentstate, delay_fsm_nextstate: DELAY_FSM_TRIGG;
-  type LVL1_START_FSM is
-    (IDLE, SEND_LVL1_TRIGG_1, SEND_LVL1_TRIGG_2, SEND_LVL1_TRIGG_3, SEND_LVL1_TRIGG_4, WAIT_FOR_ACK);
-  signal LVL1_START_fsm_currentstate, LVL1_START_fsm_nextstate : LVL1_START_FSM;
-  type ACK_LVL1_STATE_MACHINE is
-    (IDLE, ACK_LVL1_PULSE_1, ACK_LVL1_CHECK_COMPLETION);
-  signal ACK_LVL1_STATE   : ACK_LVL1_STATE_MACHINE;
-  type LVL2_START_FSM is
-    (IDLE, SEND_LVL2_TRIGG_1, SEND_LVL2_TRIGG_2, WAIT_FOR_ACK);
-  signal LVL2_START_fsm_currentstate,LVL2_START_fsm_nextstate : LVL2_START_FSM;
-  type ACK_LVL2_STATE_MACHINE is
-    (IDLE, ACK_LVL2_PULSE_1, ACK_LVL2_CHECK_COMPLETION);
-  signal ACK_LVL2_STATE   : ACK_LVL2_STATE_MACHINE;
-  signal lvl1_trigger_pulse : std_logic;
-  signal lvl2_trigger_pulse : std_logic;
-  signal lvl1_tag_reg : std_logic_vector(7 downto 0);
-  signal lvl1_code_reg : std_logic_vector(3 downto 0);
-  signal delay_up : std_logic;
-  signal delay_clr : std_logic;
-  signal delay_qout : std_logic_vector(16 downto 0);
-  signal lvl1_trigger_pulse_start : std_logic;
-  signal lvl1_trigger_pulse_delay : std_logic;
-  signal lvl1_tdc_trigg_i : std_logic;
-  signal not_tdc_clk : std_logic;
-  signal trigger_register_00_i : std_logic_vector(31 downto 0);
+      CLK       : in  std_logic;
+      RESET     : in  std_logic;
+      COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+      UP_IN     : in  std_logic;
+      DOWN_IN   : in  std_logic);
+  end component;
+  
+  component multiplexer
+    port (
+      RESET              : in  std_logic;
+      CLK                : in  std_logic;
+      MULTIPLEXER_OUT    : out std_logic;
+      MULTIPLEXER_IN     : in  std_logic_vector(7 downto 0);
+      MULTIPLEXER_SELECT : in  std_logic_vector(2 downto 0)
+      );
+  end component;
+
+  component one_clock_long port (
+    clk       : in  std_logic;
+    en_clk    : in  std_logic;
+    signal_in : in  std_logic;
+    pulse     : out std_logic
+    );
+  end component;
+
+  component delay port (
+    clk           : in  std_logic;
+    to_be_delayed : in  std_logic;
+    delay_value   : in  std_logic_vector(3 downto 0);
+    delayed_pulse : out std_logic
+    );
+  end component;
+
+  component downscale port (
+    CLK              : in  std_logic;
+    disable          : in  std_logic;
+    to_be_downscaled : in  std_logic;
+    downscale_value  : in  std_logic_vector(3 downto 0);
+    downscaled       : out std_logic
+    );
+  end component;
+
+  component set_width port (
+    clk                  : in  std_logic;
+    to_be_set            : in  std_logic;
+    width_value          : in  std_logic_vector(3 downto 0);
+    width_adjusted_pulse : out std_logic);
+  end component;
+  component set_width_longer port (
+    clk                  : in  std_logic;
+    to_be_set            : in  std_logic;
+    width_value          : in  std_logic_vector(4 downto 0);
+    width_adjusted_pulse : out std_logic);
+  end component;
+
+  component set_width_special port (
+    clk                  : in  std_logic;
+    to_be_set            : in  std_logic;
+    width_value          : in  std_logic_vector(3 downto 0);
+    width_adjusted_pulse : out std_logic);
+  end component;
+  
+  component scaler port (
+    clk          : in  std_logic;
+    input_pulse  : in  std_logic;
+    scaler_reset : in  std_logic;
+    scaler_value : out std_logic_vector(19 downto 0));
+  end component;
+
+  component scaler_s port (
+    clk_300mhz   : in  std_logic;
+    clk_100mhz   : in  std_logic;
+    input_pulse  : in  std_logic;
+    scaler_reset : in  std_logic;
+    scaler_value : out std_logic_vector(31 downto 0));
+  end component;
+
+  component new_downscale_ck
+    port(
+      downscale_value : in  std_logic_vector(3 downto 0);
+      clk             : in  std_logic;
+      downscaled      : out std_logic;
+      output_disable  : in  std_logic;
+      global_inhibit  : in  std_logic;
+      scaler_reset    : out std_logic;
+      cal_inhibit     : out std_logic;
+      cal_trigger     : out std_logic
+      );
+  end component;
+
+  component beam_ramp
+    port(
+      clk_300mhz           : in  std_logic;
+      clk_50mhz            : in  std_logic;
+      input                : in  std_logic;
+      frequency_value      :     std_logic_vector(15 downto 0);
+      delay_value          : in  std_logic_vector(7 downto 0);
+      width_value_inhibit  : in  std_logic_vector(7 downto 0);
+      width_value_external : in  std_logic_vector(7 downto 0);
+      output_inhibit       : out std_logic;
+      output_external      : out std_logic;
+      beam_ramp_debug      : out std_logic_vector(31 downto 0)
+      );
+  end component;
+
+  component multiplicyty
+    port (
+      RESET      : in  std_logic;
+      CLK        : in  std_logic;
+      SIGNAL_IN  : in  std_logic_vector(5 downto 0);
+      SIGNAL_OUT : out std_logic_vector(7 downto 0)
+      );
+  end component;
+
+  component delay_pulse_module
+    port (
+      CLK        : in  std_logic;
+      SIGNAL_IN  : in  std_logic;
+      SIGNAL_OUT : out std_logic;
+      DELAY      : in  std_logic_vector(7 downto 0);
+      LENGTH     : in  std_logic_vector(7 downto 0));
+  end component;
+  
+  signal pti_one_clock_in,  pti_delayed_in, pti_sclaer_in, pti_ready_in,  pti_downscaled_in,  pti_set_width_in , pti_and_gts_in  : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+  signal pti_one_clock_out, pti_delayed_out,               pti_ready_out, pti_downscaled_out, pti_set_width_out, pti_and_gts_out : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+  signal start_veto_antycoincidence : std_logic;
+  signal cal_inhibit, cal_trigger, out_inhibit, out_inhibit_without_hv_ramp, beam_inhibit, bus_inhibit : std_logic;
+  signal global_timing_signal_out, or_out                                 : std_logic;
+  signal tof_multiplicity : std_logic_vector(7 downto 0);
+  signal tof_multiplicity_all : std_logic;
+  signal tof_mdc_trigger : std_logic;
+  signal eight_mulitplexers_in : std_logic_vector((8*8-1) downto 0);
+  signal saved_latches : std_logic_vector(50 downto 0);
+  signal triggers_to_delay : std_logic_vector(63 downto 0);  
+  signal data_to_send_delayed : std_logic_vector(63 downto 0);
+  signal data_to_send : std_logic_vector(16*32 downto 0);
+  signal reset_scalers : std_logic;
+  type   LVL1_TEST is (IDLE, LVL1_A, LVL1_B, LVL1_C);
+  signal LVL1_CURRENT, LVL1_NEXT : LVL1_TEST;
+  signal lvl1_trigger_tag_i : std_logic_vector(15 downto 0);
+  signal lvl1_trigger_code_i : std_logic_vector(3 downto 0);
+  signal lvl1_trigger_fsm : std_logic;
+  signal lvl1_busy_fsm : std_logic;   
+  signal data_valid_fsm : std_logic;  
+  signal data_out_fsm : std_logic_vector(31 downto 0);    
+  signal lvl1_busy_end_fsm : std_logic;
+  signal lvl1_trigger_debug_fsm : std_logic_vector(3 downto 0);
+  signal lvl1_trigger : std_logic;
+  signal lvl1_busy : std_logic;   
+  signal data_valid : std_logic;  
+  signal data_out : std_logic_vector(31 downto 0);    
+  signal lvl1_busy_end : std_logic;
+  signal lvl1_trigger_debug : std_logic_vector(3 downto 0);
 
   
 begin
-  TRIGGER_REGISTER_00 <= trigger_register_00_i;
-  -----------------------------------------------------------------------------
-  -- LVL1 trigger logic
-  -----------------------------------------------------------------------------
---   resetTDCBunchCounter <= '1';          --remember to reset after each LVL1
---   busy or just in the begginning ?!
---   resetTDCEventCounter <= '1';          --rememebr to reset at the beggining,
------------------------------------------------------------------------------
-  LVL1_START_PULSER : edge_to_pulse
-    port map (
-      clock     => CLK,
-      en_clk    => '1',
-      signal_in => LVL1_TRIGGER,
-      pulse     => lvl1_trigger_pulse);
-  -----------------------------------------------------------------------------
-  -- delay for trigger deliverd to TDC
-  -----------------------------------------------------------------------------
-  DELAY_COUNTER     : up_counter_17bit
+ -- TRIGGER_IN
+ -- 7:0 TS
+ -- 15:8 Veto
+ -- 21:16 TOF
+ -- 27:22 RPC
+ -- 33:28 MDC not used curently
+ -- 41:34 TOF Multiplicicty
+ -- 42 TOF & MDC - not used currently 
+ -- 50:43 Physical triggers
+ -- 
+  pti_one_clock_in(33 downto 0) <= TRIGGER_IN(33 downto 0);
+  pti_one_clock_in(41 downto 34) <= tof_multiplicity;
+  pti_one_clock_in(42) <= tof_mdc_trigger;
+  pti_one_clock_in(TRIGGER_INPUTS_NUMBER-1 downto 43) <= TRIGGER_IN( (TRIGGER_INPUTS_NUMBER-43)+34-1 downto 34);
+  
+  multiplicyty_1: multiplicyty
     port map (
-      CLK       => CLK,
-      UP        => delay_up,
-      CLR       => delay_clr,
-      QOUT      => delay_qout
+      RESET      => RESET,
+      CLK        => CLK,
+      SIGNAL_IN  => TRIGGER_IN(21 downto 16), --TOFin
+      SIGNAL_OUT => tof_multiplicity);
+
+--ONE CLOCK LONG 
+  GENERATE_ONE_CLOCK_LONG : for i in 0 to TRIGGER_INPUTS_NUMBER -1 generate
+    THE_ONE_CLOCK : ONE_CLOCK_LONG port map (
+      clk       => clk_300MHz,
+      en_clk    => INPUT_ENABLE(i),
+      signal_in => pti_one_clock_in(i),
+      pulse     => pti_one_clock_out(i));
+  end generate GENERATE_ONE_CLOCK_LONG;
+
+  pti_delayed_in <= pti_one_clock_out;
+--DELAYS
+  GENERATE_DELAY : for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+    THE_DELAY : DELAY port map (
+      clk           => clk_300MHz,
+      to_be_delayed => pti_delayed_in(i),
+      delay_value   => DELAY_TRIGGER_REGISTER((i+1)*4-1 downto i*4),
+      delayed_pulse => pti_delayed_out(i));
+  end generate;
+
+
+  pti_downscaled_in(0) <=  pti_delayed_out(7) or pti_delayed_out(6) or pti_delayed_out(5) or pti_delayed_out(4) or pti_delayed_out(3) or pti_delayed_out(2) or pti_delayed_out(1) or pti_delayed_out(0); --START
+  pti_downscaled_in(7 downto 1) <= (others => '0');
+  pti_downscaled_in(8) <=  pti_delayed_out(15) or pti_delayed_out(14) or pti_delayed_out(13) or pti_delayed_out(12) or pti_delayed_out(11) or pti_delayed_out(10) or pti_delayed_out(9) or pti_delayed_out(8);--VETO
+  pti_downscaled_in(15 downto 9) <= (others => '0');
+  pti_downscaled_in(16) <= pti_delayed_out(16) or pti_delayed_out(22); --TOF or RPC
+  pti_downscaled_in(17) <= pti_delayed_out(17) or pti_delayed_out(23); --TOF or RPC
+  pti_downscaled_in(18) <= pti_delayed_out(18) or pti_delayed_out(24); --TOF or RPC
+  pti_downscaled_in(19) <= pti_delayed_out(19) or pti_delayed_out(25); --TOF or RPC
+  pti_downscaled_in(20) <= pti_delayed_out(20) or pti_delayed_out(26); --TOF or RPC
+  pti_downscaled_in(21) <= pti_delayed_out(21) or pti_delayed_out(27); --TOF or RPC
+  pti_downscaled_in(27 downto 22) <= (others => '0');
+  pti_downscaled_in(33 downto 28) <= (others => '0');  --MDC not used currently
+  pti_downscaled_in(41 downto 34) <= tof_multiplicity;
+  pti_downscaled_in(42) <= '0';         --TOF MDC not used currently
+  pti_downscaled_in(TRIGGER_INPUTS_NUMBER-1 downto 43)  <= pti_delayed_out(TRIGGER_INPUTS_NUMBER-1 downto 43);
+
+    
+--SCALERS
+  GENERATE_SCALERS : for i in 0 to TRIGGER_INPUTS_NUMBER -1 generate
+    TEH_SCALER : SCALER_S port map (
+      clk_300MHz   => clk_300MHz,
+      clk_100MHz   => CLK,       --PTI1÷5 before inhibit
+      input_pulse  => pti_downscaled_in(i),
+      scaler_reset => reset_scalers,
+      scaler_value => SCALER_OUT(32*(i+1)-1 downto 32*i)
       );
-  DELAY_FSM_CLOCK   : process (CLK, RESET)
-  begin  -- process DELAY_FSM_CLOCK
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        delay_fsm_currentstate   <= IDLE;
-      else
-        delay_fsm_currentstate   <= delay_fsm_nextstate;
-      end if;
-    end if;
-  end process DELAY_FSM_CLOCK;
-  -- purpose: delay trigger whitch is sending to TDC 
-  TO_DELAY_TRIGG : process (CLK,lvl1_trigger_pulse,delay_qout,DELAY_TRIGGER)
-  begin  -- process TO_DELAY_TRIGG
-    case (delay_fsm_currentstate) is
-      when IDLE    =>
-        trigger_register_00_i(1 downto 0) <= "00";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        if lvl1_trigger_pulse = '1' then
-          delay_fsm_nextstate    <= DELAY_1;
-        else
-          delay_fsm_nextstate    <= IDLE;
+
+  end generate GENERATE_SCALERS;
+
+---DOWNSCALE
+  GENERATE_DOWNSCALERS : for i in 0 to TRIGGER_INPUTS_NUMBER -1 generate
+    THE_DOWNSCALER : DOWNSCALE port map (
+      clk              => clk_300MHz,
+      disable          => out_inhibit,
+      to_be_downscaled => pti_downscaled_in(i),
+      downscale_value  => DOWNSCALE_REGISTER((i+1)*4-1 downto i*4),
+      downscaled       => pti_downscaled_out(i));
+  end generate GENERATE_DOWNSCALERS;
+
+  pti_set_width_in(TRIGGER_INPUTS_NUMBER-1 downto 1) <= pti_downscaled_out (TRIGGER_INPUTS_NUMBER-1 downto 1);
+  
+--WIDTH
+  GENERATE_SET_WIDTH : for i in 0 to TRIGGER_INPUTS_NUMBER -1 generate
+    setw1 : SET_WIDTH port map (
+      clk                  => clk_300MHz,
+      to_be_set            => pti_set_width_in(i),
+      width_value          => WIDTH_REGISTER((i+1)*4-1 downto i*4),
+      width_adjusted_pulse => pti_set_width_out(i));
+  end generate GENERATE_SET_WIDTH;
+
+  start_veto_antycoincidence <= pti_downscaled_in(0)  and (not pti_set_width_out(8));                              
+
+--  Inst_new_downscale_ck : new_downscale_ck port map(
+--    downscale_value => DOWNSCALE_REGISTER_CLOCK(3 downto 0),
+--    clk             => clk_300MHz,
+--    output_disable  => CAL_TRIGGER_DISABLE,
+--    scaler_reset    => scaler_reset_internal,
+--    downscaled      => CLOCK_DOWNSCALED,
+--    global_inhibit  => out_inhibit_without_hv_ramp,
+--    cal_inhibit     => cal_inhibit,
+--    cal_trigger     => cal_trigger);
+
+--MDC and TOF
+   
+-------------- Final AND-OR logic function
+  pti_and_gts_in <= pti_set_width_out;
+  
+  GENERATE_OUT_TRIGGERS : for i in 0 to TRIGGER_INPUTS_NUMBER -1  generate
+    TS_V_SIGNALS: if i<2 generate
+      pti_and_gts_and_mdc_tof_out : process(clk_300MHz)
+      begin
+        if rising_edge(clk_300MHz) then
+          pti_and_gts_out(i) <= pti_and_gts_in(i)  and TRIGGER_OUT_EN(i);
         end if;
-      when DELAY_1 =>
-        trigger_register_00_i(1 downto 0)    <= "01";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '0';
-        delay_up                 <= '1';
-        if delay_qout = DELAY_TRIGGER(7 downto 0) then
-          delay_fsm_nextstate    <= DELAY_2;
-        else
-          delay_fsm_nextstate    <= DELAY_1;
+      end process pti_and_gts_and_mdc_tof_out;
+    end generate TS_V_SIGNALS;
+    REST_SIGNALS: if i>1 generate
+      pti_and_gts_and_mdc_tof_out : process(clk_300MHz)
+      begin
+        if rising_edge(clk_300MHz) then
+          pti_and_gts_out(i) <=((pti_and_gts_in(i) and TS_GATING_DISABLE(i) and TRIGGER_OUT_EN(i))) or
+                               ((pti_and_gts_in(i) and (not(TS_GATING_DISABLE(i))) and TRIGGER_OUT_EN(i) and start_veto_antycoincidence));
         end if;
-      when DELAY_2 =>
-        trigger_register_00_i(1 downto 0)    <= "10";
-        lvl1_trigger_pulse_delay <= '1';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        delay_fsm_nextstate      <= IDLE;
-      when others  =>
-        trigger_register_00_i(1 downto 0)    <= "11";
-        lvl1_trigger_pulse_delay <= '0';
-        delay_clr                <= '1';
-        delay_up                 <= '0';
-        delay_fsm_nextstate      <= IDLE;
-    end case;
-  end process TO_DELAY_TRIGG;
-  lvl1_trigger_pulse_start <= lvl1_trigger_pulse when DELAY_TRIGGER = x"00" else lvl1_trigger_pulse_delay;
-  SAVE_LVL1_TRIGG_VALUES : process (CLK, RESET,lvl1_trigger_pulse)
+      end process pti_and_gts_and_mdc_tof_out;
+    end generate REST_SIGNALS;
+  end generate GENERATE_OUT_TRIGGERS;
+      
+  TRIGGER_OUT_OR : process (clk_300MHz, reset)
   begin
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        lvl1_tag_reg       <= (others => '0');
-        lvl1_code_reg      <= (others => '0');
-      elsif lvl1_trigger_pulse = '1' then
-        lvl1_tag_reg       <= LVL1_TRIGGER_TAG;
-        lvl1_code_reg      <= LVL1_TRIGGER_CODE;
+    if rising_edge(clk_300MHz) then
+      if reset = '1' then
+        or_out <= '0';
+      elsif pti_and_gts_out > 0 then
+        or_out <= '1';
       else
-        lvl1_tag_reg       <= lvl1_tag_reg;
-        lvl1_code_reg      <= lvl1_code_reg;
+        or_out <= '0';
       end if;
     end if;
-  end process SAVE_LVL1_TRIGG_VALUES;
-  TDC_TAG <= lvl1_tag_reg;
-  TDC_CODE <= lvl1_code_reg;
-  LVL1_START         : process (CLK, RESET)
-  begin 
-    if rising_edge(CLK)  then 
-      if RESET = '1' then 
-        LVL1_START_fsm_currentstate <= IDLE;
-      else 
-        LVL1_START_fsm_currentstate <= LVL1_START_fsm_nextstate;
+  end process TRIGGER_OUT_OR;
+
+
+  global_timing_signal_out <=  (or_out and (not out_inhibit) and (not cal_inhibit));
+
+  out_inhibit                 <= '0';--SIGNAL_IN(0) or beam_inhibit;
+  out_inhibit_without_hv_ramp <= '0';-- SIGNAL_IN(0) ;
+ 
+  SET_WIDTH_OUT : set_width_special port map (
+    clk                  => CLK,
+    to_be_set            => global_timing_signal_out,
+    width_value          => x"6",       -- fixed to 20 ns
+    width_adjusted_pulse => SIGNAL_OUT(15)
+    );                   
+  
+--  INST_BEAM_RAMP : beam_ramp port map(
+--    clk_300MHz           => clk_300MHz,
+--    clk_50MHz            => clk_50MHz,
+--    input                => '0',        --lemin_s(1),
+--    output_inhibit       => beam_inhibit,
+--    output_external      => TIN(12),
+--    frequency_value      => FREQUENCY_REGISTER_BEAM,
+--    delay_value          => DELAY_REGISTER_BEAM,
+--    width_value_inhibit  => WIDTH_INHIBIT_REGISTER_BEAM,
+--    width_value_external => WIDTH_EXTERNAL_REGISTER_BEAM,
+--    beam_ramp_debug      => beam_ramp_debug);
+
+
+--  SCALER_dead <= SCALER_dead_count;
+
+
+-------------- TOF & MDC logic - not used
+
+--multiplexing
+  eight_mulitplexers_in(31 downto 0) <= pti_delayed_out(31 downto 0);
+  eight_mulitplexers_in(63 downto 32) <= (others => '0');
+
+  GENERATE_MULTIPLEXERS: for i in 0 to 7 generate
+    THE_MULTIPLEXER: multiplexer
+      port map (
+        RESET              => RESET,
+        CLK                => CLK,
+        MULTIPLEXER_OUT    => SIGNAL_OUT(i),
+        MULTIPLEXER_IN     => eight_mulitplexers_in(((i+1)*8-1)downto(i*8)),
+        MULTIPLEXER_SELECT => MULTIPLEXER_SELECT(((i+1)*3-1)downto(i*3))
+        );
+  end generate GENERATE_MULTIPLEXERS;
+
+--LVL1 TRIGGER and DATA TRANSPORT
+
+  LVL1_TRIGGER_TAG : up_down_counter
+    generic map (
+      NUMBER_OF_BITS => 16)
+    port map (
+      CLK       => CLK,
+      RESET     => RESET,
+      COUNT_OUT => lvl1_trigger_tag_i,
+      UP_IN     => global_timing_signal_out,
+      DOWN_IN   => '0');
+
+  --lvl1_trigger <= GTS_to_databus or cal_trigger;
+
+  DTU_CODE_CHANGE : process (CLK)
+  begin  -- process DTU_CODE_CHANGE
+    if rising_edge (CLK) then
+      if DTU_CODE_SELECT(4) = '0' then
+        lvl1_trigger_code_i <= x"1";
+      else
+        lvl1_trigger_code_i <= DTU_CODE_SELECT(3 downto 0);
       end if;
     end if;
-  end process LVL1_START;
-  LVL1_START_FSM_PROC : process (LVL1_START_fsm_currentstate, CLK,lvl1_trigger_pulse_start,ACK_LVL1_STATE,TRIGG_WITHOUT_HADES,TDC_CONTROL_REGISTER,LVL1_BUSY,LVL2_BUSY)
-  begin  
-    case (LVL1_START_fsm_currentstate) is
-      when IDLE         =>
-        trigger_register_00_i(4 downto 2)    <= "000";
-        lvl1_tdc_trigg_i         <= '0';
-        if (lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE /= x"d") or
-          (TRIGG_WITHOUT_HADES ='1' and TDC_CONTROL_REGISTER(0) = '1') then
-          LVL1_START_fsm_nextstate <= SEND_LVL1_TRIGG_1;
-        else
-          LVL1_START_fsm_nextstate <= IDLE;
-        end if;
-      when SEND_LVL1_TRIGG_1 =>         --4 clock of 100MHz - to generate token
-        trigger_register_00_i(4 downto 2)    <= "001";
-        lvl1_tdc_trigg_i         <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_2;
-      when SEND_LVL1_TRIGG_2 =>
-        trigger_register_00_i(4 downto 2)    <= "010";
-        lvl1_tdc_trigg_i         <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_3;
-      when SEND_LVL1_TRIGG_3 =>
-        trigger_register_00_i(4 downto 2)    <= "011";
-        lvl1_tdc_trigg_i         <= '1';
-        LVL1_START_fsm_nextstate   <= SEND_LVL1_TRIGG_4;
-      when SEND_LVL1_TRIGG_4 =>
-        trigger_register_00_i(4 downto 2)    <= "100";
-        lvl1_tdc_trigg_i         <= '0';
-        LVL1_START_fsm_nextstate   <= WAIT_FOR_ACK;
-      when WAIT_FOR_ACK      =>
-        trigger_register_00_i(4 downto 2)    <= "101";
-        lvl1_tdc_trigg_i         <= '0';
-        if ACK_LVL1_STATE = ACK_LVL1_pulse_1 then
-          LVL1_START_fsm_nextstate <= IDLE;
-        else
-          LVL1_START_fsm_nextstate <= WAIT_FOR_ACK;
-        end if;
-      when others            =>
-        trigger_register_00_i(4 downto 2)    <= "111";
-        LVL1_START_fsm_nextstate   <= IDLE;
-        lvl1_tdc_trigg_i         <= '0';
-    end case;
-  end process LVL1_START_FSM_PROC;
-  LVL1_TDC_TRIGG <= lvl1_tdc_trigg_i;
-  ACK_LVL1_NEXT_STATE_DECODE : process (CLK, RESET, ACK_LVL1_STATE,LVL1_BUSY,lvl1_trigger_pulse_start)
+  end process DTU_CODE_CHANGE;
+
+  
+  DELAY_DELAYED_SIGNALS_TO_SAVE: for i in 0 to 31 generate
+    delay_pulse_module_1: delay_pulse_module
+      port map (
+        CLK        => CLK,
+        SIGNAL_IN  => triggers_to_delay(i),
+        SIGNAL_OUT => data_to_send_delayed(i),
+        DELAY      => DELAY_TRIGGER_TO_SAVE(7 downto 0),
+        LENGTH     => LENGTH_TRIGGER_TO_SAVE(7 downto 0));
+  end generate DELAY_DELAYED_SIGNALS_TO_SAVE;
+
+  DELAY_DOWNSCALED_SIGNALS_TO_SAVE: for i in 32 to 63 generate
+    delay_pulse_module_1: delay_pulse_module
+      port map (
+        CLK        => CLK,
+        SIGNAL_IN  => triggers_to_delay(i),
+        SIGNAL_OUT => data_to_send_delayed(i),
+        DELAY      => DELAY_TRIGGER_TO_SAVE(15 downto 8),
+        LENGTH     => LENGTH_TRIGGER_TO_SAVE(15 downto 8));
+  end generate DELAY_DOWNSCALED_SIGNALS_TO_SAVE;
+
+  data_to_send(16*32-1 downto 64) <= (others => '1');
+                                     
+  SAVE_DATA_TO_SEND_TO_TRB : process (CLK, reset)
   begin
     if rising_edge(CLK) then
-      if RESET = '1' then
-        ACK_LVL1_STATE       <= IDLE;
+      if reset = '1' then
+        data_to_send(63 downto 0) <= (others => '0');
+      elsif global_timing_signal_out = '1' then
+        data_to_send(63 downto 0) <= data_to_send_delayed;
       else
-        case (ACK_LVL1_STATE) is
-          when IDLE                      =>
-            trigger_register_00_i(6 downto 5)    <= "00";
-            TRB_ACK_LVL1     <= '0';
-            if LVL1_BUSY = '1' then
-              ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION;
-            elsif lvl1_trigger_pulse_start = '1' and LVL1_TRIGGER_CODE = x"d" then
-              ACK_LVL1_STATE <= ACK_LVL1_PULSE_1;
-            else
-              ACK_LVL1_STATE <= IDLE;
-            end if;
-          when ACK_LVL1_CHECK_COMPLETION =>
-            trigger_register_00_i(6 downto 5)    <= "01";
-            TRB_ACK_LVL1     <= '0';
-            if LVL1_BUSY = '1'then
-              ACK_LVL1_STATE <= ACK_LVL1_CHECK_COMPLETION;
-            else
-              ACK_LVL1_STATE <= ACK_LVL1_PULSE_1;
-            end if;
-          when ACK_LVL1_PULSE_1          =>
-            trigger_register_00_i(6 downto 5)    <= "10";
-            TRB_ACK_LVL1     <= '1';
-            ACK_LVL1_STATE   <= IDLE;
-          when others                    =>
-            trigger_register_00_i(6 downto 5)    <= "11";
-            ACK_LVL1_STATE   <= IDLE;
-        end case;
+        data_to_send(63 downto 0) <= data_to_send(63 downto 0);
       end if;
     end if;
-  end process;
-  not_tdc_clk <= not TDC_CLK;
-  SEND_TDC_TRIGGER : edge_to_pulse
-    port map (
-      clock     => not_tdc_clk,
-      en_clk    => '1',
-      signal_in => lvl1_tdc_trigg_i,
-      pulse     => TRIGGER_TO_TDC);
-  -----------------------------------------------------------------------------
-  -- LVL2 trigger logic
-  -----------------------------------------------------------------------------
-  LVL2_START_PULSER : edge_to_pulse
-    port map (
-      clock     => CLK,
-      en_clk    => '1',
-      signal_in => LVL2_TRIGGER(0),
-      pulse     => lvl2_trigger_pulse);
-
-  LVL2_START : process (CLK, RESET)
+  end process SAVE_DATA_TO_SEND_TO_TRB;
+  
+  LVL1_CLOCK : process (CLK, RESET)
   begin
     if rising_edge(CLK) then
       if RESET = '1' then
-        LVL2_START_fsm_currentstate <= IDLE;
+        LVL1_CURRENT <= IDLE;
       else
-        LVL2_START_fsm_currentstate <= LVL2_START_fsm_nextstate;
+        LVL1_CURRENT <= LVL1_NEXT;
       end if;
     end if;
-  end process LVL2_START;
-  LVL2_START_FSM_PROC     : process (LVL2_START_fsm_currentstate,CLK,lvl2_trigger_pulse,ACK_LVL1_STATE,TDC_CONTROL_REGISTER(0),ACK_LVL2_STATE)
+  end process LVL1_CLOCK;
+
+  LVL1_PROC : process (CLK)
+    variable data_counter : integer:=0;
   begin
-    case (LVL2_START_fsm_currentstate) is
-      when IDLE              =>
-        trigger_register_00_i(9 downto 7)    <= "000";
-        LVL2_TDC_TRIGG          <= "00";
-        if (lvl2_trigger_pulse='1') or (ACK_LVL1_STATE = ACK_LVL1_PULSE_1 and TDC_CONTROL_REGISTER(0) = '1') then
-          LVL2_START_fsm_nextstate <= SEND_LVL2_TRIGG_1;
+    lvl1_trigger_fsm <= '0';
+    lvl1_busy_fsm     <= '1';
+    data_valid_fsm    <= '0';
+    data_out_fsm      <= (others => '0');
+    lvl1_busy_end_fsm <= '0';
+    lvl1_trigger_debug_fsm  <= x"0";
+    case (LVL1_CURRENT) is
+      when IDLE =>
+        data_counter :=0;
+        lvl1_trigger_debug <= x"1";
+        lvl1_busy_fsm    <= '0';
+        if global_timing_signal_out = '1' then
+          LVL1_NEXT <= LVL1_A;
         else
-          LVL2_START_fsm_nextstate <= IDLE;
+          LVL1_NEXT <= IDLE;
         end if;
-      when SEND_LVL2_TRIGG_1 =>
-        trigger_register_00_i(9 downto 7)    <= "001";
-        LVL2_TDC_TRIGG          <= "00";
-        if LVL2_BUSY_ALL = '0' then
-          LVL2_START_fsm_nextstate   <= SEND_LVL2_TRIGG_2;
+      when LVL1_A =>
+        lvl1_trigger_debug <= x"2";
+        data_valid_fsm   <= '1';
+        data_counter := data_counter + 1;
+        data_out_fsm <= data_to_send((data_counter+1)*32-1 downto data_counter*32);
+        if data_counter = 16 then
+          LVL1_NEXT <= LVL1_B;
         else
-          LVL2_START_fsm_nextstate   <= SEND_LVL2_TRIGG_1;
+          LVL1_NEXT <= LVL1_A;
         end if;
---        LVL2_TDC_TRIGG             <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0)))  & '1';
---        LVL2_START_fsm_nextstate   <= SEND_LVL2_TRIGG_2;
-      when SEND_LVL2_TRIGG_2 =>
-        trigger_register_00_i(9 downto 7)    <= "010";
-        LVL2_TDC_TRIGG          <= "00";
---        LVL2_TDC_TRIGG             <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0))) & '1';
-        LVL2_START_fsm_nextstate   <= WAIT_FOR_ACK;
-      when WAIT_FOR_ACK      =>
-        trigger_register_00_i(9 downto 7)    <= "011";
-        LVL2_TDC_TRIGG             <= (not(LVL2_TRIGGER_CODE(3)) or (TDC_CONTROL_REGISTER(0))) & '1';
-        if ACK_LVL2_STATE = ACK_LVL2_PULSE_1 then
-          LVL2_START_fsm_nextstate <= IDLE;
+      when LVL1_B =>
+        lvl1_trigger_debug  <= x"2";
+        lvl1_busy_end_fsm <= '1';
+        LVL1_NEXT         <= LVL1_C;
+      when LVL1_C =>
+        lvl1_trigger_debug <= x"3";
+        if LVL1_BUSY_IN = '0' then
+          LVL1_NEXT <= IDLE;
         else
-          LVL2_START_fsm_nextstate <= WAIT_FOR_ACK;
+          LVL1_NEXT <= LVL1_C;
         end if;
-      when others            =>
-        trigger_register_00_i(9 downto 7)    <= "111";
-        LVL2_START_fsm_nextstate   <= IDLE;
-        LVL2_TDC_TRIGG        <=  "00";
+      when others =>
+        lvl1_trigger_debug <= x"f";
+        LVL1_NEXT        <= IDLE;
     end case;
-  end process LVL2_START_FSM_PROC;
-  ACK_LVL2_NEXT_STATE_DECODE : process (CLK, RESET, LVL2_BUSY, ACK_LVL2_STATE,LVL2_START_fsm_currentstate)
-  begin
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        ACK_LVL2_STATE       <= IDLE;
-      else
-        case (ACK_LVL2_STATE) is
-          when IDLE                      =>
-            trigger_register_00_i(11 downto 10)    <= "00";
-        --03.27    if LVL2_BUSY = '1' and LVL2_START_fsm_currentstate ???? /= IDLE then
-            if LVL2_BUSY = '1'  then
-              ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
-            else
-              ACK_LVL2_STATE <= IDLE;
-            end if;
-          when ACK_LVL2_CHECK_COMPLETION =>
-            trigger_register_00_i(11 downto 10)    <= "01";
-            if LVL2_BUSY = '1' then
-              ACK_LVL2_STATE <= ACK_LVL2_CHECK_COMPLETION;
-            else
-              ACK_LVL2_STATE <= ACK_LVL2_PULSE_1;
-            end if;
-          when ACK_LVL2_PULSE_1          =>
-            trigger_register_00_i(11 downto 10)    <= "10";
-            ACK_LVL2_STATE   <= IDLE;
-          when others                    =>
-            trigger_register_00_i(11 downto 10)    <= "11";
-            ACK_LVL2_STATE   <= IDLE;
-        end case;
-      end if;
-    end if;
-  end process;
-  TRB_ACK_LVL2               <= '1' when ACK_LVL2_STATE = ACK_LVL2_PULSE_1 else '0';
+  end process LVL1_PROC;
+
+-------------------------------------------------------------------------------
+-- debug logic ...
+-------------------------------------------------------------------------------
+
+
+
+  
 end trigger_logic;
-- 
2.43.0