From 8d2ba62b8c17508f6aad5307658642e16e241ba1 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Wed, 21 Jan 2009 14:48:47 +0000
Subject: [PATCH] added rom18x128, Boris

---
 basics/ram_16x16_dp.vhd |  2 +-
 basics/rom_18x128.vhd   | 90 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+), 1 deletion(-)
 create mode 100644 basics/rom_18x128.vhd

diff --git a/basics/ram_16x16_dp.vhd b/basics/ram_16x16_dp.vhd
index 2bf97c4..8ab8971 100644
--- a/basics/ram_16x16_dp.vhd
+++ b/basics/ram_16x16_dp.vhd
@@ -50,6 +50,6 @@ begin
         dout1 <= ram(conv_integer(a1));
         dout2 <= ram(conv_integer(a2));
       end if;
-    end process;
+  end process;
 
 end architecture;
\ No newline at end of file
diff --git a/basics/rom_18x128.vhd b/basics/rom_18x128.vhd
new file mode 100644
index 0000000..aeb3fd8
--- /dev/null
+++ b/basics/rom_18x128.vhd
@@ -0,0 +1,90 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+
+library work;
+use work.trb_net_std.all;
+
+entity rom_18x128 is
+  generic(
+    DATA_MEM_SIZE : integer := 16*128;
+    DATA : std_logic_vector(16*128-1 downto 0) := 
+              x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000"
+            & x"0000_0000_0000_0000";
+
+    PARITY_BIT0 : std_logic_vector(127 downto 0) := x"00100000000000000000000000000000";     
+    PARITY_BIT1 : std_logic_vector(127 downto 0) := x"00100000000000000000000000000000"
+    );
+  port(
+    CLK      : in  std_logic;
+    ADDR_IN  : in  std_logic_vector(6 downto 0);
+    READ_IN  : in  std_logic;
+    DATA_OUT : out std_logic_vector(17 downto 0)
+    );
+end entity;
+
+architecture rom_18x128_arch of rom_18x128 is
+    type memory_cell is array(0 to 127) of std_logic_vector(17 downto 0);
+    signal memory : memory_cell;
+
+begin
+
+MAPPING: process(CLK)
+  variable place : integer;  -- place is between 0 and 127 pointing at the cell in memory
+  begin
+  for row in DATA_MEM_SIZE/64 downto 1 loop
+    for cell in 1 to 4 loop
+      place := (row*4)-cell;
+--			if ( cell = 4 ) then
+				memory( place ) <= PARITY_BIT1(place)
+												 & PARITY_BIT0(place)
+												 & DATA( ((place+1)*16)-1  downto  place*16 );
+--		  else
+--		  	memory( place ) <= "00" & INPUT( ((place+1)*16)-1  downto  place*16 );
+-- 			end if;                  
+	  end loop;
+	end loop;
+  end process;
+
+
+  process(CLK)
+    begin
+      if rising_edge(CLK) then
+        if (READ_IN='1') then
+          DATA_OUT <= memory(conv_integer(ADDR_IN));
+        end if;
+      end if;
+    end process;
+
+end architecture;
\ No newline at end of file
-- 
2.43.0