From 8dc3ec31750c5893397a1b9d59253454cd988a64 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 25 Jul 2014 18:16:28 +0200 Subject: [PATCH] few more debugging regs for ADC --- ADC/trb3_periph_adc.vhd | 2 +- base/code/adc_ad9219.vhd | 50 +++++++++++++++++------------------ base/code/adc_data_buffer.vhd | 11 ++++---- 3 files changed, 31 insertions(+), 32 deletions(-) diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index e9cd47f..ac8801d 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -206,7 +206,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal spi_sdi, spi_sdo, spi_sck : std_logic; signal clk_adcref_i : std_logic; - signal debug_adc : std_logic_vector(31 downto 0); + signal debug_adc : std_logic_vector(48*32-1 downto 0); signal adc_restart_i : std_logic; signal adc_data : std_logic_vector(479 downto 0); diff --git a/base/code/adc_ad9219.vhd b/base/code/adc_ad9219.vhd index 512f6c2..d4a77a2 100644 --- a/base/code/adc_ad9219.vhd +++ b/base/code/adc_ad9219.vhd @@ -25,7 +25,7 @@ entity adc_ad9219 is DATA_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*CHANNELS*RESOLUTION-1 downto 0); FCO_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*RESOLUTION-1 downto 0); DATA_VALID_OUT : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)-1 downto 0); - DEBUG : out std_logic_vector(31 downto 0) + DEBUG : out std_logic_vector((DEVICES_LEFT+DEVICES_RIGHT)*CHANNELS*32-1 downto 0) ); end entity; @@ -37,19 +37,19 @@ type s_t is array(0 to 11) of integer range 0 to 1; constant fpgaside : s_t := (0,0,0,0,0,0,1,0,1,1,1,1); type q_t is array(0 to 11) of std_logic_vector(19 downto 0); -signal q,qq,qqq : q_t; +signal q,qq,qqq,q_q : q_t; signal clk_adcfast_i : std_logic_vector(1 downto 0); --200MHz signal clk_data : std_logic_vector(1 downto 0); --100MHz signal clk_data_half : std_logic_vector(1 downto 0); signal restart_i : std_logic_vector(1 downto 0); -signal q0_q, q0 : std_logic_vector(19 downto 0); + type state_t is (S1,S2,S3,S4,S5); type states_t is array(0 to 11) of state_t; signal state : states_t; -signal state_q : state_t; +signal state_q : states_t; type value_it is array(0 to 4) of std_logic_vector(9 downto 0); type value_t is array(0 to 11) of value_it; @@ -92,8 +92,6 @@ begin restart_i(0) <= RESTART_IN when rising_edge(clk_data(0)); restart_i(1) <= RESTART_IN when rising_edge(clk_data(1)); - clk_data_half(0) <= not clk_data_half(0) when rising_edge(clk_data(0)); - clk_data_half(1) <= not clk_data_half(1) when rising_edge(clk_data(1)); THE_LEFT : entity work.dqsinput_7x5 port map( @@ -260,29 +258,29 @@ gen_chips_left : for i in 0 to DEVICES_LEFT+DEVICES_RIGHT-1 generate DATA_VALID_OUT(i) <= '0'; end if; end process; + + + proc_debug : process begin + wait until rising_edge(CLK); + DEBUG(i*32+31 downto i*32) <= (others => '0'); + DEBUG(i*32+3 downto i*32+0) <= q_q(i)(3 downto 0); + DEBUG(i*32+7 downto i*32+4) <= q_q(i)(19 downto 16); + case state_q(i) is + when S1 => DEBUG(i*32+11 downto i*32+8) <= x"1"; + when S2 => DEBUG(i*32+11 downto i*32+8) <= x"2"; + when S3 => DEBUG(i*32+11 downto i*32+8) <= x"3"; + when S4 => DEBUG(i*32+11 downto i*32+8) <= x"4"; + when S5 => DEBUG(i*32+11 downto i*32+8) <= x"5"; + when others => DEBUG(i*32+11 downto i*32+8) <= x"0"; + end case; + end process; end generate; -q0 <= q(0) when rising_edge(clk_data(0)); -q0_q <= q0 when rising_edge(CLK); - -proc_debug : process begin - wait until rising_edge(CLK); - state_q <= state(0); - DEBUG <= (others => '0'); - DEBUG(3 downto 0) <= q0_q(3 downto 0); - DEBUG(7 downto 4) <= q0_q(19 downto 16); - case state_q is - when S1 => DEBUG(11 downto 8) <= x"1"; - when S2 => DEBUG(11 downto 8) <= x"2"; - when S3 => DEBUG(11 downto 8) <= x"3"; - when S4 => DEBUG(11 downto 8) <= x"4"; - when S5 => DEBUG(11 downto 8) <= x"5"; - when others => DEBUG(11 downto 8) <= x"0"; - end case; - DEBUG(14 downto 12) <= lock; - DEBUG(17 downto 16) <= clk_data_half; -end process; +q_q <= qqq when rising_edge(CLK); +state_q <= state when rising_edge(CLK); + + diff --git a/base/code/adc_data_buffer.vhd b/base/code/adc_data_buffer.vhd index 1afacb4..c5a8b97 100644 --- a/base/code/adc_data_buffer.vhd +++ b/base/code/adc_data_buffer.vhd @@ -18,7 +18,7 @@ entity adc_data_buffer is ADC_DATA_IN : in std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0); ADC_FCO_IN : in std_logic_vector(DEVICES*RESOLUTION-1 downto 0); ADC_DATA_VALID : in std_logic_vector(DEVICES-1 downto 0); - ADC_STATUS_IN : in std_logic_vector(31 downto 0); + ADC_STATUS_IN : in std_logic_vector(DEVICES*CHANNELS*32-1 downto 0); ADC_CONTROL_OUT: out std_logic_vector(31 downto 0); ADC_RESET_OUT : out std_logic; @@ -57,7 +57,7 @@ gen_data_fifo : for i in 0 to DEVICES*CHANNELS-1 generate port map ( Data(9 downto 0) => ADC_DATA_IN(10*i+9 downto 10*i), -- Data(17 downto 10) => ADC_FCO_IN (10*(i/CHANNELS)+7 downto 10*(i/CHANNELS)), - Data(15 downto 12) => ADC_FCO_IN (10*(i/CHANNELS)+3 downto 10*(i/CHANNELS)), + Data(17 downto 12) => ADC_FCO_IN (10*(i/CHANNELS)+6 downto 10*(i/CHANNELS)+1), Clock => CLK, WrEn => fifo_write(i), RdEn => fifo_read(i), @@ -92,8 +92,9 @@ PROC_BUS : process begin if BUS_RX.addr(7 downto 0) = x"80" then BUS_TX.data <= ctrl_reg; BUS_TX.ack <= '1'; - elsif BUS_RX.addr(7 downto 0) = x"82" then - BUS_TX.data <= ADC_STATUS_IN(31 downto 0); + elsif BUS_RX.addr(7 downto 0) >= x"40" and BUS_RX.addr(7 downto 0) < x"80" + and BUS_RX.addr(5 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,6)) then + BUS_TX.data <= ADC_STATUS_IN(to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32+31 downto to_integer(unsigned(BUS_RX.addr(5 downto 0)))*32); BUS_TX.ack <= '1'; elsif BUS_RX.addr(7 downto 0) = x"83" then BUS_TX.data <= (others => '0'); @@ -125,7 +126,7 @@ PROC_BUS : process begin BUS_TX.ack <= '1'; BUS_TX.data(17 downto 0) <= fifo_dout(saved_addr); BUS_TX.data(30 downto 18) <= (others => '0'); - BUS_TX.data(31) <= fifo_empty(saved_addr / CHANNELS); + BUS_TX.data(31) <= fifo_empty(saved_addr); end if; end process; -- 2.43.0