From 8e29eb26686d5741b25aeaa1bac817022add02d2 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 29 Jul 2008 18:59:52 +0000 Subject: [PATCH] *** empty log message *** --- trb_net16_endpoint_1_trg_2_data_1_regio.vhd | 68 +++++++++++---------- 1 file changed, 35 insertions(+), 33 deletions(-) diff --git a/trb_net16_endpoint_1_trg_2_data_1_regio.vhd b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd index 9fcf0e2..8aadcaa 100644 --- a/trb_net16_endpoint_1_trg_2_data_1_regio.vhd +++ b/trb_net16_endpoint_1_trg_2_data_1_regio.vhd @@ -64,63 +64,63 @@ entity trb_net16_endpoint_1_trg_2_api_1_regio is LVL1_GOT_TRIGGER_OUT : out std_logic; LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0); LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0); - LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0); - LVL1_RELEASE_IN : in std_logic; + LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0) := x"00000000"; + LVL1_RELEASE_IN : in std_logic := '0'; -- IPU-Data Channel APL - IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - IPUD_APL_DATAREADY_IN : in std_logic; + IPUD_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; + IPUD_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; + IPUD_APL_DATAREADY_IN : in std_logic := '0'; IPUD_APL_READ_OUT : out std_logic; - IPUD_APL_SHORT_TRANSFER_IN: in std_logic; - IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0); - IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - IPUD_APL_SEND_IN : in std_logic; - IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); + IPUD_APL_SHORT_TRANSFER_IN: in std_logic := '0'; + IPUD_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; + IPUD_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; + IPUD_APL_SEND_IN : in std_logic:= '0'; + IPUD_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; IPUD_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); IPUD_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); IPUD_APL_TYP_OUT : out std_logic_vector (2 downto 0); IPUD_APL_DATAREADY_OUT : out std_logic; - IPUD_APL_READ_IN : in std_logic; + IPUD_APL_READ_IN : in std_logic:= '0'; IPUD_APL_RUN_OUT : out std_logic; IPUD_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); -- LVL2-Data Channel APL - LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); - LVL2_APL_DATAREADY_IN : in std_logic; + LVL2_APL_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0) := x"0000"; + LVL2_APL_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0) := "00"; + LVL2_APL_DATAREADY_IN : in std_logic := '0'; LVL2_APL_READ_OUT : out std_logic; - LVL2_APL_SHORT_TRANSFER_IN: in std_logic; - LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0); - LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0); - LVL2_APL_SEND_IN : in std_logic; - LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0); + LVL2_APL_SHORT_TRANSFER_IN: in std_logic := '0'; + LVL2_APL_DTYPE_IN : in std_logic_vector (3 downto 0) := x"0"; + LVL2_APL_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0) := x"00000000"; + LVL2_APL_SEND_IN : in std_logic:= '0'; + LVL2_APL_TARGET_ADDRESS_IN: in std_logic_vector (15 downto 0) := x"0000"; LVL2_APL_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); LVL2_APL_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); LVL2_APL_TYP_OUT : out std_logic_vector (2 downto 0); LVL2_APL_DATAREADY_OUT : out std_logic; - LVL2_APL_READ_IN : in std_logic; + LVL2_APL_READ_IN : in std_logic:= '0'; LVL2_APL_RUN_OUT : out std_logic; LVL2_APL_SEQNR_OUT : out std_logic_vector (7 downto 0); -- Slow Control Data Port - SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0); + SCTR_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); SCTR_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0); - SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0); + SCTR_REGISTERS_IN : in std_logic_vector(32*2**(SCTR_NUM_STAT_REGS)-1 downto 0) := (others => '0'); SCTR_REGISTERS_OUT : out std_logic_vector(32*2**(SCTR_NUM_CTRL_REGS)-1 downto 0); --following ports only used when using internal data port SCTR_ADDR_OUT : out std_logic_vector(16-1 downto 0); SCTR_READ_ENABLE_OUT : out std_logic; SCTR_WRITE_ENABLE_OUT : out std_logic; SCTR_DATA_OUT : out std_logic_vector(32-1 downto 0); - SCTR_DATA_IN : in std_logic_vector(32-1 downto 0); - SCTR_DATAREADY_IN : in std_logic; - SCTR_NO_MORE_DATA_IN : in std_logic; + SCTR_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + SCTR_DATAREADY_IN : in std_logic := '0'; + SCTR_NO_MORE_DATA_IN : in std_logic := '0'; --IDRAM is used if no 1-wire interface, onewire used otherwise - SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0); + SCTR_IDRAM_DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); SCTR_IDRAM_DATA_OUT : out std_logic_vector(15 downto 0); - SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0); - SCTR_IDRAM_WR_IN : in std_logic; + SCTR_IDRAM_ADDR_IN : in std_logic_vector(2 downto 0) := "000"; + SCTR_IDRAM_WR_IN : in std_logic := '0'; SCTR_ONEWIRE_INOUT : inout std_logic; --Additional r/w access to ctrl registers SCTR_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0'); @@ -128,12 +128,12 @@ entity trb_net16_endpoint_1_trg_2_api_1_regio is SCTR_EXT_REG_WRITE_IN : in std_logic := '0'; SCTR_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0) := (others => '0'); -- Status - MPLEX_CTRL : in std_logic_vector (31 downto 0); - STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0); - STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0); + MPLEX_CTRL : in std_logic_vector (31 downto 0) := (others => '0'); + STAT_CTRL_INIT_BUFFER : in std_logic_vector (4*32-1 downto 0) := (others => '0'); + STAT_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_GEN_1 : out std_logic_vector (31 downto 0); -- General Status STAT_GEN_2 : out std_logic_vector (31 downto 0); -- General Status - CTRL_GEN : in std_logic_vector (4*32-1 downto 0) + CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0') ); end entity; @@ -821,6 +821,7 @@ begin IPUD_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(1*8-1 downto 0*8); LVL2_APL_SEQNR_OUT <= buf_APL_SEQNR_OUT(2*8-1 downto 1*8); + gen_regio : if USE_CHANNEL(c_SLOW_CTRL_CHANNEL) = c_YES generate regIO : trb_net16_regIO generic map( REGISTER_WIDTH => 32, @@ -889,7 +890,8 @@ begin EXT_REG_ADDR_IN => SCTR_EXT_REG_ADDR_IN, STAT => SCTR_REGIO_STAT ); - + end generate; + gen_no1wire : if SCTR_USE_1WIRE_INTERFACE = 0 generate buf_IDRAM_DATA_IN <= SCTR_IDRAM_DATA_IN; buf_IDRAM_ADDR_IN <= SCTR_IDRAM_ADDR_IN; -- 2.43.0