From 8eb678be2319d934ce08dd7760867425ce63c703 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Thu, 21 Aug 2014 15:06:11 +0200 Subject: [PATCH] Revert "nxyter, new working adc handler" This reverts commit c4a02b3d2e11046863a5561372c0e9f6abd11500. --- nxyter/cores/dynamic_shift_register8x64.ipx | 10 + nxyter/cores/dynamic_shift_register8x64.lpc | 41 + nxyter/cores/dynamic_shift_register8x64.vhd | 454 ++++++ nxyter/cores/fifo_data_stream_44to44_dc.ipx | 9 + nxyter/cores/fifo_data_stream_44to44_dc.lpc | 47 + nxyter/cores/fifo_data_stream_44to44_dc.vhd | 606 ++++++++ nxyter/cores/pll_nx_clk250.ipx | 8 +- nxyter/cores/pll_nx_clk250.lpc | 8 +- nxyter/cores/pll_nx_clk250.vhd | 9 +- nxyter/nodelist.txt | 15 - nxyter/source/adc_ad9228.vhd | 662 +++++++-- nxyter/source/nx_data_receiver.vhd | 1412 +++++++++++-------- nxyter/source/nxyter_components.vhd | 2 + nxyter/source/nxyter_fee_board.vhd | 2 + nxyter/trb3_periph.prj | 6 +- nxyter/trb3_periph.vhd | 3 + nxyter/trb3_periph_constraints.lpf | 61 +- nxyter/trb3_periph_multi.p2t | 4 +- nxyter/trb3_periph_nxyter.lpf | 34 +- 19 files changed, 2629 insertions(+), 764 deletions(-) create mode 100644 nxyter/cores/dynamic_shift_register8x64.ipx create mode 100644 nxyter/cores/dynamic_shift_register8x64.lpc create mode 100644 nxyter/cores/dynamic_shift_register8x64.vhd create mode 100644 nxyter/cores/fifo_data_stream_44to44_dc.ipx create mode 100644 nxyter/cores/fifo_data_stream_44to44_dc.lpc create mode 100644 nxyter/cores/fifo_data_stream_44to44_dc.vhd diff --git a/nxyter/cores/dynamic_shift_register8x64.ipx b/nxyter/cores/dynamic_shift_register8x64.ipx new file mode 100644 index 0000000..abd7cc9 --- /dev/null +++ b/nxyter/cores/dynamic_shift_register8x64.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/nxyter/cores/dynamic_shift_register8x64.lpc b/nxyter/cores/dynamic_shift_register8x64.lpc new file mode 100644 index 0000000..dc5aeb9 --- /dev/null +++ b/nxyter/cores/dynamic_shift_register8x64.lpc @@ -0,0 +1,41 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_Based_Shift_Register +CoreRevision=4.1 +ModuleName=dynamic_shift_register8x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/18/2014 +Time=13:07:29 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +DataWidth=8 +Type=VarLossless +NoOfShifts=16 +MaxLossyShifts=16 +MaxLosslessShifts=64 +EOR=1 +MemFile= +MemFormat=orca +RamType=dram + +[FilesGenerated] +=mem diff --git a/nxyter/cores/dynamic_shift_register8x64.vhd b/nxyter/cores/dynamic_shift_register8x64.vhd new file mode 100644 index 0000000..3b85a64 --- /dev/null +++ b/nxyter/cores/dynamic_shift_register8x64.vhd @@ -0,0 +1,454 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 4.1 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register8x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 8 -depth 64 -mode 2 -pipe_final_output -e + +-- Fri Apr 18 13:07:29 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dynamic_shift_register8x64 is + port ( + Din: in std_logic_vector(7 downto 0); + Addr: in std_logic_vector(5 downto 0); + Clock: in std_logic; + ClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(7 downto 0)); +end dynamic_shift_register8x64; + +architecture Structure of dynamic_shift_register8x64 is + + -- internal signal declarations + signal shreg_addr_w5_inv: std_logic; + signal shreg_addr_w4_inv: std_logic; + signal Reset_inv: std_logic; + signal scuba_vhi: std_logic; + signal ishreg_addr_w0: std_logic; + signal ishreg_addr_w1: std_logic; + signal sreg_0_ctr_1_ci: std_logic; + signal ishreg_addr_w2: std_logic; + signal ishreg_addr_w3: std_logic; + signal co0: std_logic; + signal ishreg_addr_w4: std_logic; + signal ishreg_addr_w5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal low_inv: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal shreg_addr_w4: std_logic; + signal co2_1: std_logic; + signal shreg_addr_w5: std_logic; + signal scuba_vlo: std_logic; + signal Q7_ffin: std_logic; + signal Q6_ffin: std_logic; + signal Q5_ffin: std_logic; + signal Q4_ffin: std_logic; + signal Q3_ffin: std_logic; + signal Q2_ffin: std_logic; + signal Q1_ffin: std_logic; + signal Q0_ffin: std_logic; + signal shreg_addr_r5: std_logic; + signal shreg_addr_r4: std_logic; + signal mdL0_0_7: std_logic; + signal mdL0_0_6: std_logic; + signal mdL0_0_5: std_logic; + signal mdL0_0_4: std_logic; + signal mdL0_0_3: std_logic; + signal mdL0_0_2: std_logic; + signal mdL0_0_1: std_logic; + signal mdL0_0_0: std_logic; + signal dec0_wre3: std_logic; + signal mdL0_1_7: std_logic; + signal mdL0_1_6: std_logic; + signal mdL0_1_5: std_logic; + signal mdL0_1_4: std_logic; + signal mdL0_1_3: std_logic; + signal mdL0_1_2: std_logic; + signal mdL0_1_1: std_logic; + signal mdL0_1_0: std_logic; + signal dec1_wre7: std_logic; + signal mdL0_2_7: std_logic; + signal mdL0_2_6: std_logic; + signal mdL0_2_5: std_logic; + signal mdL0_2_4: std_logic; + signal mdL0_2_3: std_logic; + signal mdL0_2_2: std_logic; + signal mdL0_2_1: std_logic; + signal mdL0_2_0: std_logic; + signal dec2_wre11: std_logic; + signal mdL0_3_7: std_logic; + signal mdL0_3_6: std_logic; + signal mdL0_3_5: std_logic; + signal mdL0_3_4: std_logic; + signal mdL0_3_3: std_logic; + signal mdL0_3_2: std_logic; + signal mdL0_3_1: std_logic; + signal mdL0_3_0: std_logic; + signal shreg_addr_r3: std_logic; + signal shreg_addr_r2: std_logic; + signal shreg_addr_r1: std_logic; + signal shreg_addr_r0: std_logic; + signal dec3_wre15: std_logic; + signal shreg_addr_w3: std_logic; + signal shreg_addr_w2: std_logic; + signal shreg_addr_w1: std_logic; + signal shreg_addr_w0: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component MUX41 + port (D0: in std_logic; D1: in std_logic; D2: in std_logic; + D3: in std_logic; SD1: in std_logic; SD2: in std_logic; + Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of sram_1_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of sram_1_0_0 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_0_0 : label is "sram_1_0_0"; + attribute MEM_INIT_FILE of sram_1_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of sram_1_0_1 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_0_1 : label is "sram_1_0_1"; + attribute MEM_INIT_FILE of sram_1_1_0 : label is "(16-31)(0-3)"; + attribute MEM_LPC_FILE of sram_1_1_0 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_1_0 : label is "sram_1_1_0"; + attribute MEM_INIT_FILE of sram_1_1_1 : label is "(16-31)(4-7)"; + attribute MEM_LPC_FILE of sram_1_1_1 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_1_1 : label is "sram_1_1_1"; + attribute MEM_INIT_FILE of sram_1_2_0 : label is "(32-47)(0-3)"; + attribute MEM_LPC_FILE of sram_1_2_0 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_2_0 : label is "sram_1_2_0"; + attribute MEM_INIT_FILE of sram_1_2_1 : label is "(32-47)(4-7)"; + attribute MEM_LPC_FILE of sram_1_2_1 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_2_1 : label is "sram_1_2_1"; + attribute MEM_INIT_FILE of sram_1_3_0 : label is "(48-63)(0-3)"; + attribute MEM_LPC_FILE of sram_1_3_0 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_3_0 : label is "sram_1_3_0"; + attribute MEM_INIT_FILE of sram_1_3_1 : label is "(48-63)(4-7)"; + attribute MEM_LPC_FILE of sram_1_3_1 : label is "dynamic_shift_register8x64.lpc"; + attribute COMP of sram_1_3_1 : label is "sram_1_3_1"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_3: INV + port map (A=>Reset, Z=>Reset_inv); + + INV_2: INV + port map (A=>scuba_vlo, Z=>low_inv); + + INV_1: INV + port map (A=>shreg_addr_w4, Z=>shreg_addr_w4_inv); + + INV_0: INV + port map (A=>shreg_addr_w5, Z=>shreg_addr_w5_inv); + + LUT4_3: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5_inv, DO0=>dec0_wre3); + + LUT4_2: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5_inv, DO0=>dec1_wre7); + + LUT4_1: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4_inv, + AD0=>shreg_addr_w5, DO0=>dec2_wre11); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>Reset_inv, AD2=>ClockEn, AD1=>shreg_addr_w4, + AD0=>shreg_addr_w5, DO0=>dec3_wre15); + + FF_13: FD1P3DX + port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w0); + + FF_12: FD1P3DX + port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w1); + + FF_11: FD1P3DX + port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w2); + + FF_10: FD1P3DX + port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w3); + + FF_9: FD1P3DX + port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w4); + + FF_8: FD1P3DX + port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w5); + + FF_7: FD1P3DX + port map (D=>Q7_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(7)); + + FF_6: FD1P3DX + port map (D=>Q6_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(6)); + + FF_5: FD1P3DX + port map (D=>Q5_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(5)); + + FF_4: FD1P3DX + port map (D=>Q4_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(4)); + + FF_3: FD1P3DX + port map (D=>Q3_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(3)); + + FF_2: FD1P3DX + port map (D=>Q2_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(2)); + + FF_1: FD1P3DX + port map (D=>Q1_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(1)); + + FF_0: FD1P3DX + port map (D=>Q0_ffin, SP=>ClockEn, CK=>Clock, CD=>Reset, Q=>Q(0)); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + sreg_0_ctr_1_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, + S0=>open, S1=>open); + + sreg_0_ctr_1_0: CU2 + port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, + PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, + NC1=>ishreg_addr_w1); + + sreg_0_ctr_1_1: CU2 + port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, + CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); + + sreg_0_ctr_1_2: CU2 + port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, + CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); + + raddr_sub_1_0: FSUB2B + port map (A0=>scuba_vlo, A1=>shreg_addr_w0, B0=>low_inv, + B1=>Addr(0), BI=>scuba_vlo, BOUT=>co0_1, S0=>open, + S1=>shreg_addr_r0); + + raddr_sub_1_1: FSUB2B + port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), + B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, + S1=>shreg_addr_r2); + + raddr_sub_1_2: FSUB2B + port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), + B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, + S1=>shreg_addr_r4); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + raddr_sub_1_3: FSUB2B + port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5), + B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5, + S1=>open); + + mux_7: MUX41 + port map (D0=>mdL0_0_7, D1=>mdL0_1_7, D2=>mdL0_2_7, D3=>mdL0_3_7, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q7_ffin); + + mux_6: MUX41 + port map (D0=>mdL0_0_6, D1=>mdL0_1_6, D2=>mdL0_2_6, D3=>mdL0_3_6, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q6_ffin); + + mux_5: MUX41 + port map (D0=>mdL0_0_5, D1=>mdL0_1_5, D2=>mdL0_2_5, D3=>mdL0_3_5, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q5_ffin); + + mux_4: MUX41 + port map (D0=>mdL0_0_4, D1=>mdL0_1_4, D2=>mdL0_2_4, D3=>mdL0_3_4, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q4_ffin); + + mux_3: MUX41 + port map (D0=>mdL0_0_3, D1=>mdL0_1_3, D2=>mdL0_2_3, D3=>mdL0_3_3, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q3_ffin); + + mux_2: MUX41 + port map (D0=>mdL0_0_2, D1=>mdL0_1_2, D2=>mdL0_2_2, D3=>mdL0_3_2, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q2_ffin); + + mux_1: MUX41 + port map (D0=>mdL0_0_1, D1=>mdL0_1_1, D2=>mdL0_2_1, D3=>mdL0_3_1, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q1_ffin); + + mux_0: MUX41 + port map (D0=>mdL0_0_0, D1=>mdL0_1_0, D2=>mdL0_2_0, D3=>mdL0_3_0, + SD1=>shreg_addr_r4, SD2=>shreg_addr_r5, Z=>Q0_ffin); + + sram_1_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_0_4, DO1=>mdL0_0_5, + DO2=>mdL0_0_6, DO3=>mdL0_0_7); + + sram_1_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_0_0, DO1=>mdL0_0_1, + DO2=>mdL0_0_2, DO3=>mdL0_0_3); + + sram_1_1_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), + WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_1_4, DO1=>mdL0_1_5, + DO2=>mdL0_1_6, DO3=>mdL0_1_7); + + sram_1_1_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + WCK=>Clock, WRE=>dec1_wre7, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_1_0, DO1=>mdL0_1_1, + DO2=>mdL0_1_2, DO3=>mdL0_1_3); + + sram_1_2_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), + WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_2_4, DO1=>mdL0_2_5, + DO2=>mdL0_2_6, DO3=>mdL0_2_7); + + sram_1_2_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + WCK=>Clock, WRE=>dec2_wre11, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_2_0, DO1=>mdL0_2_1, + DO2=>mdL0_2_2, DO3=>mdL0_2_3); + + sram_1_3_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(4), DI1=>Din(5), DI2=>Din(6), DI3=>Din(7), + WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_3_4, DO1=>mdL0_3_5, + DO2=>mdL0_3_6, DO3=>mdL0_3_7); + + sram_1_3_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + WCK=>Clock, WRE=>dec3_wre15, RAD0=>shreg_addr_r0, + RAD1=>shreg_addr_r1, RAD2=>shreg_addr_r2, + RAD3=>shreg_addr_r3, WAD0=>shreg_addr_w0, + WAD1=>shreg_addr_w1, WAD2=>shreg_addr_w2, + WAD3=>shreg_addr_w3, DO0=>mdL0_3_0, DO1=>mdL0_3_1, + DO2=>mdL0_3_2, DO3=>mdL0_3_3); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dynamic_shift_register8x64 is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:MUX41 use entity ecp3.MUX41(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/fifo_data_stream_44to44_dc.ipx b/nxyter/cores/fifo_data_stream_44to44_dc.ipx new file mode 100644 index 0000000..af6ce25 --- /dev/null +++ b/nxyter/cores/fifo_data_stream_44to44_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_data_stream_44to44_dc.lpc b/nxyter/cores/fifo_data_stream_44to44_dc.lpc new file mode 100644 index 0000000..9d39529 --- /dev/null +++ b/nxyter/cores/fifo_data_stream_44to44_dc.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_data_stream_44to44_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=04/15/2014 +Time=22:11:13 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=44 +RDepth=4 +RWidth=44 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/nxyter/cores/fifo_data_stream_44to44_dc.vhd b/nxyter/cores/fifo_data_stream_44to44_dc.vhd new file mode 100644 index 0000000..221cda5 --- /dev/null +++ b/nxyter/cores/fifo_data_stream_44to44_dc.vhd @@ -0,0 +1,606 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.4 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 44 -depth 4 -rdata_width 44 -regout -no_enable -pe -1 -pf -1 -e + +-- Tue Apr 15 22:11:13 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_data_stream_44to44_dc is + port ( + Data: in std_logic_vector(43 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(43 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_data_stream_44to44_dc; + +architecture Structure of fifo_data_stream_44to44_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal wcount_2: std_logic; + signal co0: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal rcount_2: std_logic; + signal co0_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_data_stream_44to44_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_data_stream_44to44_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>scuba_vlo, DI9=>scuba_vlo, + DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo, + DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo, + DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo, + DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo, + DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo, + DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo, + DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo, + DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo, + DI34=>scuba_vlo, DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, + ADW2=>scuba_vlo, ADW3=>scuba_vlo, ADW4=>scuba_vlo, + ADW5=>scuba_vlo, ADW6=>scuba_vlo, ADW7=>scuba_vlo, + ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>scuba_vlo, ADR8=>scuba_vlo, ADR9=>scuba_vlo, + ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo, + ADR13=>scuba_vlo, CER=>scuba_vhi, CLKR=>RdClock, + CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, + DO0=>open, DO1=>open, DO2=>open, DO3=>open, DO4=>open, + DO5=>open, DO6=>open, DO7=>open, DO8=>open, DO9=>open, + DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, + DO15=>open, DO16=>open, DO17=>open, DO18=>Q(36), DO19=>Q(37), + DO20=>Q(38), DO21=>Q(39), DO22=>Q(40), DO23=>Q(41), + DO24=>Q(42), DO25=>Q(43), DO26=>open, DO27=>open, DO28=>open, + DO29=>open, DO30=>open, DO31=>open, DO32=>open, DO33=>open, + DO34=>open, DO35=>open); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_data_stream_44to44_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/pll_nx_clk250.ipx b/nxyter/cores/pll_nx_clk250.ipx index 7f1ff1a..4b69c49 100644 --- a/nxyter/cores/pll_nx_clk250.ipx +++ b/nxyter/cores/pll_nx_clk250.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/nxyter/cores/pll_nx_clk250.lpc b/nxyter/cores/pll_nx_clk250.lpc index 8cdcdc6..5560e3e 100644 --- a/nxyter/cores/pll_nx_clk250.lpc +++ b/nxyter/cores/pll_nx_clk250.lpc @@ -16,8 +16,8 @@ CoreRevision=5.6 ModuleName=pll_nx_clk250 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=08/13/2014 -Time=20:33:11 +Date=08/04/2014 +Time=16:09:19 [Parameters] Verilog=0 @@ -61,9 +61,9 @@ Bandwidth=1.753251 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 -EnCLKOK=0 +EnCLKOK=1 ClkOKBp=0 enClkOK2=0 [Command] -cmd_line= -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw +cmd_line= -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw diff --git a/nxyter/cores/pll_nx_clk250.vhd b/nxyter/cores/pll_nx_clk250.vhd index 6143d71..8f788e4 100644 --- a/nxyter/cores/pll_nx_clk250.vhd +++ b/nxyter/cores/pll_nx_clk250.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 -- Module Version: 5.6 ---/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n pll_nx_clk250 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 250 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -fclkok 125 -fclkok_tol 0.0 -clkoki 0 -use_rst -noclkok2 -bw --- Wed Aug 13 20:33:11 2014 +-- Mon Aug 4 16:09:19 2014 library IEEE; use IEEE.std_logic_1164.all; @@ -16,6 +16,7 @@ entity pll_nx_clk250 is CLK: in std_logic; RESET: in std_logic; CLKOP: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic); attribute dont_touch : boolean; attribute dont_touch of pll_nx_clk250 : entity is true; @@ -54,8 +55,10 @@ architecture Structure of pll_nx_clk250 is end component; attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOK : string; attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000"; attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; + attribute FREQUENCY_PIN_CLKOK of PLLInst_0 : label is "125.000000"; attribute syn_keep : boolean; attribute syn_noprune : boolean; attribute syn_noprune of Structure : architecture is true; @@ -81,7 +84,7 @@ begin DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, - FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); CLKOP <= CLKOP_t; diff --git a/nxyter/nodelist.txt b/nxyter/nodelist.txt index 74db793..756c1ad 100755 --- a/nxyter/nodelist.txt +++ b/nxyter/nodelist.txt @@ -1,18 +1,3 @@ -[c2] -system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[c3] -system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ -[c4] -system = linux -corenum = 4 -env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env -workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ [c5] system = linux corenum = 4 diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 13b473d..268b591 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -44,7 +44,6 @@ entity adc_ad9228 is ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_CLK_OUT : out std_logic; - ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; @@ -64,18 +63,91 @@ architecture Behavioral of adc_ad9228 is signal q_1_f : std_logic_vector(19 downto 0); signal q_1 : std_logic_vector(19 downto 0); - -- Data Types --- type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0); + -- Merge Data + type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0); type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + type BYTE_STATUS is (B_UNDEF, + B_BITSHIFTED, + B_ALIGNED, + B_SHIFTED + ); + -- ADC0 + signal adc0_data_shift : adc_data_s; + + signal adc0_data_m : adc_data_t; + signal adc0_data_clk_m : std_logic; + + signal adc0_data_m_f : adc_data_t; + signal adc0_data_clk_m_f : std_logic; + + signal adc0_byte_status : BYTE_STATUS; + signal adc0_byte_status_last : BYTE_STATUS; + + signal adc0_frame_clk_ok : std_logic; + signal adc0_frame_clk_ok_hist : std_logic_vector(15 downto 0); + signal adc0_frame_locked : std_logic; + signal adc0_error : std_logic; + signal adc0_error_undef : std_logic; + + -- ADC0 + signal adc1_data_shift : adc_data_s; + + signal adc1_data_m : adc_data_t; + signal adc1_data_clk_m : std_logic; + + signal adc1_byte_status : BYTE_STATUS; + signal adc1_byte_status_last : BYTE_STATUS; + + signal adc1_frame_clk_ok : std_logic; + signal adc1_frame_clk_ok_hist : std_logic_vector(15 downto 0); + signal adc1_frame_locked : std_logic; + signal adc1_error : std_logic; + signal adc1_error_undef : std_logic; + + -- Clock Transfer + signal adc0_fifo_empty : std_logic; + signal adc0_fifo_full : std_logic; + signal adc0_write_enable : std_logic; + signal adc0_read_enable : std_logic; + signal adc0_read_enable_t : std_logic; + signal adc0_read_enable_tt : std_logic; + signal adc0_locked_ff : std_logic; + signal adc0_locked_f : std_logic; + signal adc0_locked_o : std_logic; + + signal adc1_fifo_empty : std_logic; + signal adc1_fifo_full : std_logic; + signal adc1_write_enable : std_logic; + signal adc1_read_enable : std_logic; + signal adc1_read_enable_t : std_logic; + signal adc1_read_enable_tt : std_logic; + signal adc1_locked_ff : std_logic; + signal adc1_locked_f : std_logic; + signal adc1_locked_o : std_logic; + + -- Error + signal error_adc0_ff : std_logic; + signal error_adc0_f : std_logic; + signal error_adc0_o : std_logic; + signal error_adc1_ff : std_logic; + signal error_adc1_f : std_logic; + signal error_adc1_o : std_logic; + signal error_undef_adc0_ff : std_logic; + signal error_undef_adc0_f : std_logic; + signal error_undef_adc0_o : std_logic; + signal error_undef_adc1_ff : std_logic; + signal error_undef_adc1_f : std_logic; + signal error_undef_adc1_o : std_logic; + -- Output signal adc0_data_clk_o : std_logic; + signal adc0_data_f : adc_data_t; signal adc0_data_o : adc_data_t; - signal adc0_locked_o : std_logic; - + signal adc1_data_clk_o : std_logic; + signal adc1_data_f : adc_data_t; signal adc1_data_o : adc_data_t; - signal adc1_locked_o : std_logic; -- RESET Handler type R_STATES is (R_IDLE, @@ -101,23 +173,63 @@ architecture Behavioral of adc_ad9228 is -- attribute syn_keep : boolean; - attribute syn_keep of q_0_ff : signal is true; - attribute syn_keep of q_0_f : signal is true; - attribute syn_keep of q_1_ff : signal is true; - attribute syn_keep of q_1_f : signal is true; - - attribute syn_keep of RESET_ADC0_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC0_CLKD : signal is true; - attribute syn_keep of RESET_ADC1_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC1_CLKD : signal is true; - + attribute syn_keep of q_0_ff : signal is true; + attribute syn_keep of q_0_f : signal is true; + attribute syn_keep of q_1_ff : signal is true; + attribute syn_keep of q_1_f : signal is true; + + attribute syn_keep of adc0_locked_ff : signal is true; + attribute syn_keep of adc0_locked_f : signal is true; + attribute syn_keep of adc1_locked_ff : signal is true; + attribute syn_keep of adc1_locked_f : signal is true; + + attribute syn_keep of adc0_data_m_f : signal is true; + attribute syn_keep of adc0_data_clk_m_f : signal is true; + +-- attribute syn_keep of error_adc0_ff : signal is true; +-- attribute syn_keep of error_adc0_f : signal is true; +-- attribute syn_keep of error_adc1_ff : signal is true; +-- attribute syn_keep of error_adc1_f : signal is true; +-- +-- attribute syn_keep of error_undef_adc0_ff : signal is true; +-- attribute syn_keep of error_undef_adc0_f : signal is true; +-- attribute syn_keep of error_undef_adc1_ff : signal is true; +-- attribute syn_keep of error_undef_adc1_f : signal is true; + + attribute syn_keep of RESET_ADC0_CLKD_F : signal is true; + attribute syn_keep of RESET_ADC0_CLKD : signal is true; + attribute syn_keep of RESET_ADC1_CLKD_F : signal is true; + attribute syn_keep of RESET_ADC1_CLKD : signal is true; + attribute syn_preserve : boolean; + attribute syn_preserve of q_0_ff : signal is true; + attribute syn_preserve of q_0_f : signal is true; + attribute syn_preserve of q_1_ff : signal is true; + attribute syn_preserve of q_1_f : signal is true; + + attribute syn_preserve of adc0_locked_ff : signal is true; + attribute syn_preserve of adc0_locked_f : signal is true; + attribute syn_preserve of adc1_locked_ff : signal is true; + attribute syn_preserve of adc1_locked_f : signal is true; + + attribute syn_preserve of adc0_data_m_f : signal is true; + attribute syn_preserve of adc0_data_clk_m_f : signal is true; + +-- attribute syn_preserve of error_adc0_ff : signal is true; +-- attribute syn_preserve of error_adc0_f : signal is true; +-- attribute syn_preserve of error_adc1_ff : signal is true; +-- attribute syn_preserve of error_adc1_f : signal is true; +-- +-- attribute syn_preserve of error_undef_adc0_ff : signal is true; +-- attribute syn_preserve of error_undef_adc0_f : signal is true; +-- attribute syn_preserve of error_undef_adc1_ff : signal is true; +-- attribute syn_preserve of error_undef_adc1_f : signal is true; - attribute syn_preserve of q_0_ff : signal is true; - attribute syn_preserve of q_0_f : signal is true; - attribute syn_preserve of q_1_ff : signal is true; - attribute syn_preserve of q_1_f : signal is true; - + attribute syn_preserve of RESET_ADC0_CLKD_F : signal is true; + attribute syn_preserve of RESET_ADC0_CLKD : signal is true; + attribute syn_preserve of RESET_ADC1_CLKD_F : signal is true; + attribute syn_preserve of RESET_ADC1_CLKD : signal is true; + begin ----------------------------------------------------------------------------- @@ -148,97 +260,57 @@ begin PROC_DEBUG: process (DEBUG_IN) begin - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DDR_DATA_CLK; + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= DDR_DATA_CLK; case DEBUG_IN is - when others => - DEBUG_OUT(15 downto 2) <= (others => '0'); + when x"1" => + DEBUG_OUT(15 downto 2) <= adc0_data_shift(0); + + when x"2" => + DEBUG_OUT(15 downto 2) <= adc0_data_shift(1); + + when x"3" => + DEBUG_OUT(15 downto 2) <= adc0_data_shift(2); + + when x"4" => + DEBUG_OUT(15 downto 2) <= adc0_data_shift(3); + when x"5" => + DEBUG_OUT(15 downto 2) <= adc0_data_shift(4); + + when others => + -- DEBUG + DEBUG_OUT(2) <= adc0_write_enable; + DEBUG_OUT(3) <= adc0_fifo_full; + DEBUG_OUT(4) <= adc0_fifo_empty; + DEBUG_OUT(5) <= adc0_data_clk_m; + DEBUG_OUT(6) <= adc0_read_enable; + DEBUG_OUT(7) <= adc0_read_enable_t; + DEBUG_OUT(8) <= adc0_read_enable_tt; + DEBUG_OUT(9) <= adc0_data_clk_o; + DEBUG_OUT(10) <= adc0_error; + DEBUG_OUT(11) <= adc0_frame_locked; + DEBUG_OUT(12) <= adc0_frame_clk_ok; + DEBUG_OUT(13) <= wait_timer_done; + DEBUG_OUT(14) <= RESET_CLKDIV; + DEBUG_OUT(15) <= RESET_ADC0; + end case; end process PROC_DEBUG; end generate DTRUE; ----------------------------------------------------------------------------- - -- DDR Generic Interface to ADC - ----------------------------------------------------------------------------- - adc_ddr_generic_1: entity work.adc_ddr_generic - port map ( - clk_0 => ADC0_DCLK_IN, - clk_1 => ADC1_DCLK_IN, - clkdiv_reset => RESET_CLKDIV, - eclk => CLK_ADCDAT_IN, - reset_0 => RESET_ADC0, - reset_1 => RESET_ADC1, - sclk => DDR_DATA_CLK, - - datain_0(0) => ADC0_DATA_A_IN, - datain_0(1) => ADC0_DATA_B_IN, - datain_0(2) => ADC0_DATA_C_IN, - datain_0(3) => ADC0_DATA_D_IN, - datain_0(4) => ADC0_FCLK_IN, - - datain_1(0) => ADC1_DATA_A_IN, - datain_1(1) => ADC1_DATA_B_IN, - datain_1(2) => ADC1_DATA_C_IN, - datain_1(3) => ADC1_DATA_D_IN, - datain_1(4) => ADC1_FCLK_IN, - - q_0 => q_0_ff, - q_1 => q_1_ff - ); - - -- Two FIFOs to relaxe timing - q_0_f <= q_0_ff when rising_edge(DDR_DATA_CLK); - q_0 <= q_0_f when rising_edge(DDR_DATA_CLK); - - q_1_f <= q_1_ff when rising_edge(DDR_DATA_CLK); - q_1 <= q_1_f when rising_edge(DDR_DATA_CLK); - - -- The ADC Data Handlers - adc_ad9228_data_handler_1: entity work.adc_ad9228_data_handler - generic map ( - DEBUG_ENABLE => DEBUG_ENABLE - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC0, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_0, - DATA_A_OUT => adc0_data_o(0), - DATA_B_OUT => adc0_data_o(1), - DATA_C_OUT => adc0_data_o(2), - DATA_D_OUT => adc0_data_o(3), - DATA_CLK_OUT => adc0_data_clk_o, - FRAME_LOCKED_OUT => adc0_locked_o, - ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, - DEBUG_OUT => open - ); - adc_ad9228_data_handler_2: entity work.adc_ad9228_data_handler - generic map ( - DEBUG_ENABLE => DEBUG_ENABLE - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC1, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_1, - DATA_A_OUT => adc1_data_o(0), - DATA_B_OUT => adc1_data_o(1), - DATA_C_OUT => adc1_data_o(2), - DATA_D_OUT => adc1_data_o(3), - DATA_CLK_OUT => adc1_data_clk_o, - FRAME_LOCKED_OUT => adc1_locked_o, - ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, - DEBUG_OUT => open - ); + RESET_ADC0_CLKD_F <= RESET_ADC0 when rising_edge(DDR_DATA_CLK); + RESET_ADC0_CLKD <= RESET_ADC0_CLKD_F when rising_edge(DDR_DATA_CLK); + + RESET_ADC1_CLKD_F <= RESET_ADC1 when rising_edge(DDR_DATA_CLK); + RESET_ADC1_CLKD <= RESET_ADC1_CLKD_F when rising_edge(DDR_DATA_CLK); ----------------------------------------------------------------------------- - -- Reset Handler - ----------------------------------------------------------------------------- timer_static_RESET_TIMER: timer_static generic map ( @@ -270,7 +342,7 @@ begin wait_timer_start <= '0'; timer_reset <= '0'; startup_reset <= '0'; - + case R_STATE is when R_IDLE => if (startup_reset = '1') then @@ -322,8 +394,396 @@ begin end process PROC_DDR_RESET_HANDLER; ----------------------------------------------------------------------------- - -- Outputs + + adc_ddr_generic_1: entity work.adc_ddr_generic + port map ( + clk_0 => ADC0_DCLK_IN, + clk_1 => ADC1_DCLK_IN, + clkdiv_reset => RESET_CLKDIV, + eclk => CLK_ADCDAT_IN, + reset_0 => RESET_ADC0, + reset_1 => RESET_ADC1, + sclk => DDR_DATA_CLK, + + datain_0(0) => ADC0_DATA_A_IN, + datain_0(1) => ADC0_DATA_B_IN, + datain_0(2) => ADC0_DATA_C_IN, + datain_0(3) => ADC0_DATA_D_IN, + datain_0(4) => ADC0_FCLK_IN, + + datain_1(0) => ADC1_DATA_A_IN, + datain_1(1) => ADC1_DATA_B_IN, + datain_1(2) => ADC1_DATA_C_IN, + datain_1(3) => ADC1_DATA_D_IN, + datain_1(4) => ADC1_FCLK_IN, + + q_0 => q_0_ff, + q_1 => q_1_ff + ); + + -- Two Input FIFOs to relaxe timing + q_0_f <= q_0_ff when rising_edge(DDR_DATA_CLK); + q_0 <= q_0_f when rising_edge(DDR_DATA_CLK); + + q_1_f <= q_1_ff when rising_edge(DDR_DATA_CLK); + q_1 <= q_1_f when rising_edge(DDR_DATA_CLK); + + ----------------------------------------------------------------------------- + + PROC_MERGE_DATA_ADC0: process(DDR_DATA_CLK) + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_ADC0_CLKD = '1') then + for I in 0 to 4 loop + adc0_data_shift(I) <= (others => '0'); + end loop; + + for I in 0 to 3 loop + adc0_data_m(I) <= (others => '0'); + end loop; + adc0_data_clk_m <= '0'; + + adc0_byte_status <= B_UNDEF; + adc0_byte_status_last <= B_UNDEF; + adc0_frame_clk_ok <= '0'; + adc0_frame_clk_ok_hist <= (others => '0'); + adc0_frame_locked <= '0'; + adc0_error <= '0'; + adc0_error_undef <= '0'; + else + -- Store new incoming Data in Shift Registers + for I in 0 to 4 loop + adc0_data_shift(I)(3) <= q_0(I + 0); + adc0_data_shift(I)(2) <= q_0(I + 5); + adc0_data_shift(I)(1) <= q_0(I + 10); + adc0_data_shift(I)(0) <= q_0(I + 15); + adc0_data_shift(I)(13 downto 4) <= adc0_data_shift(I)(9 downto 0); + end loop; + + -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock + case adc0_data_shift(4)(11 downto 0) is + when "111111000000" => + -- Input Data is correct and new Frame is available + for I in 0 to 3 loop + adc0_data_m(I) <= adc0_data_shift(I)(11 downto 0); + end loop; + adc0_data_clk_m <= '1'; + adc0_frame_clk_ok <= '1'; + adc0_byte_status <= B_ALIGNED; + + when "111100000011" => + -- Input Data is correct and new Frame is available, + -- but byte shifted by one + for I in 0 to 3 loop + adc0_data_m(I) <= adc0_data_shift(I)(13 downto 2); + end loop; + adc0_data_clk_m <= '1'; + adc0_frame_clk_ok <= '1'; + adc0_byte_status <= B_SHIFTED; + + when "110000001111" | "000011111100" => + -- Input Data is correct + adc0_data_clk_m <= '0'; + adc0_frame_clk_ok <= '1'; + adc0_byte_status <= B_ALIGNED; + + when "000000111111" | "001111110000" => + -- Input Data is correct + adc0_data_clk_m <= '0'; + adc0_frame_clk_ok <= '1'; + adc0_byte_status <= B_SHIFTED; + + when "000001111110" | + "000111111000" | + "011111100000" | + "111110000001" | + "111000000111" | + "100000011111" => + adc0_data_clk_m <= '0'; + adc0_frame_clk_ok <= '0'; + adc0_byte_status <= B_BITSHIFTED; + + when others => + -- Input Data is invalid, Fatal Error of DDR Data, needs reset. + adc0_data_clk_m <= '0'; + adc0_frame_clk_ok <= '0'; + adc0_byte_status <= B_UNDEF; + + end case; + + -- Determin ADC Frame Lock Status + adc0_frame_clk_ok_hist(0) <= adc0_frame_clk_ok; + adc0_frame_clk_ok_hist(15 downto 1) <= + adc0_frame_clk_ok_hist(14 downto 0); + + if (adc0_frame_clk_ok_hist = x"ffff") then + adc0_frame_locked <= '1'; + else + adc0_frame_locked <= '0'; + end if; + + -- Error Status + adc0_byte_status_last <= adc0_byte_status; + --if (adc0_byte_status /= adc0_byte_status_last and + -- adc0_byte_status /= B_UNDEF and + -- adc0_byte_status_last /= B_UNDEF) then + if (adc0_byte_status = B_BITSHIFTED) then + adc0_error <= '1'; + else + adc0_error <= '0'; + end if; + + if (adc0_byte_status = B_UNDEF) then + adc0_error_undef <= '1'; + else + adc0_error_undef <= '0'; + end if; + + end if; + + end if; + end process PROC_MERGE_DATA_ADC0; + + ----------------------------------------------------------------------------- + + PROC_MERGE_DATA_ADC1: process(DDR_DATA_CLK) + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_ADC1_CLKD = '1') then + for I in 0 to 4 loop + adc1_data_shift(I) <= (others => '0'); + end loop; + + for I in 0 to 3 loop + adc1_data_m(I) <= (others => '0'); + end loop; + adc1_data_clk_m <= '0'; + + adc1_byte_status <= B_UNDEF; + adc1_byte_status_last <= B_UNDEF; + adc1_frame_clk_ok <= '0'; + adc1_frame_clk_ok_hist <= (others => '0'); + adc1_frame_locked <= '0'; + adc1_error <= '0'; + else + + -- Store new incoming Data in Shift Registers + for I in 0 to 4 loop + adc1_data_shift(I)(3) <= q_1(I + 0); + adc1_data_shift(I)(2) <= q_1(I + 5); + adc1_data_shift(I)(1) <= q_1(I + 10); + adc1_data_shift(I)(0) <= q_1(I + 15); + + adc1_data_shift(I)(13 downto 4) <= adc1_data_shift(I)(9 downto 0); + end loop; + + -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock + case adc1_data_shift(4)(11 downto 0) is + when "111111000000" => + -- Input Data is correct and new Frame is available + for I in 0 to 3 loop + adc1_data_m(I) <= adc1_data_shift(I)(11 downto 0); + end loop; + adc1_data_clk_m <= '1'; + adc1_frame_clk_ok <= '1'; + adc1_byte_status <= B_ALIGNED; + + when "111100000011" => + -- Input Data is correct and new Frame is available, + -- but byte shifted by one + for I in 0 to 3 loop + adc1_data_m(I) <= adc1_data_shift(I)(13 downto 2); + end loop; + adc1_data_clk_m <= '1'; + adc1_frame_clk_ok <= '1'; + adc1_byte_status <= B_SHIFTED; + + when "110000001111" | "000011111100" => + -- Input Data is correct + adc1_data_clk_m <= '0'; + adc1_frame_clk_ok <= '1'; + adc1_byte_status <= B_ALIGNED; + + when "000000111111" | "001111110000" => + -- Input Data is correct + adc1_data_clk_m <= '0'; + adc1_frame_clk_ok <= '1'; + adc1_byte_status <= B_SHIFTED; + + when others => + -- Input Data is invalid, Fatal Error of DDR Data, needs reset. + adc1_data_clk_m <= '0'; + adc1_frame_clk_ok <= '0'; + adc1_byte_status <= B_UNDEF; + + end case; + + -- Determin ADC Frame Lock Status + adc1_frame_clk_ok_hist(0) <= adc1_frame_clk_ok; + adc1_frame_clk_ok_hist(15 downto 1) <= + adc1_frame_clk_ok_hist(14 downto 0); + + if (adc1_frame_clk_ok_hist = x"ffff") then + adc1_frame_locked <= '1'; + else + adc1_frame_locked <= '0'; + end if; + + -- Error Status + adc1_byte_status_last <= adc1_byte_status; + if (adc1_byte_status /= adc1_byte_status_last) then + adc1_error <= '1'; + else + adc1_error <= '0'; + end if; + + if (adc1_byte_status = B_UNDEF) then + adc1_error_undef <= '1'; + else + adc1_error_undef <= '0'; + end if; + + end if; + end if; + end process PROC_MERGE_DATA_ADC1; + + + ----------------------------------------------------------------------------- + -- Tansfer to CLK_IN + ----------------------------------------------------------------------------- + + adc0_data_m_f <= adc0_data_m when rising_edge(DDR_DATA_CLK); + adc0_data_clk_m_f <= adc0_data_clk_m when rising_edge(DDR_DATA_CLK); + + fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc + port map ( + Data(11 downto 0) => adc0_data_m_f(0), + Data(23 downto 12) => adc0_data_m_f(1), + Data(35 downto 24) => adc0_data_m_f(2), + Data(47 downto 36) => adc0_data_m_f(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc0_write_enable, + RdEn => adc0_read_enable, + Reset => RESET_ADC0, + RPReset => RESET_ADC0, + Q(11 downto 0) => adc0_data_f(0), + Q(23 downto 12) => adc0_data_f(1), + Q(35 downto 24) => adc0_data_f(2), + Q(47 downto 36) => adc0_data_f(3), + Empty => adc0_fifo_empty, + Full => adc0_fifo_full + ); + + -- Readout Handler + adc0_write_enable <= adc0_data_clk_m_f and not adc0_fifo_full; + adc0_read_enable <= not adc0_fifo_empty; + + PROC_ADC0_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + adc0_read_enable_t <= adc0_read_enable; + if (RESET_IN = '1') then + adc0_read_enable_tt <= '0'; + for I in 0 to 3 loop + adc0_data_o(I) <= (others => '0'); + end loop; + adc0_data_clk_o <= '0'; + else + -- Read enable + adc0_read_enable_tt <= adc0_read_enable_t; + + if (adc0_read_enable_tt = '1') then + for I in 0 to 3 loop + adc0_data_o(I) <= adc0_data_f(I); + end loop; + adc0_data_clk_o <= '1'; + else + adc0_data_clk_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC0_FIFO_READ; + ----------------------------------------------------------------------------- + + fifo_adc_48to48_dc_2: entity work.fifo_adc_48to48_dc + port map ( + Data(11 downto 0) => adc1_data_m(0), + Data(23 downto 12) => adc1_data_m(1), + Data(35 downto 24) => adc1_data_m(2), + Data(47 downto 36) => adc1_data_m(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc1_write_enable, + RdEn => adc1_read_enable, + Reset => RESET_ADC1, + RPReset => RESET_ADC1, + Q(11 downto 0) => adc1_data_f(0), + Q(23 downto 12) => adc1_data_f(1), + Q(35 downto 24) => adc1_data_f(2), + Q(47 downto 36) => adc1_data_f(3), + Empty => adc1_fifo_empty, + Full => adc1_fifo_full + ); + + -- Readout Handler + adc1_write_enable <= adc1_data_clk_m and not adc1_fifo_full; + adc1_read_enable <= not adc1_fifo_empty; + + PROC_ADC1_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + adc1_read_enable_t <= '0'; + adc1_read_enable_tt <= '0'; + for I in 0 to 3 loop + adc1_data_o(I) <= (others => '0'); + end loop; + adc1_data_clk_o <= '0'; + else + -- Read enable + adc1_read_enable_t <= adc1_read_enable; + adc1_read_enable_tt <= adc1_read_enable_t; + + if (adc1_read_enable_tt = '1') then + for I in 0 to 3 loop + adc1_data_o(I) <= adc1_data_f(I); + end loop; + adc1_data_clk_o <= '1'; + else + adc1_data_clk_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC1_FIFO_READ; + + -- Domain Transfer + adc0_locked_ff <= adc0_frame_locked when rising_edge(CLK_IN); + adc0_locked_f <= adc0_locked_ff when rising_edge(CLK_IN); + adc0_locked_o <= adc0_locked_f when rising_edge(CLK_IN); + + adc1_locked_ff <= adc1_frame_locked when rising_edge(CLK_IN); + adc1_locked_f <= adc1_locked_ff when rising_edge(CLK_IN); + adc1_locked_o <= adc1_locked_f when rising_edge(CLK_IN); + + --error_adc0_ff <= adc0_error when rising_edge(CLK_IN); + --error_adc0_f <= error_adc0_ff when rising_edge(CLK_IN); + --error_adc0_o <= error_adc0_f when rising_edge(CLK_IN); + -- + --error_adc1_ff <= adc1_error when rising_edge(CLK_IN); + --error_adc1_f <= error_adc1_ff when rising_edge(CLK_IN); + --error_adc1_o <= error_adc1_f when rising_edge(CLK_IN); + -- + --error_undef_adc0_ff <= adc0_error_undef when rising_edge(CLK_IN); + --error_undef_adc0_f <= error_undef_adc0_ff when rising_edge(CLK_IN); + --error_undef_adc0_o <= error_undef_adc0_f when rising_edge(CLK_IN); + -- + --error_undef_adc1_ff <= adc1_error_undef when rising_edge(CLK_IN); + --error_undef_adc1_f <= error_undef_adc1_ff when rising_edge(CLK_IN); + --error_undef_adc1_o <= error_undef_adc1_f when rising_edge(CLK_IN); + + -- Output ADC0_SCLK_OUT <= ADC0_SCLK_IN; ADC1_SCLK_OUT <= ADC1_SCLK_IN; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 482b2a5..9458c50 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -14,6 +14,7 @@ entity nx_data_receiver is port( CLK_IN : in std_logic; RESET_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; TRIGGER_IN : in std_logic; NX_ONLINE_IN : in std_logic; NX_CLOCK_ON_IN : in std_logic; @@ -62,11 +63,19 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- NX_TIMESTAMP_IN Process + signal fifo_fw_reset_i : std_logic; + signal fifo_fw_write_enable : std_logic; + signal fifo_fw_read_enable : std_logic; + signal fifo_fw_empty : std_logic; + signal fifo_fw_full : std_logic; + signal nx_timestamp_delay_f : unsigned(2 downto 0); signal nx_timestamp_delay : unsigned(2 downto 0); signal nx_shift_register_delay : std_logic_vector(5 downto 0); + signal nx_frame_word_fff : std_logic_vector(7 downto 0); signal nx_frame_word_ff : std_logic_vector(7 downto 0); signal nx_frame_word_f : std_logic_vector(7 downto 0); + signal nx_frame_word_s : std_logic_vector(7 downto 0); signal nx_frame_word_t : std_logic_vector(31 downto 0); signal nx_frame_clk_t : std_logic; @@ -81,25 +90,20 @@ architecture Behavioral of nx_data_receiver is signal nx_frame_synced : std_logic; signal rs_sync_set : std_logic; signal rs_sync_reset : std_logic; - - -- NX Frame Delay - signal nx_frame_word_s : std_logic_vector(31 downto 0); - signal nx_frame_clk_s : std_logic; - -- Clock Domain Transfer NX Data - signal fifo_nx_reset_i : std_logic; - signal fifo_nx_write_enable : std_logic; - signal fifo_nx_read_enable : std_logic; - signal fifo_nx_empty : std_logic; - signal fifo_nx_full : std_logic; - signal fifo_nx_data : std_logic_vector(31 downto 0); - signal fifo_nx_data_clk_tt : std_logic; - signal fifo_nx_data_clk_t : std_logic; - signal fifo_nx_data_clk : std_logic; - signal nx_data : std_logic_vector(31 downto 0); - signal nx_data_clk : std_logic; + -- NX Timestamp Frame Delay + type delay_array_b is array(0 to 3) of std_logic_vector(31 downto 0); + signal nx_frame_word_delayed_t : delay_array_b; - ----------------------------------------------------------------------------- + signal nx_frame_clk_delayed_t : std_logic_vector(3 downto 0); + signal nx_timestamp_delayed : std_logic_vector(31 downto 0); + signal nx_timestamp_delayed_clk : std_logic; + + signal nx_frame_word_delay_f : unsigned(1 downto 0); + signal nx_frame_word_delay : unsigned(1 downto 0); + signal adc_data_clk_last : std_logic_vector(3 downto 0); + signal frame_word_delay_change : std_logic; + signal frame_word_delay_set : std_logic; -- ADC Ckl Generator signal adc_sclk_skip : std_logic; @@ -108,6 +112,7 @@ architecture Behavioral of nx_data_receiver is signal johnson_ff_1 : std_logic; signal johnson_counter_sync : std_logic_vector(1 downto 0); signal adc_sclk_ok : std_logic; + signal adc_sclk_ok_f : std_logic; signal adc_sclk_ok_c100 : std_logic; signal pll_adc_sampling_clk_o : std_logic; @@ -115,7 +120,7 @@ architecture Behavioral of nx_data_receiver is -- PLL ADC Monitor signal pll_adc_not_lock : std_logic; - signal pll_adc_not_lock_shift : std_logic_vector(1 downto 0); + signal pll_adc_not_lock_f : std_logic_vector(1 downto 0); signal pll_adc_not_lock_ctr : unsigned(11 downto 0); signal pll_adc_not_lock_ctr_clear : std_logic; @@ -133,31 +138,40 @@ architecture Behavioral of nx_data_receiver is signal ADC_RESET_AD9228 : std_logic; signal adc_data : std_logic_vector(11 downto 0); signal adc_data_clk : std_logic; + signal adc_data_clk_c100 : std_logic; signal adc_locked : std_logic; + signal adc_locked_c100 : std_logic; signal adc_notlocked_p : std_logic; signal adc_data_s : std_logic_vector(11 downto 0); signal adc_data_s_clk : std_logic; signal adc_notlock_ctr : unsigned(7 downto 0); signal ADC_DEBUG : std_logic_vector(15 downto 0); + signal adc_debug_type_f : std_logic_vector(3 downto 0); + signal adc_debug_type : std_logic_vector(3 downto 0); -- Merge Data Streams + signal merge_handler_reset_i : std_logic; signal merge_handler_reset : std_logic; - signal merge_status : std_logic_vector(1 downto 0); - signal merge_status_error : std_logic; - signal merge_timing_ctr : unsigned(2 downto 0); - signal merge_timing_error : std_logic; - + signal data_frame_f : std_logic_vector(43 downto 0); + signal data_frame : std_logic_vector(43 downto 0); + signal data_frame_clk_f : std_logic; + signal data_frame_clk : std_logic; + signal merge_timeout_ctr : unsigned(3 downto 0); + signal merge_timeout_error : std_logic; signal merge_error_ctr : unsigned(11 downto 0); - - signal data_m : std_logic_vector(43 downto 0); - signal data_clk_m : std_logic; - + -- Data Output Handler signal data_o : std_logic_vector(43 downto 0); signal data_clk_o : std_logic; - -- ADC Sampling Clock Phase adjustment + -- Check Nxyter Data Clock via Johnson Counter + signal nx_data_clock_test_0 : std_logic; + signal nx_data_clock_test_1 : std_logic; + signal nx_data_clock : std_logic; + signal nx_data_clock_state : std_logic_vector(3 downto 0); + signal nx_data_clock_ok : std_logic; + signal pll_adc_sample_clk_dphase : std_logic_vector(3 downto 0); signal pll_adc_sample_clk_finedelb : std_logic_vector(3 downto 0); @@ -176,15 +190,15 @@ architecture Behavioral of nx_data_receiver is signal error_o : std_logic; signal error_status_bits : std_logic_vector(15 downto 0); signal adc_notlock_counter : unsigned(27 downto 0); - signal nx_online : std_logic; - signal nx_online_shift : std_logic_vector(1 downto 0); - signal reset_after_offline : std_logic; -- Rate Errors + signal nx_frame_rate_offline_last : std_logic; + signal nx_frame_rate_offline : std_logic; signal nx_frame_rate_error : std_logic; signal adc_frame_rate_error : std_logic; signal frame_rate_error : std_logic; signal parity_rate_error : std_logic; + signal reset_for_offline : std_logic; -- Events per Second Errors signal adc_dt_error_cur : std_logic; @@ -193,20 +207,32 @@ architecture Behavioral of nx_data_receiver is signal timestamp_dt_error : std_logic; -- Data Stream DeltaT Error Counters - signal adc_dt_shift_reg : std_logic_vector(3 downto 0); - signal timestamp_dt_shift_reg : std_logic_vector(3 downto 0); - signal adc_dt_error_ctr : unsigned(11 downto 0); - signal timestamp_dt_error_ctr : unsigned(11 downto 0); + signal new_adc_dt_ctr : unsigned(3 downto 0); + signal new_timestamp_dt_ctr : unsigned(3 downto 0); + signal new_adc_dt_error_ctr : unsigned(11 downto 0); + signal new_timestamp_dt_error_ctr : unsigned(11 downto 0); signal adc_dt_error_p : std_logic; signal adc_dt_error_c100 : std_logic; signal timestamp_dt_error_p : std_logic; signal timestamp_dt_error_c100 : std_logic; - + ----------------------------------------------------------------------------- -- CLK Domain Transfer ----------------------------------------------------------------------------- + -- NX FIFO READ ENABLE + signal fifo_reset_i : std_logic; + signal fifo_write_enable : std_logic; + signal fifo_read_enable : std_logic; + signal fifo_empty : std_logic; + signal fifo_full : std_logic; + signal fifo_data_clk_tt : std_logic; + signal fifo_data_clk_t : std_logic; + signal fifo_data_clk : std_logic; + + signal fifo_data : std_logic_vector(43 downto 0); + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -218,6 +244,7 @@ architecture Behavioral of nx_data_receiver is signal reset_parity_error_ctr : std_logic; signal debug_mode : std_logic_vector(2 downto 0); signal reset_handler_start_r : std_logic; + signal adc_bit_shift : unsigned(3 downto 0); signal johnson_counter_sync_r : unsigned(1 downto 0); signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0); signal pll_adc_sample_clk_finedelb_r : unsigned(3 downto 0); @@ -228,8 +255,12 @@ architecture Behavioral of nx_data_receiver is signal nx_timestamp_delay_actr : unsigned(15 downto 0); signal nx_frame_word_delay_rr : unsigned(1 downto 0); signal nx_frame_word_delay_r : unsigned(1 downto 0); - signal adc_dt_error_ctr_r : unsigned(11 downto 0); - signal timestamp_dt_error_ctr_r : unsigned(11 downto 0); + signal fifo_full_rr : std_logic; + signal fifo_full_r : std_logic; + signal fifo_empty_rr : std_logic; + signal fifo_empty_r : std_logic; + signal new_adc_dt_error_ctr_r : unsigned(11 downto 0); + signal new_timestamp_dt_error_ctr_r : unsigned(11 downto 0); signal adc_notlock_ctr_r : unsigned(7 downto 0); signal merge_error_ctr_r : unsigned(11 downto 0); signal nx_frame_synced_rr : std_logic; @@ -240,6 +271,8 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + signal nx_online_ii : std_logic; + signal nx_online_i : std_logic; signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; @@ -248,15 +281,17 @@ architecture Behavioral of nx_data_receiver is signal rs_timeout_timer_done : std_logic; signal rs_timeout_timer_reset : std_logic; signal nx_timestamp_reset_o : std_logic; - signal nx_fifo_reset_handler : std_logic; + signal fifo_reset_handler : std_logic; type R_STATES is (R_IDLE, R_START, R_WAIT_0, - R_RESET_TIMESTAMP, + R_WAIT_NX_ONLINE, R_WAIT_1, - R_SET_ALL_RESETS, + R_RESET_TIMESTAMP, R_WAIT_2, + R_SET_ALL_RESETS, + R_WAIT_3, R_WAIT_NX_FRAME_RATE_OK, R_PLL_WAIT_LOCK, R_WAIT_ADC_OK, @@ -269,11 +304,17 @@ architecture Behavioral of nx_data_receiver is signal adc_reset_handler : std_logic; signal adc_reset_p : std_logic; signal output_handler_reset : std_logic; + signal disable_adc_f : std_logic; + signal disable_adc : std_logic; signal reset_handler_counter : unsigned(15 downto 0); signal reset_handler_busy : std_logic; signal reset_timeout_flag : std_logic; + + signal adc_reset_handler_cnx_ff : std_logic; + signal adc_reset_handler_cnx_f : std_logic; + signal adc_reset_handler_cnx : std_logic; -- Resync Counter Process signal resync_counter : unsigned(11 downto 0); signal resync_ctr_inc : std_logic; @@ -287,40 +328,74 @@ architecture Behavioral of nx_data_receiver is -- Reset Domain Transfers signal reset_nx_timestamp_clk_in_ff : std_logic; signal reset_nx_timestamp_clk_in_f : std_logic; - signal RESET_NX_TIMESTAMP_CLK_IN : std_logic; - - signal reset_nx_data_clk_in_ff : std_logic; - signal reset_nx_data_clk_in_f : std_logic; + signal RESET_NX_DATA_CLK_IN : std_logic; signal debug_state : std_logic_vector(3 downto 0); + signal debug_frame_on : std_logic; -- Keep FlipFlops, do not change to shift registers ----------- attribute syn_keep : boolean; - attribute syn_keep of nx_frame_word_f : signal is true; + attribute syn_keep of data_frame_f : signal is true; + attribute syn_keep of data_frame_clk_f : signal is true; attribute syn_keep of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_keep of reset_nx_timestamp_clk_in_f : signal is true; - attribute syn_keep of reset_nx_data_clk_in_ff : signal is true; - attribute syn_keep of reset_nx_data_clk_in_f : signal is true; + attribute syn_keep of adc_reset_handler_cnx_ff : signal is true; + attribute syn_keep of adc_reset_handler_cnx_f : signal is true; + + attribute syn_keep of nx_frame_clk_delayed_t : signal is true; + attribute syn_keep of nx_frame_word_delayed_t : signal is true; + + attribute syn_keep of nx_online_ii : signal is true; + attribute syn_keep of nx_online_i : signal is true; + + attribute syn_keep of disable_adc_f : signal is true; + attribute syn_keep of disable_adc : signal is true; + + attribute syn_keep of adc_debug_type_f : signal is true; + attribute syn_keep of adc_debug_type : signal is true; + + attribute syn_keep of nx_frame_word_delay_f : signal is true; + attribute syn_keep of nx_frame_word_delay : signal is true; + + attribute syn_keep of nx_frame_word_ff : signal is true; - attribute syn_keep of nx_timestamp_delay_f : signal is true; - attribute syn_keep of nx_timestamp_delay : signal is true; + --attribute syn_keep of nx_frame_word_delay_rr : signal is true; + --attribute syn_keep of nx_frame_word_delay_r : signal is true; attribute syn_preserve : boolean; - attribute syn_preserve of nx_frame_word_f : signal is true; + attribute syn_preserve of data_frame_f : signal is true; + attribute syn_preserve of data_frame_clk_f : signal is true; attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true; - attribute syn_preserve of reset_nx_data_clk_in_ff : signal is true; - attribute syn_preserve of reset_nx_data_clk_in_f : signal is true; + attribute syn_preserve of adc_reset_handler_cnx_ff : signal is true; + attribute syn_preserve of adc_reset_handler_cnx_f : signal is true; - attribute syn_preserve of nx_timestamp_delay_f : signal is true; - attribute syn_preserve of nx_timestamp_delay : signal is true; + attribute syn_preserve of nx_frame_clk_delayed_t : signal is true; + attribute syn_preserve of nx_frame_word_delayed_t : signal is true; + + attribute syn_preserve of nx_online_ii : signal is true; + attribute syn_preserve of nx_online_i : signal is true; + + attribute syn_preserve of disable_adc_f : signal is true; + attribute syn_preserve of disable_adc : signal is true; + + attribute syn_preserve of adc_debug_type_f : signal is true; + attribute syn_preserve of adc_debug_type : signal is true; + + attribute syn_preserve of nx_frame_word_delay_f : signal is true; + attribute syn_preserve of nx_frame_word_delay : signal is true; + + attribute syn_preserve of nx_frame_word_ff : signal is true; + + --attribute syn_preserve of nx_frame_word_delay_rr : signal is true; + --attribute syn_preserve of nx_frame_word_delay_r : signal is true; begin @@ -339,6 +414,10 @@ begin ADC_RESET_AD9228, nx_frame_clk, adc_reset_ctr, + fifo_write_enable, + fifo_empty, + fifo_read_enable, + nx_timestamp_delayed_clk, adc_data_s_clk, data_clk_o, nx_frame_synced, @@ -349,15 +428,15 @@ begin when "001" => -- Reset Handler DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= nx_frame_clk_c100; - DEBUG_OUT(2) <= adc_data_clk; + DEBUG_OUT(1) <= nx_frame_clk; + DEBUG_OUT(2) <= adc_data_clk_c100; --clk_skip; DEBUG_OUT(3) <= adc_sclk_ok; DEBUG_OUT(4) <= adc_reset_sync; DEBUG_OUT(5) <= adc_reset_handler; - DEBUG_OUT(6) <= nx_online; + DEBUG_OUT(6) <= ADC_RESET_AD9228; DEBUG_OUT(7) <= pll_adc_not_lock; - DEBUG_OUT(8) <= reset_after_offline; - DEBUG_OUT(9) <= nx_fifo_reset_handler; + DEBUG_OUT(8) <= reset_for_offline; + DEBUG_OUT(9) <= fifo_reset_handler; DEBUG_OUT(10) <= reset_handler_busy; DEBUG_OUT(11) <= pll_adc_sampling_clk_reset; DEBUG_OUT(15 downto 12) <= debug_state; @@ -371,12 +450,12 @@ begin DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(3 downto 1) <= debug_state(2 downto 0); DEBUG_OUT(4) <= reset_handler_busy; - DEBUG_OUT(5) <= '0'; + DEBUG_OUT(5) <= nx_frame_rate_offline; DEBUG_OUT(6) <= nx_frame_rate_error; DEBUG_OUT(7) <= pll_adc_not_lock; DEBUG_OUT(8) <= '0'; DEBUG_OUT(9) <= adc_frame_rate_error; - DEBUG_OUT(10) <= nx_fifo_reset_handler; + DEBUG_OUT(10) <= fifo_reset_handler; DEBUG_OUT(11) <= pll_adc_sampling_clk_reset; DEBUG_OUT(12) <= adc_reset_handler; DEBUG_OUT(13) <= output_handler_reset; @@ -388,57 +467,81 @@ begin DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= nx_frame_clk; - DEBUG_OUT(3) <= nx_data_clk; - DEBUG_OUT(4) <= adc_data_clk; + DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= nx_timestamp_delayed_clk; DEBUG_OUT(5) <= '0'; - DEBUG_OUT(6) <= adc_dt_error_p; - DEBUG_OUT(9 downto 7) <= merge_timing_ctr; - DEBUG_OUT(10) <= timestamp_dt_error_p; - DEBUG_OUT(11) <= merge_status_error; - DEBUG_OUT(12) <= merge_timing_error; - DEBUG_OUT(14 downto 13) <= merge_status; - DEBUG_OUT(15) <= data_clk_o; + DEBUG_OUT(6) <= adc_data_clk; + DEBUG_OUT(7) <= '0'; + DEBUG_OUT(8) <= fifo_write_enable; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(10) <= data_frame_clk; + DEBUG_OUT(11) <= '0'; + DEBUG_OUT(12) <= nx_frame_synced; + DEBUG_OUT(13) <= '0'; + DEBUG_OUT(14) <= frame_word_delay_change; + DEBUG_OUT(15) <= data_clk_o; when "101" => -- AD9228 Handler Debug output - DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(0) <= NX_DATA_CLK_IN; DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= nx_frame_clk; DEBUG_OUT(3) <= '0'; + DEBUG_OUT(4) <= nx_timestamp_delayed_clk; + DEBUG_OUT(5) <= merge_timeout_error; + DEBUG_OUT(6) <= adc_data_s_clk; + DEBUG_OUT(7) <= data_frame_clk; + DEBUG_OUT(9 downto 8) <= nx_frame_word_delay; + DEBUG_OUT(10) <= frame_word_delay_change; + DEBUG_OUT(11) <= frame_word_delay_set; + DEBUG_OUT(15 downto 12) <= adc_data_clk_last; + + when "110" => + DEBUG_OUT(0) <= NX_DATA_CLK_IN; + DEBUG_OUT(1) <= '0'; + DEBUG_OUT(2) <= '0'; + DEBUG_OUT(3) <= '0'; DEBUG_OUT(4) <= '0'; - DEBUG_OUT(5) <= merge_timing_error; + DEBUG_OUT(5) <= debug_frame_on; DEBUG_OUT(6) <= '0'; DEBUG_OUT(7) <= '0'; - DEBUG_OUT(9 downto 8) <= (others => '0'); - DEBUG_OUT(10) <= '0'; + DEBUG_OUT(8) <= '0'; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(10) <= adc_sampling_clk; DEBUG_OUT(11) <= '0'; - DEBUG_OUT(15 downto 12) <= (others => '0'); - - when "110" => - DEBUG_OUT(0) <= nx_frame_clk_s; --data_clk_o; - DEBUG_OUT(15 downto 1) <= nx_frame_word_s(14 downto 0); --data_m(14 downto 0); + DEBUG_OUT(12) <= '0'; + DEBUG_OUT(13) <= '0'; + DEBUG_OUT(14) <= '0'; + DEBUG_OUT(15) <= ADC_SAMPLE_CLK_OUT; when "111" => - DEBUG_OUT(0) <= nx_data_clk; - DEBUG_OUT(15 downto 1) <= nx_data(14 downto 0); + DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(1) <= NX_DATA_CLK_IN; + DEBUG_OUT(2) <= data_frame_clk; + DEBUG_OUT(3) <= fifo_fw_reset_i; + DEBUG_OUT(4) <= fifo_fw_full; + DEBUG_OUT(5) <= fifo_fw_write_enable; + DEBUG_OUT(6) <= fifo_fw_empty; + DEBUG_OUT(7) <= fifo_fw_read_enable; + DEBUG_OUT(15 downto 8) <= nx_frame_word_f; when others => -- Default DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= TRIGGER_IN; - DEBUG_OUT(2) <= data_clk_o; - DEBUG_OUT(3) <= nx_fifo_reset_handler; - DEBUG_OUT(4) <= '0'; - DEBUG_OUT(5) <= '0'; - DEBUG_OUT(6) <= '0'; - DEBUG_OUT(7) <= '0'; - DEBUG_OUT(8) <= '0'; + DEBUG_OUT(2) <= data_frame_clk; + DEBUG_OUT(3) <= fifo_reset_handler; + DEBUG_OUT(4) <= fifo_full; + DEBUG_OUT(5) <= fifo_write_enable; + DEBUG_OUT(6) <= fifo_empty; + DEBUG_OUT(7) <= fifo_read_enable; + DEBUG_OUT(8) <= fifo_data_clk; DEBUG_OUT(9) <= nx_frame_clk; - DEBUG_OUT(10) <= '0'; + DEBUG_OUT(10) <= nx_timestamp_delayed_clk; DEBUG_OUT(11) <= adc_data_s_clk; DEBUG_OUT(12) <= data_clk_o; DEBUG_OUT(13) <= parity_error_c100; - DEBUG_OUT(14) <= merge_timing_error; + DEBUG_OUT(14) <= merge_timeout_error; DEBUG_OUT(15) <= nx_frame_synced; end case; @@ -451,12 +554,12 @@ begin -- Reset Domain Transfer ----------------------------------------------------------------------------- reset_nx_timestamp_clk_in_ff <= RESET_IN - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); reset_nx_timestamp_clk_in_f <= reset_nx_timestamp_clk_in_ff - when rising_edge(NX_TIMESTAMP_CLK_IN); - RESET_NX_TIMESTAMP_CLK_IN <= reset_nx_timestamp_clk_in_f - when rising_edge(NX_TIMESTAMP_CLK_IN); - + when rising_edge(NX_DATA_CLK_IN); + RESET_NX_DATA_CLK_IN <= reset_nx_timestamp_clk_in_f + when rising_edge(NX_DATA_CLK_IN); + ----------------------------------------------------------------------------- -- PLL Handler ----------------------------------------------------------------------------- @@ -490,24 +593,69 @@ begin LOCK => pll_adc_sampling_clk_lock ); + signal_async_trans_2: signal_async_trans + port map ( + CLK_IN => CLK_IN, + SIGNAL_A_IN => not pll_adc_sampling_clk_lock, + SIGNAL_OUT => pll_adc_not_lock + ); + PROC_PLL_LOCK_COUNTER: process(CLK_IN) begin if (rising_edge(CLK_IN)) then if( RESET_IN = '1' or pll_adc_not_lock_ctr_clear = '1') then - pll_adc_not_lock_shift <= (others => '0'); - pll_adc_not_lock_ctr <= (others => '0'); + pll_adc_not_lock_f <= (others => '0'); + pll_adc_not_lock_ctr <= (others => '0'); else - pll_adc_not_lock_shift(0) <= pll_adc_not_lock; - pll_adc_not_lock_shift(1) <= pll_adc_not_lock_shift(0); + pll_adc_not_lock_f(0) <= pll_adc_not_lock; + pll_adc_not_lock_f(1) <= pll_adc_not_lock_f(0); - if (pll_adc_not_lock_shift = "01") then - pll_adc_not_lock_ctr <= pll_adc_not_lock_ctr + 1; + if (pll_adc_not_lock_f = "01") then + pll_adc_not_lock_ctr <= pll_adc_not_lock_ctr + 1; end if; end if; end if; end process PROC_PLL_LOCK_COUNTER; + pulse_dtrans_adc_data_clk: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_data_clk, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_data_clk_c100 + ); + pulse_dtrans_nx_frame_clk: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => nx_frame_clk, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => nx_frame_clk_c100 + ); + + pulse_dtrans_parity_error: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => parity_error_b, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => parity_error_c100 + ); + timer_static_RESET_TIMER: timer_static generic map ( CTR_WIDTH => 20, @@ -532,14 +680,33 @@ begin TIMER_DONE_OUT => rs_timeout_timer_done ); + pulse_dtrans_1: pulse_dtrans + generic map ( + CLK_RATIO => 4 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_reset_sync_s, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_reset_sync + ); + + signal_async_trans_ADC_LOCKED: signal_async_trans + port map ( + CLK_IN => CLK_IN, + SIGNAL_A_IN => adc_locked, + SIGNAL_OUT => adc_locked_c100 + ); ----------------------------------------------------------------------------- -- ADC Sampling Clock Generator using a Johnson Counter ----------------------------------------------------------------------------- - PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then if (adc_sclk_skip = '0') then johnson_ff_0 <= not johnson_ff_1; johnson_ff_1 <= johnson_ff_0; @@ -550,34 +717,28 @@ begin -- Adjust johnson_counter_sync to show optimal value at 0 - PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_SAMPLING_CLK_SYNC: process(NX_DATA_CLK_IN) variable adc_sclk_state : std_logic_vector(1 downto 0); begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - johnson_counter_sync <= (others => '0'); - adc_sclk_skip <= '0'; - adc_sclk_ok <= '0'; - else - johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r); - adc_sclk_state := johnson_ff_1 & johnson_ff_0; - adc_sclk_skip <= '0'; - if (nx_frame_clk = '1') then - if (adc_sclk_state /= johnson_counter_sync) then - adc_sclk_skip <= '1'; - adc_sclk_ok <= '0'; - else - adc_sclk_ok <= '1'; - end if; + if (rising_edge(NX_DATA_CLK_IN)) then + johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r); + adc_sclk_state := johnson_ff_1 & johnson_ff_0; + adc_sclk_skip <= '0'; + if (nx_frame_clk = '1') then + if (adc_sclk_state /= johnson_counter_sync) then + adc_sclk_skip <= '1'; + adc_sclk_ok <= '0'; + else + adc_sclk_ok <= '1'; end if; end if; end if; end process PROC_ADC_SAMPLING_CLK_SYNC; - PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_RESET: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then adc_sclk_ok_last <= '0'; adc_reset_sync_s <= '0'; else @@ -607,51 +768,106 @@ begin -- NX Timestamp Handler ----------------------------------------------------------------------------- - -- First: Use three Input FIFO to relax Timing - nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_TIMESTAMP_CLK_IN); - - -- Second: Merge TS Data 8bit to 32Bit Timestamp Frame - PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + -- First: use two FFs for NX_TIMESTAMP_IN + nx_frame_word_fff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); + nx_frame_word_ff <= nx_frame_word_fff when rising_edge(NX_TIMESTAMP_CLK_IN); + + -- Second: Clock Domain Transfer to NX_DATA_CLK_IN + fifo_nx_frame_8to8_dc_1: entity work.fifo_nx_frame_8to8_dc + port map ( + Data => nx_frame_word_ff, + WrClock => NX_TIMESTAMP_CLK_IN, + RdClock => NX_DATA_CLK_IN, + WrEn => fifo_fw_write_enable, + RdEn => fifo_fw_read_enable, + Reset => fifo_fw_reset_i, + RPReset => fifo_fw_reset_i, + Q => nx_frame_word_f, + Empty => fifo_fw_empty, + Full => fifo_fw_full + ); + fifo_fw_reset_i <= RESET_NX_DATA_CLK_IN; + fifo_fw_write_enable <= '1'; --not fifo_fw_full; + fifo_fw_read_enable <= '1'; --not fifo_fw_empty; + + -- Third: delay NX_TIMESTAMP_IN relatively to ADC Clock + dynamic_shift_register8x64_1: entity work.dynamic_shift_register8x64 + port map ( + Din => nx_frame_word_f, + Addr => nx_shift_register_delay, + Clock => NX_DATA_CLK_IN, + ClockEn => '1', + Reset => RESET_NX_DATA_CLK_IN, + Q => nx_frame_word_s + ); + + -- Timestamp Input Delay relative to ADC + PROC_NX_SHIFT_REGISTER_DELAY: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then - nx_frame_word_t <= (others => '0'); - nx_frame_word <= (others => '0'); - nx_frame_clk_t <= '0'; - nx_frame_clk <= '0'; + if (rising_edge(NX_DATA_CLK_IN)) then + nx_timestamp_delay_f <= nx_timestamp_delay_s; + if( RESET_NX_DATA_CLK_IN = '1' ) then + nx_timestamp_delay <= "010"; + nx_shift_register_delay <= "011011"; -- 27 else - case frame_byte_pos is - when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; - - when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; + nx_timestamp_delay <= nx_timestamp_delay_f; - when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_f; - nx_frame_clk_t <= '0'; + case nx_timestamp_delay is + when "000" => + nx_shift_register_delay <= "011011"; -- 27 + + when "001" => + nx_shift_register_delay <= "011111"; -- 31 + + when "010" => + nx_shift_register_delay <= "100011"; -- 35 + + when "011" => + nx_shift_register_delay <= "100111"; -- 39 + + when "100" => + nx_shift_register_delay <= "101011"; -- 43 - when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_f; - nx_frame_clk_t <= '1'; + when others => null; end case; + end if; + end if; + end process PROC_NX_SHIFT_REGISTER_DELAY; - -- Output Frame - if (nx_frame_clk_t = '1') then - nx_frame_word <= nx_frame_word_t; - nx_frame_clk <= '1'; - else - nx_frame_word <= x"0000_0001"; - nx_frame_clk <= '0'; - end if; + -- Merge TS Data 8bit to 32Bit Timestamp Frame + PROC_8_TO_32_BIT: process(NX_DATA_CLK_IN) + begin + if (rising_edge(NX_DATA_CLK_IN)) then + case frame_byte_pos is + when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_s; + nx_frame_clk_t <= '0'; + + when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_s; + nx_frame_clk_t <= '1'; + end case; + + -- Output Frame + if (nx_frame_clk_t = '1') then + nx_frame_word <= nx_frame_word_t; + nx_frame_clk <= '1'; + else + nx_frame_word <= x"0000_0001"; + nx_frame_clk <= '0'; end if; end if; end process PROC_8_TO_32_BIT; -- TS Frame Sync process - PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) + PROC_SYNC_TO_NX_FRAME: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if( RESET_NX_DATA_CLK_IN = '1' ) then frame_byte_pos <= "11"; rs_sync_set <= '0'; rs_sync_reset <= '0'; @@ -687,10 +903,10 @@ begin end process PROC_SYNC_TO_NX_FRAME; -- RS FlipFlop to hold Sync Status - PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) + PROC_RS_FRAME_SYNCED: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then nx_frame_synced <= '0'; else if (rs_sync_reset = '1') then @@ -703,12 +919,12 @@ begin end process PROC_RS_FRAME_SYNCED; -- Check Parity Bit - PROC_PARITY_CHECKER: process(NX_TIMESTAMP_CLK_IN) + PROC_PARITY_CHECKER: process(NX_DATA_CLK_IN) variable parity_bits : std_logic_vector(22 downto 0); variable parity : std_logic; begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then parity_error_b <= '0'; else if (nx_frame_clk = '1') then @@ -732,127 +948,105 @@ begin end if; end process PROC_PARITY_CHECKER; - -- Delay NX Data relative to ADC Data - dynamic_shift_register33x64_1: entity work.dynamic_shift_register33x64 - port map ( - Din(31 downto 0) => nx_frame_word, - Din(32) => nx_frame_clk, - Addr => nx_shift_register_delay, - Clock => NX_TIMESTAMP_CLK_IN, - ClockEn => '1', - Reset => RESET_NX_TIMESTAMP_CLK_IN, - Q(31 downto 0) => nx_frame_word_s, - Q(32) => nx_frame_clk_s - ); - - -- Timestamp Input Delay relative to ADC - nx_timestamp_delay_f <= nx_timestamp_delay_s - when rising_edge(NX_TIMESTAMP_CLK_IN); - nx_timestamp_delay <= nx_timestamp_delay_f - when rising_edge(NX_TIMESTAMP_CLK_IN); - PROC_NX_SHIFT_REGISTER_DELAY: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if(RESET_NX_TIMESTAMP_CLK_IN = '1') then - nx_shift_register_delay <= (others => '0'); - else - case nx_timestamp_delay is - when "000" => - nx_shift_register_delay <= "001111"; -- 15 - - when "001" => - nx_shift_register_delay <= "010011"; -- 19 - - when "010" => - nx_shift_register_delay <= "010111"; -- 23 - - when "011" => - nx_shift_register_delay <= "011011"; -- 27 - - when "100" => - nx_shift_register_delay <= "011111"; -- 31 - - when "101" => - nx_shift_register_delay <= "100011"; -- 35 - - when "110" => - nx_shift_register_delay <= "100111"; -- 39 - - when "111" => - nx_shift_register_delay <= "101011"; -- 43 - - end case; - end if; - end if; - end process PROC_NX_SHIFT_REGISTER_DELAY; - ----------------------------------------------------------------------------- - -- Clock Domain Transfer Nxyter Data Stream + -- Delay NX Timestamp relative to ADC Frames ----------------------------------------------------------------------------- - - fifo_nxyter_32to32_dc_1: entity work.fifo_nxyter_32to32_dc - port map ( - Data => nx_frame_word_s, - WrClock => NX_TIMESTAMP_CLK_IN, - RdClock => CLK_IN, - WrEn => fifo_nx_write_enable, - RdEn => fifo_nx_read_enable, - Reset => fifo_nx_reset_i, - RPReset => fifo_nx_reset_i, - Q => fifo_nx_data, - Empty => fifo_nx_empty, - Full => fifo_nx_full - ); - - fifo_nx_reset_i <= RESET_IN or nx_fifo_reset_handler; - fifo_nx_write_enable <= not fifo_nx_full and nx_frame_clk_s; - fifo_nx_read_enable <= not fifo_nx_empty; - - PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) + PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_DATA_CLK_IN) begin - if (rising_edge(CLK_IN)) then - fifo_nx_data_clk_tt <= fifo_nx_read_enable; - if(RESET_IN = '1') then - fifo_nx_data_clk_t <= '0'; - fifo_nx_data_clk <= '0'; - else - -- Delay read signal by two Clock Cycles - fifo_nx_data_clk_t <= fifo_nx_data_clk_tt; - fifo_nx_data_clk <= fifo_nx_data_clk_t; - end if; + if (rising_edge(NX_DATA_CLK_IN)) then + nx_frame_word_delayed_t(0) <= nx_frame_word; + nx_frame_clk_delayed_t(0) <= nx_frame_clk; + + -- Delay Pipeline NX Clock + for X in 1 to 3 loop + nx_frame_word_delayed_t(X) <= nx_frame_word_delayed_t(X - 1); + nx_frame_clk_delayed_t(X) <= nx_frame_clk_delayed_t(X - 1); + end loop; + + -- Output + nx_timestamp_delayed_clk <= + nx_frame_clk_delayed_t(to_integer(nx_frame_word_delay)); + nx_timestamp_delayed <= + nx_frame_word_delayed_t(to_integer(nx_frame_word_delay)); end if; - end process PROC_NX_FIFO_READ_ENABLE; - - PROC_NX_FIFO_READ_HANDLER: process(CLK_IN) + end process PROC_NX_TIMESTAMP_FRAME_DELAY; + + PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_DATA_CLK_IN) begin - if (rising_edge(CLK_IN)) then - if(RESET_IN = '1') then - nx_data <= (others => '0'); - nx_data_clk <= '0'; + if (rising_edge(NX_DATA_CLK_IN)) then + nx_frame_word_delay <= nx_frame_word_delay_f; + adc_data_clk_last(0) <= adc_data_s_clk; + + if (RESET_NX_DATA_CLK_IN = '1') then + nx_frame_word_delay_f <= "10"; + adc_data_clk_last(3 downto 1) <= (others => '0'); + frame_word_delay_change <= '0'; + frame_word_delay_set <= '0'; else - if (fifo_nx_data_clk = '1') then - nx_data <= fifo_nx_data; - nx_data_clk <= '1'; + for I in 1 to 3 loop + adc_data_clk_last(I) <= adc_data_clk_last(I - 1); + end loop; + frame_word_delay_change <= '0'; + frame_word_delay_set <= '0'; + + if (disable_adc = '1') then + nx_frame_word_delay_f <= "10"; + frame_word_delay_set <= '1'; else - nx_data <= (others => '0'); - nx_data_clk <= '0'; + if (nx_timestamp_delayed_clk = '1') then + case adc_data_clk_last is + when "0100" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 1; + frame_word_delay_change <= '1'; + + when "0010" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 2; + frame_word_delay_change <= '1'; + + when "0001" => + nx_frame_word_delay_f <= nx_frame_word_delay_f + 3; + frame_word_delay_change <= '1'; + + when others => + null; + + end case; + + if (adc_data_s_clk = '1') then + frame_word_delay_set <= '1'; + end if; + end if; end if; end if; end if; - end process PROC_NX_FIFO_READ_HANDLER; + end process PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP; ----------------------------------------------------------------------------- -- ADC Input Handler ----------------------------------------------------------------------------- - ADC_RESET_AD9228 <= RESET_IN or adc_reset_handler; + adc_reset_handler_cnx_ff <= adc_reset_handler + when rising_edge(NX_DATA_CLK_IN); + adc_reset_handler_cnx_f <= adc_reset_handler_cnx_ff + when rising_edge(NX_DATA_CLK_IN); + adc_reset_handler_cnx <= adc_reset_handler_cnx_f + when rising_edge(NX_DATA_CLK_IN); + + ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or + adc_reset_handler_cnx; + + + adc_debug_type_f <= adc_debug_type_r + when rising_edge(NX_DATA_CLK_IN); + adc_debug_type <= adc_debug_type_f + when rising_edge(NX_DATA_CLK_IN); adc_ad9228_1: adc_ad9228 generic map ( DEBUG_ENABLE => false ) port map ( - CLK_IN => CLK_IN, + CLK_IN => NX_DATA_CLK_IN, RESET_IN => ADC_RESET_AD9228, CLK_ADCDAT_IN => ADC_CLK_DAT_IN, @@ -889,178 +1083,154 @@ begin ADC0_LOCKED_OUT => adc_locked, ADC1_LOCKED_OUT => open, - DEBUG_IN => adc_debug_type_r, + DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG ); + PROC_ADC_DATA_BIT_SHIFT: process(NX_DATA_CLK_IN) + variable adcval : unsigned(11 downto 0) := (others => '0'); + begin + if (rising_edge(NX_DATA_CLK_IN)) then + if (adc_bit_shift(3) = '1') then + adcval := unsigned(adc_data) rol + to_integer(adc_bit_shift(2 downto 0)); + else + adcval := unsigned(adc_data) ror + to_integer(adc_bit_shift(2 downto 0)); + end if; + + if (adc_data_clk = '1') then + adc_data_s <= std_logic_vector(adcval); + adc_data_s_clk <= '1'; + else + adc_data_s <= x"aff"; + adc_data_s_clk <= '0'; + end if; + end if; + end process PROC_ADC_DATA_BIT_SHIFT; + ----------------------------------------------------------------------------- -- Merge Data Streams Timestamps and ADC Value ----------------------------------------------------------------------------- - - merge_handler_reset <= merge_status_error or - merge_timing_error or - output_handler_reset; - - PROC_DATA_MERGE_HANDLER: process(CLK_IN) - variable status : std_logic_vector(3 downto 0); + merge_handler_reset_i <= output_handler_reset + when rising_edge(NX_DATA_CLK_IN); + merge_handler_reset <= merge_handler_reset_i + when rising_edge(NX_DATA_CLK_IN); + disable_adc_f <= disable_adc_r when rising_edge(NX_DATA_CLK_IN); + disable_adc <= disable_adc_f when rising_edge(NX_DATA_CLK_IN); + + PROC_DATA_MERGE_HANDLER: process(NX_DATA_CLK_IN) begin - if (rising_edge(CLK_IN)) then - if (RESET_IN = '1' or merge_handler_reset = '1') then - merge_status <= (others => '0'); - data_m <= (others => '0'); - data_clk_m <= '0'; - - merge_status_error <= '0'; - merge_timing_ctr <= (others => '0'); - merge_timing_error <= '0'; + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1' or merge_handler_reset = '1') then + merge_timeout_ctr <= (others => '0'); + merge_timeout_error <= '0'; + merge_error_ctr <= (others => '0'); else - merge_status_error <= '0'; - merge_timing_error <= '0'; - data_clk_m <= '0'; - - if (disable_adc_r = '0') then - status := adc_data_clk & nx_data_clk & merge_status; + if (nx_timestamp_delayed_clk = '1' and + (adc_data_s_clk = '1' or disable_adc = '1') + ) then + data_frame(31 downto 0) <= nx_timestamp_delayed; + if (disable_adc = '0') then + data_frame(43 downto 32) <= adc_data_s; + else + data_frame(43 downto 32) <= x"000"; + end if; + data_frame_clk <= '1'; + merge_timeout_ctr <= (others => '0'); else - status := '0' & nx_data_clk & '1' & merge_status(0); + data_frame <= (others => '0'); + data_frame_clk <= '0'; + merge_timeout_ctr <= merge_timeout_ctr + 1; end if; - - case status is - when "0100" => - data_m(31 downto 0) <= nx_data; - data_m(43 downto 32) <= (others => '0'); - merge_status <= "01"; - - when "0110" => - data_m(31 downto 0) <= nx_data; - merge_status <= "00"; - data_clk_m <= '1'; - - when "1000" => - data_m(31 downto 0) <= (others => '0'); - data_m(43 downto 32) <= adc_data; - merge_status <= "10"; - - when "1001" => - data_m(43 downto 32) <= adc_data; - data_clk_m <= '1'; - merge_status <= "00"; - - when "1100" => - data_m(31 downto 0) <= nx_data; - data_m(43 downto 32) <= adc_data; - data_clk_m <= '1'; - merge_status <= "00"; - - when "0000" | - "0001" | - "0010" => - null; - - when others => - data_m <= (others => '0'); - merge_status <= (others => '0'); - merge_status_error <= '1'; - - end case; - -- Check Timing - if (data_clk_m = '1') then - if (merge_timing_ctr < x"2" or merge_timing_ctr > x"3") then - merge_timing_error <= '1'; - else - merge_timing_ctr <= (others => '0'); - end if; + -- Timeout? + if (merge_timeout_ctr > x"3") then + merge_timeout_error <= '1'; + merge_error_ctr <= merge_error_ctr + 1; else - if (merge_timing_ctr >= x"3") then - merge_timing_error <= '1'; - end if; - merge_timing_ctr <= merge_timing_ctr + 1; + merge_timeout_error <= '0'; end if; - end if; end if; end process PROC_DATA_MERGE_HANDLER; ----------------------------------------------------------------------------- - -- Signal Domain Transfers + -- Clock Domain Transfer Data Stream ----------------------------------------------------------------------------- - signal_async_trans_2: signal_async_trans - port map ( - CLK_IN => CLK_IN, - SIGNAL_A_IN => not pll_adc_sampling_clk_lock, - SIGNAL_OUT => pll_adc_not_lock - ); - pulse_dtrans_nx_frame_clk: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, - PULSE_A_IN => nx_frame_clk, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => nx_frame_clk_c100 - ); + -- Relax Timing by FF + data_frame_f <= data_frame when rising_edge(NX_DATA_CLK_IN); + data_frame_clk_f <= data_frame_clk when rising_edge(NX_DATA_CLK_IN); - pulse_dtrans_parity_error: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) + fifo_data_stream_44to44_dc_1: fifo_data_stream_44to44_dc port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, - PULSE_A_IN => parity_error_b, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => parity_error_c100 - ); - pulse_dtrans_1: pulse_dtrans - generic map ( - CLK_RATIO => 4 - ) - port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, - PULSE_A_IN => adc_reset_sync_s, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => adc_reset_sync - ); + Data => data_frame_f, + WrClock => NX_DATA_CLK_IN, + RdClock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => RESET_NX_DATA_CLK_IN, --fifo_reset_i, + RPReset => fifo_reset_i, + Q => fifo_data, + Empty => fifo_empty, + Full => fifo_full + ); + fifo_reset_i <= RESET_IN or fifo_reset_handler; + fifo_write_enable <= not fifo_full and data_frame_clk_f; + fifo_read_enable <= not fifo_empty; + + PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + fifo_data_clk_tt <= fifo_read_enable; + if(RESET_IN = '1') then + fifo_data_clk_t <= '0'; + fifo_data_clk <= '0'; + else + -- Delay read signal by two Clock Cycles + fifo_data_clk_t <= fifo_data_clk_tt; + fifo_data_clk <= fifo_data_clk_t; + end if; + end if; + end process PROC_NX_FIFO_READ_ENABLE; - signal_async_trans_ADC_SCLK_OK: signal_async_trans - port map ( - CLK_IN => CLK_IN, - SIGNAL_A_IN => adc_sclk_ok, - SIGNAL_OUT => adc_sclk_ok_c100 - ); + PROC_DATA_OUTPUT_HANDLER: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if(RESET_IN = '1') then + data_o <= (others => '0'); + data_clk_o <= '0'; + else + if (fifo_data_clk = '1') then + data_o <= fifo_data; + data_clk_o <= '1'; + else + data_o <= (others => '0'); + data_clk_o <= '0'; + end if; + end if; + end if; + end process PROC_DATA_OUTPUT_HANDLER; + ----------------------------------------------------------------------------- + -- Status Counters + ----------------------------------------------------------------------------- + + -- Domain Transfers pulse_dtrans_2: pulse_dtrans generic map ( CLK_RATIO => 3 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => rs_sync_reset, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, PULSE_B_OUT => resync_ctr_inc ); - ----------------------------------------------------------------------------- - -- Status Counters - ----------------------------------------------------------------------------- - - level_to_pulse_ADC_NOTLOCKED: level_to_pulse - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - LEVEL_IN => not adc_locked, - PULSE_OUT => adc_notlocked_p - ); - -- Counters PROC_RESYNC_COUNTER: process(CLK_IN) begin @@ -1088,19 +1258,7 @@ begin end if; end process PROC_PARITY_ERROR_COUNTER; - PROC_MERGE_ERROR_COUNTER: process(CLK_IN) - begin - if (rising_edge(CLK_IN)) then - if (RESET_IN = '1') then - merge_error_ctr <= (others => '0'); - else - if (merge_status_error = '1' or merge_timing_error = '1') then - merge_error_ctr <= merge_error_ctr + 1; - end if; - end if; - end if; - end process PROC_MERGE_ERROR_COUNTER; - + ----------------------------------------------------------------------------- -- Rate Counters + Rate Error Check ----------------------------------------------------------------------------- @@ -1126,7 +1284,7 @@ begin nx_frame_rate_ctr <= nx_frame_rate_ctr + 1; end if; - if (adc_data_clk = '1') then + if (adc_data_clk_c100 = '1') then adc_frame_rate_ctr <= adc_frame_rate_ctr + 1; end if; @@ -1148,7 +1306,7 @@ begin nx_frame_rate_ctr(0) <= nx_frame_clk_c100; adc_frame_rate_ctr(27 downto 1) <= (others => '0'); - adc_frame_rate_ctr(0) <= adc_data_clk; + adc_frame_rate_ctr(0) <= adc_data_clk_c100; frame_rate_ctr(27 downto 1) <= (others => '0'); frame_rate_ctr(0) <= data_clk_o; @@ -1156,7 +1314,6 @@ begin parity_err_rate_ctr(27 downto 1) <= (others => '0'); parity_err_rate_ctr(0) <= parity_error_c100; end if; - end if; end if; end process PROC_RATE_COUNTER; @@ -1166,11 +1323,21 @@ begin begin if (rising_edge(CLK_IN)) then if (RESET_IN = '1') then + nx_frame_rate_offline <= '1'; + nx_frame_rate_offline_last <= '1'; nx_frame_rate_error <= '0'; adc_frame_rate_error <= '0'; frame_rate_error <= '0'; parity_rate_error <= '0'; + reset_for_offline <= '0'; else + if (nx_frame_rate < 2) then + -- Assuming nxyter not online or does not receive clock + nx_frame_rate_offline <= '1'; + else + nx_frame_rate_offline <= '0'; + end if; + if ((nx_frame_rate < x"1dc_d642" or nx_frame_rate > x"1dc_d652")) then nx_frame_rate_error <= '1'; @@ -1197,15 +1364,46 @@ begin else parity_rate_error <= '0'; end if; + + -- Reset Request to Reset Handler + nx_frame_rate_offline_last <= nx_frame_rate_offline; + if (nx_frame_rate_offline_last = '1' and + nx_frame_rate_offline = '0') then + reset_for_offline <= '1'; + else + reset_for_offline <= '0'; + end if; end if; end if; end process PROC_RATE_ERRORS; ----------------------------------------------------------------------------- - - adc_dt_error_c100 <= adc_dt_error_p; - timestamp_dt_error_c100 <= timestamp_dt_error_p; - + pulse_dtrans_ADC_DT_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_dt_error_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_dt_error_c100 + ); + + pulse_dtrans_TIMESTAMP_DT_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => timestamp_dt_error_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => timestamp_dt_error_c100 + ); + PROC_EVENT_ERRORS_PER_SECOND: process(CLK_IN) begin if (rising_edge(CLK_IN)) then @@ -1232,47 +1430,40 @@ begin end if; end process PROC_EVENT_ERRORS_PER_SECOND; - PROC_DATA_STREAM_DELTA_T: process(CLK_IN) + PROC_DATA_STREAM_DELTA_T: process(NX_DATA_CLK_IN) begin - if (rising_edge(CLK_IN)) then - if (RESET_IN = '1') then - adc_dt_shift_reg <= (others => '0'); - timestamp_dt_shift_reg <= (others => '0'); - adc_dt_error_ctr <= (others => '0'); - timestamp_dt_error_ctr <= (others => '0'); + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then + new_adc_dt_ctr <= (others => '0'); + new_timestamp_dt_ctr <= (others => '0'); + new_adc_dt_error_ctr <= (others => '0'); + new_timestamp_dt_error_ctr <= (others => '0'); else - - -- ADC - adc_dt_shift_reg(0) <= adc_data_clk; - adc_dt_shift_reg(3 downto 1) <= adc_dt_shift_reg(2 downto 0); + adc_dt_error_p <= '0'; + timestamp_dt_error_p <= '0'; - case adc_dt_shift_reg is - when "1000" | "0100" | "0010" | "0001" | - "1001" | "0011" | "0110" | "1100" => - adc_dt_error_p <= '0'; - - when others => - adc_dt_error_ctr <= adc_dt_error_ctr + 1; - adc_dt_error_p <= '1'; - - end case; + -- ADC + if (adc_data_clk = '1') then + if (new_adc_dt_ctr /= x"3" ) then + new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1; + adc_dt_error_p <= '1'; + end if; + new_adc_dt_ctr <= (others => '0'); + else + new_adc_dt_ctr <= new_adc_dt_ctr + 1; + end if; -- TimeStamp - timestamp_dt_shift_reg(0) <= nx_data_clk; - timestamp_dt_shift_reg(3 downto 1) - <= timestamp_dt_shift_reg(2 downto 0); + if (nx_frame_clk = '1') then + if (new_timestamp_dt_ctr /= x"3") then + new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1; + timestamp_dt_error_p <= '1'; + end if; + new_timestamp_dt_ctr <= (others => '0'); + else + new_timestamp_dt_ctr <= new_timestamp_dt_ctr + 1; + end if; - case timestamp_dt_shift_reg is - when "1000" | "0100" | "0010" | "0001" | - "1001" | "0011" | "0110" | "1100" => - timestamp_dt_error_p <= '0'; - - when others => - timestamp_dt_error_ctr <= timestamp_dt_error_ctr + 1; - timestamp_dt_error_p <= '1'; - - end case; - end if; end if; end process PROC_DATA_STREAM_DELTA_T; @@ -1281,12 +1472,15 @@ begin -- Reset Handler ----------------------------------------------------------------------------- + nx_online_ii <= NX_ONLINE_IN when rising_edge(CLK_IN); + nx_online_i <= nx_online_ii when rising_edge(CLK_IN); + PROC_RESET_HANDLER: process(CLK_IN) begin if (rising_edge(CLK_IN)) then if( RESET_IN = '1' ) then frame_rates_reset <= '0'; - nx_fifo_reset_handler <= '0'; + fifo_reset_handler <= '0'; pll_adc_sampling_clk_reset <= '0'; adc_reset_p <= '0'; adc_reset_handler <= '0'; @@ -1303,7 +1497,7 @@ begin R_STATE <= R_IDLE; else frame_rates_reset <= '0'; - nx_fifo_reset_handler <= '0'; + fifo_reset_handler <= '0'; pll_adc_sampling_clk_reset <= '0'; adc_reset_p <= '0'; adc_reset_handler <= '0'; @@ -1317,15 +1511,9 @@ begin debug_state <= x"0"; - if (nx_online = '0') then - -- If Nxyter is 0ffline nothing will happen - rs_timeout_timer_reset <= '1'; - reset_timeout_flag <= '0'; - R_STATE <= R_IDLE; - elsif (reset_handler_start_r = '1') then + if (reset_handler_start_r = '1') then -- Reset by register always wins, start it rs_timeout_timer_reset <= '1'; - reset_timeout_flag <= '0'; R_STATE <= R_START; elsif (rs_timeout_timer_done = '1') then -- Reset Timeout, retry RESET @@ -1336,26 +1524,24 @@ begin case R_STATE is when R_IDLE => - if (nx_online = '1') then + if (NX_CLOCK_ON_IN = '1') then if ((disable_adc_r = '0' and (pll_adc_not_lock = '1' or adc_reset_sync = '1' or adc_frame_rate_error = '1' or + pll_adc_not_lock = '1' or adc_dt_error = '1' or adc_sclk_ok_c100 = '0' or - adc_locked = '0' + adc_locked_c100 = '0' ) ) or - ( - nx_frame_rate_error = '1' or - timestamp_dt_error = '1' or - parity_rate_error = '1' or - nx_frame_rate_error = '1' or - reset_after_offline = '1' or - startup_reset = '1' - ) + nx_frame_rate_error = '1' or + startup_reset = '1' or + timestamp_dt_error = '1' or + parity_rate_error = '1' or + nx_frame_rate_error = '1' ) then - R_STATE <= R_START; + R_STATE <= R_IDLE; --R_RESET_TIMESTAMP; else reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; @@ -1365,12 +1551,10 @@ begin else reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; - reset_handler_busy <= '0'; R_STATE <= R_IDLE; end if; - debug_state <= x"1"; - + when R_START => -- First wait 1mue for NX_MAIN_CLK, have to put lock status here -- to check in the future. @@ -1382,9 +1566,27 @@ begin if (rs_wait_timer_done = '0') then R_STATE <= R_WAIT_0; else - R_STATE <= R_RESET_TIMESTAMP ; + R_STATE <= R_WAIT_NX_ONLINE; end if; debug_state <= x"3"; + + when R_WAIT_NX_ONLINE => + if (nx_online_i = '0') then + R_STATE <= R_WAIT_NX_ONLINE; + else + -- Just wait again + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_1; + end if; + debug_state <= x"4"; + + when R_WAIT_1 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_1; + else + R_STATE <= R_RESET_TIMESTAMP; + end if; + debug_state <= x"5"; when R_RESET_TIMESTAMP => -- must reset/resync Timestamp clock and data transmission clock @@ -1392,16 +1594,16 @@ begin reset_handler_counter <= reset_handler_counter + 1; nx_timestamp_reset_o <= '1'; rs_wait_timer_start <= '1'; -- wait 1mue to settle - R_STATE <= R_WAIT_1; - debug_state <= x"4"; + R_STATE <= R_WAIT_2; + debug_state <= x"6"; - when R_WAIT_1 => + when R_WAIT_2 => if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_1; + R_STATE <= R_WAIT_2; else R_STATE <= R_SET_ALL_RESETS; end if; - debug_state <= x"5"; + debug_state <= x"7"; when R_SET_ALL_RESETS => -- timer reset should be finished, can we check status, @@ -1412,34 +1614,35 @@ begin adc_reset_p <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; -- give resets 1mue to take effect rs_wait_timer_start <= '1'; - R_STATE <= R_WAIT_2; - debug_state <= x"6"; + R_STATE <= R_WAIT_3; + debug_state <= x"3"; - when R_WAIT_2 => + when R_WAIT_3 => pll_adc_sampling_clk_reset <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_2; + R_STATE <= R_WAIT_3; else -- now start timeout timer and begin to release resets -- step by step rs_timeout_timer_start <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"7"; + debug_state <= x"8"; when R_WAIT_NX_FRAME_RATE_OK => - if (nx_frame_rate_error = '0') then + if (nx_frame_rate_offline = '0' and + nx_frame_rate_error = '0') then -- Next: Release PLL Reset, i.e. sampling_clk_reset adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; if (disable_adc_r = '0') then R_STATE <= R_PLL_WAIT_LOCK; else @@ -1449,35 +1652,35 @@ begin pll_adc_sampling_clk_reset <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"8"; + debug_state <= x"9"; when R_PLL_WAIT_LOCK => if (adc_sclk_ok_c100 = '1' and pll_adc_not_lock = '0') then -- Next: Release ADC Reset output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; R_STATE <= R_WAIT_ADC_OK; else adc_reset_handler <= '1'; output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; R_STATE <= R_PLL_WAIT_LOCK; end if; - debug_state <= x"9"; + debug_state <= x"6"; when R_WAIT_ADC_OK => - if (adc_locked = '1' and + if (adc_locked_c100 = '1' and adc_frame_rate_error = '0') then -- Next: Release Output Handler and Clock Domain transfer Fifo -- Resets R_STATE <= R_WAIT_DATA_HANDLER_OK; else output_handler_reset <= '1'; - nx_fifo_reset_handler <= '1'; + fifo_reset_handler <= '1'; R_STATE <= R_WAIT_ADC_OK; end if; debug_state <= x"a"; @@ -1501,19 +1704,28 @@ begin ----------------------------------------------------------------------------- -- Error Status ----------------------------------------------------------------------------- + level_to_pulse_ADC_NOTLOCKED: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => not adc_locked_c100, + PULSE_OUT => adc_notlocked_p + ); + PROC_ERROR_STATUS: process(CLK_IN) variable error_mask : std_logic_vector(15 downto 0); begin if (rising_edge(CLK_IN)) then + adc_sclk_ok_f <= adc_sclk_ok; if (RESET_IN = '1') then - nx_online <= '0'; - nx_online_shift <= (others => '0'); - reset_after_offline <= '0'; + adc_sclk_ok_c100 <= '0'; error_status_bits <= (others => '0'); error_o <= '0'; adc_notlock_counter <= (others => '0'); else - error_status_bits(0) <= not nx_online; + adc_sclk_ok_c100 <= adc_sclk_ok_f; + + error_status_bits(0) <= nx_frame_rate_offline; error_status_bits(1) <= frame_rate_error; error_status_bits(2) <= nx_frame_rate_error; error_status_bits(3) <= adc_frame_rate_error; @@ -1522,21 +1734,12 @@ begin error_status_bits(6) <= '0'; error_status_bits(7) <= pll_adc_not_lock; error_status_bits(8) <= not adc_sclk_ok_c100; - error_status_bits(9) <= not adc_locked; + error_status_bits(9) <= not adc_locked_c100; error_status_bits(10) <= timestamp_dt_error; error_status_bits(11) <= adc_dt_error; error_status_bits(12) <= reset_handler_busy; error_status_bits(15 downto 13) <= (others => '0'); - nx_online <= NX_CLOCK_ON_IN and NX_ONLINE_IN; - nx_online_shift(0) <= nx_online; - nx_online_shift(1) <= nx_online_shift(0); - if (nx_online_shift = "01") then - reset_after_offline <= '1'; - else - reset_after_offline <= '0'; - end if; - if (disable_adc_r = '1') then error_mask := x"f437"; else @@ -1590,21 +1793,29 @@ begin PROC_SLAVE_BUS_BUFFER: process(CLK_IN) begin if (rising_edge(CLK_IN)) then + fifo_full_rr <= fifo_full; + fifo_empty_rr <= fifo_empty; nx_frame_synced_rr <= nx_frame_synced; --nx_frame_word_delay_rr <= nx_frame_word_delay_f; if (RESET_IN = '1') then + fifo_full_r <= '0'; + fifo_empty_r <= '0'; nx_frame_synced_r <= '0'; - adc_dt_error_ctr_r <= (others => '0'); - timestamp_dt_error_ctr_r <= (others => '0'); + new_adc_dt_error_ctr_r <= (others => '0'); + new_timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); +-- nx_frame_word_delay_r <= (others => '0'); else + fifo_full_r <= fifo_full_rr; + fifo_empty_r <= fifo_empty_rr; nx_frame_synced_r <= nx_frame_synced_rr; - adc_dt_error_ctr_r <= adc_dt_error_ctr; - timestamp_dt_error_ctr_r <= timestamp_dt_error_ctr; + new_adc_dt_error_ctr_r <= new_adc_dt_error_ctr; + new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; + --nx_frame_word_delay_r <= nx_frame_word_delay_rr; end if; end if; end process PROC_SLAVE_BUS_BUFFER; @@ -1622,12 +1833,13 @@ begin reset_resync_ctr <= '0'; reset_parity_error_ctr <= '0'; johnson_counter_sync_r <= "00"; - pll_adc_sample_clk_dphase_r <= x"5"; + pll_adc_sample_clk_dphase_r <= x"d"; pll_adc_sample_clk_finedelb_r <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; nx_timestamp_delay_adjust <= '1'; - nx_timestamp_delay_r <= "011"; + nx_timestamp_delay_r <= "010"; reset_handler_start_r <= '0'; + adc_bit_shift <= x"0"; adc_debug_type_r <= (others => '0'); debug_mode <= (others => '0'); disable_adc_r <= '0'; @@ -1671,93 +1883,113 @@ begin slv_ack_o <= '1'; when x"0005" => - slv_data_out_o(27 downto 0) <= - std_logic_vector(parity_err_rate); + slv_data_out_o(27 downto 0) <= parity_err_rate; slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; - + when x"0006" => - slv_data_out_o(2 downto 0) <= - std_logic_vector(nx_timestamp_delay_s); - slv_data_out_o(14 downto 3) <= (others => '0'); - slv_data_out_o(15) <= nx_timestamp_delay_adjust; - slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr; - slv_ack_o <= '1'; - - when x"0007" => - slv_data_out_o(3 downto 0) <= - std_logic_vector(pll_adc_sample_clk_dphase_r); - slv_data_out_o(15 downto 4) <= (others => '0'); - slv_data_out_o(19 downto 16) <= - std_logic_vector(pll_adc_sample_clk_finedelb_r); - slv_data_out_o(31 downto 20) <= (others => '0'); - slv_ack_o <= '1'; - - when x"0008" => - slv_data_out_o(15 downto 0) <= - std_logic_vector(reset_handler_counter); + slv_data_out_o(15 downto 0) <= reset_handler_counter; slv_data_out_o(31 downto 6) <= (others => '0'); slv_ack_o <= '1'; - when x"0009" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(adc_reset_ctr); + when x"0007" => + slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"000a" => + when x"0008" => slv_data_out_o(7 downto 0) <= std_logic_vector(adc_notlock_ctr_r); slv_data_out_o(31 downto 8) <= (others => '0'); slv_ack_o <= '1'; - when x"000b" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(merge_error_ctr_r); + when x"0009" => + slv_data_out_o(11 downto 0) <= merge_error_ctr_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"000c" => + when x"000a" => slv_data_out_o(11 downto 0) <= std_logic_vector(resync_counter); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"000d" => + when x"000b" => slv_data_out_o(11 downto 0) <= std_logic_vector(parity_error_counter); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"000e" => + when x"000c" => slv_data_out_o(11 downto 0) <= std_logic_vector(pll_adc_not_lock_ctr); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - + + when x"000d" => + slv_data_out_o(3 downto 0) <= + std_logic_vector(pll_adc_sample_clk_dphase_r); + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; + + when x"000e" => + slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb_r; + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; + when x"000f" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(adc_dt_error_ctr_r); - slv_data_out_o(31 downto 12) <= (others => '0'); + slv_data_out_o(1 downto 0) <= johnson_counter_sync_r; + slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; when x"0010" => - slv_data_out_o(11 downto 0) <= - std_logic_vector(timestamp_dt_error_ctr_r); - slv_data_out_o(31 downto 12) <= (others => '0'); + slv_data_out_o(2 downto 0) <= + std_logic_vector(nx_timestamp_delay_s); + slv_data_out_o(3) <= '0'; + slv_data_out_o(5 downto 4) <= + (others => '0'); + -- std_logic_vector(nx_frame_word_delay_r); + slv_data_out_o(14 downto 6) <= (others => '0'); + slv_data_out_o(15) <= nx_timestamp_delay_adjust; + slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr; slv_ack_o <= '1'; when x"0011" => + slv_data_out_o(0) <= fifo_full_r; + slv_data_out_o(1) <= fifo_empty_r; + slv_data_out_o(2) <= '0'; + slv_data_out_o(3) <= '0'; + slv_data_out_o(4) <= '0'; + slv_data_out_o(5) <= '0'; + slv_data_out_o(29 downto 6) <= (others => '0'); + slv_data_out_o(30) <= '0'; + slv_data_out_o(31) <= nx_frame_synced_r; + slv_ack_o <= '1'; + + when x"0012" => + slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift); + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0013" => + slv_data_out_o <= (others => '0'); + slv_ack_o <= '1'; + + when x"0014" => + slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr_r; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0015" => + slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr_r; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0016" => slv_data_out_o(27 downto 0) <= std_logic_vector(adc_notlock_counter); slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; - - - when x"001d" => - slv_data_out_o(1 downto 0) <= johnson_counter_sync_r; - slv_data_out_o(31 downto 2) <= (others => '0'); - slv_ack_o <= '1'; when x"001e" => slv_data_out_o(2 downto 0) <= debug_mode; @@ -1782,40 +2014,47 @@ begin when x"0004" => disable_adc_r <= SLV_DATA_IN(31); slv_ack_o <= '1'; + + when x"000a" => + reset_resync_ctr <= '1'; + slv_ack_o <= '1'; - when x"0006" => - nx_timestamp_delay_r <= - unsigned(SLV_DATA_IN(2 downto 0)); - nx_timestamp_delay_adjust <= SLV_DATA_IN(15); + when x"000b" => + reset_parity_error_ctr <= '1'; + slv_ack_o <= '1'; + + when x"000c" => + pll_adc_not_lock_ctr_clear <= '1'; slv_ack_o <= '1'; - when x"0007" => + when x"000d" => pll_adc_sample_clk_dphase_r <= unsigned(SLV_DATA_IN(3 downto 0)); - pll_adc_sample_clk_finedelb_r <= - unsigned(SLV_DATA_IN(19 downto 16)); reset_handler_start_r <= '1'; slv_ack_o <= '1'; - - when x"000c" => - reset_resync_ctr <= '1'; - slv_ack_o <= '1'; - - when x"000d" => - reset_parity_error_ctr <= '1'; - slv_ack_o <= '1'; - when x"000e" => - pll_adc_not_lock_ctr_clear <= '1'; - slv_ack_o <= '1'; - - when x"001d" => + pll_adc_sample_clk_finedelb_r <= SLV_DATA_IN(3 downto 0); + reset_handler_start_r <= '1'; + slv_ack_o <= '1'; + + when x"000f" => johnson_counter_sync_r <= unsigned(SLV_DATA_IN(1 downto 0)) + 1; reset_handler_start_r <= '1'; slv_ack_o <= '1'; + when x"0010" => + nx_timestamp_delay_r <= + unsigned(SLV_DATA_IN(2 downto 0)); + nx_timestamp_delay_adjust <= SLV_DATA_IN(15); + slv_ack_o <= '1'; + + when x"0012" => + adc_bit_shift <= + unsigned(SLV_DATA_IN(3 downto 0)); + slv_ack_o <= '1'; + when x"001e" => debug_mode <= SLV_DATA_IN(2 downto 0); slv_ack_o <= '1'; @@ -1835,9 +2074,6 @@ begin end process PROC_SLAVE_BUS; -- Output Signals - data_o <= data_m; - data_clk_o <=data_clk_m; - NX_TIMESTAMP_RESET_OUT <= nx_timestamp_reset_o; DATA_OUT <= data_o; DATA_CLK_OUT <= data_clk_o; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 817a242..045d20b 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -14,6 +14,7 @@ package nxyter_components is CLK_IN : in std_logic; RESET_IN : in std_logic; CLK_NX_MAIN_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; PLL_ADC_DCLK_LOCK_IN : in std_logic; @@ -350,6 +351,7 @@ component nx_data_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; TRIGGER_IN : in std_logic; NX_ONLINE_IN : in std_logic; NX_CLOCK_ON_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index b9f12d4..6b24ec7 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -21,6 +21,7 @@ entity nXyter_FEE_board is CLK_IN : in std_logic; RESET_IN : in std_logic; CLK_NX_MAIN_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; PLL_ADC_DCLK_LOCK_IN : in std_logic; @@ -557,6 +558,7 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, + NX_DATA_CLK_IN => NX_DATA_CLK_IN, TRIGGER_IN => trigger_timing, -- for debugging only NX_ONLINE_IN => nxyter_online, NX_CLOCK_ON_IN => nxyter_clock_on, diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index b9d5005..6655ada 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -146,7 +146,8 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd" add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd" -add_file -vhdl -lib "work" "cores/fifo_nxyter_32to32_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_nx_frame_8to8_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd" add_file -vhdl -lib "work" "cores/ram_dp_512x40.vhd" @@ -155,7 +156,7 @@ add_file -vhdl -lib "work" "cores/ram_fifo_delay_256x44.vhd" add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd" add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" -add_file -vhdl -lib "work" "cores/dynamic_shift_register33x64.vhd" +add_file -vhdl -lib "work" "cores/dynamic_shift_register8x64.vhd" add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" @@ -197,7 +198,6 @@ add_file -vhdl -lib "work" "source/adc_spi_master.vhd" add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd" add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd" add_file -vhdl -lib "work" "source/adc_ad9228.vhd" -add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd" add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd" add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 0ab087e..74dcb5a 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -267,6 +267,7 @@ architecture trb3_periph_arch of trb3_periph is -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; + signal nx_data_clk : std_logic; signal nx_pll_clk_lock : std_logic; signal nx_pll_reset : std_logic; @@ -662,6 +663,7 @@ begin CLK_IN => clk_100_i, RESET_IN => reset_i, CLK_NX_MAIN_IN => nx_main_clk, + NX_DATA_CLK_IN => nx_data_clk, CLK_ADC_IN => NX_CLK_ADC_DAT, PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock, PLL_ADC_DCLK_LOCK_IN => nx_pll_adc_clk_lock, @@ -765,6 +767,7 @@ begin CLK => CLK_PCLK_RIGHT, RESET => nx_pll_reset, CLKOP => nx_main_clk, + CLKOK => nx_data_clk, LOCK => nx_pll_clk_lock ); diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index fc6d3b6..601932b 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -1,4 +1,4 @@ - ####################################################################### +####################################################################### BLOCK RESETPATHS ; @@ -30,21 +30,17 @@ BLOCK RD_DURING_WR_PATHS ; # CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2 # (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2 -# Speed for the configuration Flash access -SYSCONFIG MCCLK_FREQ = 20; + # Speed for the configuration Flash access + SYSCONFIG MCCLK_FREQ = 20; -FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; - -USE PRIMARY NET "nx_main_clk_c"; -USE PRIMARY NET "clk_100_i_c"; -USE PRIMARY NET "CLK_PCLK_RIGHT_c"; -USE EDGE2EDGE NET "NX_CLK_ADC_DAT"; -USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; - -PRIORITIZE NET "NX1_DATA_CLK_IN_c" 40; -PRIORITIZE NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c" 50; + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; + USE PRIMARY NET "nx_main_clk_c"; + USE PRIMARY NET "nx_data_clk_c"; + USE PRIMARY NET "clk_100_i_c"; + USE PRIMARY NET "CLK_PCLK_RIGHT_c"; + ################################################################# # Reset Nets ################################################################# @@ -88,21 +84,36 @@ MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_reset_ff* MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/timestamp_hold_o_*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_clk_in_ff*" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_reset_handler*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_bit_shift*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_rr*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_rr*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/parity_error_b*" 100ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_CLKDIV*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_data_handler_*/adc_frame_locked*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_data_handler_*/error_status*" 100 ns; - +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0_CLKD_F*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_frame_locked*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_locked_o*" 100 ns; + MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; @@ -113,11 +124,7 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_of MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns; - -MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ; -MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; -MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ; -MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; +MULTICYCLE TO CELL "*/NX1_DEBUG_LINE_*" 100 ns; #SPI Interface REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; @@ -137,8 +144,8 @@ PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN"; +INPUT_SETUP GROUP "NX1_IN" 1.0 ns HOLD 1.0 ns CLKPORT="NX1_DATA_CLK_IN"; -#UGROUP NXYTER1 BBOX 100 70 -# BLKNAME nXyter_FEE_board_0 -#LOCATE UGROUP NXYTER1 SITE "R2C2D"; +UGROUP NXYTER1 BBOX 100 70 + BLKNAME nXyter_FEE_board_0; +LOCATE UGROUP NXYTER1 SITE "R2C2D"; diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index 89af958..9f1cba2 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -1,8 +1,8 @@ -w -i 2 -l 5 --n 40 --t 20 +-n 2 +-t 10 -s 1 -c 1 -e 2 diff --git a/nxyter/trb3_periph_nxyter.lpf b/nxyter/trb3_periph_nxyter.lpf index db3cfab..bab9324 100644 --- a/nxyter/trb3_periph_nxyter.lpf +++ b/nxyter/trb3_periph_nxyter.lpf @@ -125,27 +125,27 @@ LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57 #DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP*" ; -#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; +#IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_3" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_4" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_5" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_6" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_TIMESTAMP_IN_7" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; #DEFINE PORT GROUP "LVDS_group2" "NX1_ADC*IN" ; -#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; -IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; +#IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_D_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_A_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_DCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_NX_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; +IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; -IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=OFF; +IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100 TERMINATEVTT=off; IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25; -- 2.43.0