From 8f9bdbf24467bbc10025487c7a15b503d7a28e90 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 22 Jul 2015 10:43:39 +0200 Subject: [PATCH] updating sync media interfaces, some rework still needed, but running on TRB3sc. --- media_interfaces/ecp3_sfp/serdes_sync_3.ipx | 14 +- media_interfaces/ecp3_sfp/serdes_sync_3.lpc | 10 +- media_interfaces/ecp3_sfp/serdes_sync_3.txt | 4 +- media_interfaces/ecp3_sfp/serdes_sync_3.vhd | 3 +- media_interfaces/ecp3_sfp/serdes_sync_4.ipx | 14 +- media_interfaces/ecp3_sfp/serdes_sync_4.lpc | 26 ++-- media_interfaces/ecp3_sfp/serdes_sync_4.txt | 20 +-- media_interfaces/ecp3_sfp/serdes_sync_4.vhd | 2 +- media_interfaces/med_ecp3_sfp_sync.vhd | 135 +++++++++--------- media_interfaces/med_ecp3_sfp_sync_4.vhd | 63 ++++---- media_interfaces/sync/med_sync_control.vhd | 23 ++- media_interfaces/sync/tx_control.vhd | 45 ++++-- trb_net16_endpoint_hades_full.vhd | 3 + ...t16_endpoint_hades_full_handler_record.vhd | 1 + trb_net16_hub_streaming_port_sctrl_record.vhd | 5 +- trb_net_components.vhd | 3 +- trb_net_std.vhd | 1 + 17 files changed, 213 insertions(+), 159 deletions(-) diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.ipx b/media_interfaces/ecp3_sfp/serdes_sync_3.ipx index 56769dc..25ef413 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_3.ipx +++ b/media_interfaces/ecp3_sfp/serdes_sync_3.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.lpc b/media_interfaces/ecp3_sfp/serdes_sync_3.lpc index 2c1d210..9218950 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_3.lpc +++ b/media_interfaces/ecp3_sfp/serdes_sync_3.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=8.1 +CoreRevision=8.2 ModuleName=serdes_sync_3 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=06/22/2015 -Time=12:02:18 +Date=07/13/2015 +Time=11:27:01 [Parameters] Verilog=0 @@ -58,7 +58,7 @@ _tx_data_width3=8 _tx_fifo0=DISABLED _tx_fifo1=ENABLED _tx_fifo2=ENABLED -_tx_fifo3=ENABLED +_tx_fifo3=DISABLED _tx_ficlk_rate0=200 _tx_ficlk_rate1=200 _tx_ficlk_rate2=200 @@ -94,7 +94,7 @@ _rx_data_width3=8 _rx_fifo0=ENABLED _rx_fifo1=ENABLED _rx_fifo2=ENABLED -_rx_fifo3=ENABLED +_rx_fifo3=DISABLED _rx_ficlk_rate0=200 _rx_ficlk_rate1=250.0 _rx_ficlk_rate2=250.0 diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.txt b/media_interfaces/ecp3_sfp/serdes_sync_3.txt index 313e7b4..9ba5987 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_3.txt +++ b/media_interfaces/ecp3_sfp/serdes_sync_3.txt @@ -19,8 +19,8 @@ CH3_RX_DATA_RATE "FULL" CH3_TX_DATA_RATE "FULL" CH3_TX_DATA_WIDTH "8" CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "ENABLED" -CH3_RX_FIFO "ENABLED" +CH3_TX_FIFO "DISABLED" +CH3_RX_FIFO "DISABLED" CH3_TDRV "0" #CH3_TX_FICLK_RATE 200 #CH3_RXREFCLK_RATE "200" diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.vhd b/media_interfaces/ecp3_sfp/serdes_sync_3.vhd index d3ac83f..afb2739 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_3.vhd +++ b/media_interfaces/ecp3_sfp/serdes_sync_3.vhd @@ -1541,7 +1541,6 @@ entity serdes_sync_3 is hdinp_ch3, hdinn_ch3 : in std_logic; hdoutp_ch3, hdoutn_ch3 : out std_logic; sci_sel_ch3 : in std_logic; - rxiclk_ch3 : in std_logic; txiclk_ch3 : in std_logic; rx_full_clk_ch3 : out std_logic; rx_half_clk_ch3 : out std_logic; @@ -2516,7 +2515,7 @@ port map ( PCIE_PHYSTATUS_3 => open, SCISELCH3 => sci_sel_ch3, SCIENCH3 => fpsc_vhi, - FF_RXI_CLK_3 => rxiclk_ch3, + FF_RXI_CLK_3 => fpsc_vlo, FF_TXI_CLK_3 => txiclk_ch3, FF_EBRD_CLK_3 => fpsc_vlo, FF_RX_F_CLK_3 => rx_full_clk_ch3, diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.ipx b/media_interfaces/ecp3_sfp/serdes_sync_4.ipx index f8ee2d8..c97f7a5 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_4.ipx +++ b/media_interfaces/ecp3_sfp/serdes_sync_4.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.lpc b/media_interfaces/ecp3_sfp/serdes_sync_4.lpc index 8080f31..6f97e0c 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_4.lpc +++ b/media_interfaces/ecp3_sfp/serdes_sync_4.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PCS -CoreRevision=8.1 +CoreRevision=8.2 ModuleName=serdes_sync_4 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=06/23/2015 -Time=13:38:56 +Date=07/16/2015 +Time=10:47:32 [Parameters] Verilog=0 @@ -41,8 +41,8 @@ _ldr2=DISABLED _ldr3=DISABLED _datarange=2 _pll_txsrc=INTERNAL -_refclk_mult=20X -_refclk_rate=100 +_refclk_mult=10X +_refclk_rate=200 _tx_protocol0=G8B10B _tx_protocol1=G8B10B _tx_protocol2=G8B10B @@ -55,10 +55,10 @@ _tx_data_width0=8 _tx_data_width1=8 _tx_data_width2=8 _tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED +_tx_fifo0=DISABLED +_tx_fifo1=DISABLED +_tx_fifo2=DISABLED +_tx_fifo3=DISABLED _tx_ficlk_rate0=200 _tx_ficlk_rate1=200 _tx_ficlk_rate2=200 @@ -83,10 +83,10 @@ _rx_data_rate0=FULL _rx_data_rate1=FULL _rx_data_rate2=FULL _rx_data_rate3=FULL -_rxrefclk_rate0=100 -_rxrefclk_rate1=100 -_rxrefclk_rate2=100 -_rxrefclk_rate3=100 +_rxrefclk_rate0=200 +_rxrefclk_rate1=200 +_rxrefclk_rate2=200 +_rxrefclk_rate3=200 _rx_data_width0=8 _rx_data_width1=8 _rx_data_width2=8 diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.txt b/media_interfaces/ecp3_sfp/serdes_sync_4.txt index 9dffbab..33ad2f0 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_4.txt +++ b/media_interfaces/ecp3_sfp/serdes_sync_4.txt @@ -22,8 +22,8 @@ CH0_RX_DATARATE_RANGE "MEDHIGH" CH1_RX_DATARATE_RANGE "MEDHIGH" CH2_RX_DATARATE_RANGE "MEDHIGH" CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "20X" -#REFCLK_RATE 100 +REFCK_MULT "10X" +#REFCLK_RATE 200 CH0_RX_DATA_RATE "FULL" CH1_RX_DATA_RATE "FULL" CH2_RX_DATA_RATE "FULL" @@ -40,10 +40,10 @@ CH0_RX_DATA_WIDTH "8" CH1_RX_DATA_WIDTH "8" CH2_RX_DATA_WIDTH "8" CH3_RX_DATA_WIDTH "8" -CH0_TX_FIFO "ENABLED" -CH1_TX_FIFO "ENABLED" -CH2_TX_FIFO "ENABLED" -CH3_TX_FIFO "ENABLED" +CH0_TX_FIFO "DISABLED" +CH1_TX_FIFO "DISABLED" +CH2_TX_FIFO "DISABLED" +CH3_TX_FIFO "DISABLED" CH0_RX_FIFO "ENABLED" CH1_RX_FIFO "ENABLED" CH2_RX_FIFO "ENABLED" @@ -56,10 +56,10 @@ CH3_TDRV "0" #CH1_TX_FICLK_RATE 200 #CH2_TX_FICLK_RATE 200 #CH3_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "100" -#CH1_RXREFCLK_RATE "100" -#CH2_RXREFCLK_RATE "100" -#CH3_RXREFCLK_RATE "100" +#CH0_RXREFCLK_RATE "200" +#CH1_RXREFCLK_RATE "200" +#CH2_RXREFCLK_RATE "200" +#CH3_RXREFCLK_RATE "200" #CH0_RX_FICLK_RATE 200 #CH1_RX_FICLK_RATE 200 #CH2_RX_FICLK_RATE 200 diff --git a/media_interfaces/ecp3_sfp/serdes_sync_4.vhd b/media_interfaces/ecp3_sfp/serdes_sync_4.vhd index 250aea9..b558cd4 100644 --- a/media_interfaces/ecp3_sfp/serdes_sync_4.vhd +++ b/media_interfaces/ecp3_sfp/serdes_sync_4.vhd @@ -2235,7 +2235,7 @@ end component; attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "100"; + attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; attribute black_box_pad_pin: string; attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd index c6ed506..d360edb 100644 --- a/media_interfaces/med_ecp3_sfp_sync.vhd +++ b/media_interfaces/med_ecp3_sfp_sync.vhd @@ -109,69 +109,70 @@ clk_200_internal <= CLK; SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i <= clk_rx_full; -end generate; - -gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate +-- clk_200_i <= clk_rx_full; +-- end generate; +-- +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate clk_200_i <= clk_200_internal; -end generate; +-- end generate; ------------------------------------------------- -- Serdes ------------------------------------------------- -gen_pcs0 : if SERDES_NUM = 0 generate - THE_SERDES : entity work.serdes_sync_0 - port map( - hdinp_ch0 => SD_RXD_P_IN, - hdinn_ch0 => SD_RXD_N_IN, - hdoutp_ch0 => SD_TXD_P_OUT, - hdoutn_ch0 => SD_TXD_N_OUT, - rxiclk_ch0 => clk_200_i, - txiclk_ch0 => clk_200_i, - rx_full_clk_ch0 => clk_rx_full, - rx_half_clk_ch0 => clk_rx_half, - tx_full_clk_ch0 => clk_tx_full, - tx_half_clk_ch0 => clk_tx_half, - fpga_rxrefclk_ch0 => clk_200_internal, - txdata_ch0 => tx_data, - tx_k_ch0 => tx_k, - tx_force_disp_ch0 => '0', - tx_disp_sel_ch0 => '0', - rxdata_ch0 => rx_data, - rx_k_ch0 => rx_k, - rx_disp_err_ch0 => open, - rx_cv_err_ch0 => rx_error, - rx_serdes_rst_ch0_c => rx_serdes_rst, - sb_felb_ch0_c => '0', - sb_felb_rst_ch0_c => '0', - tx_pcs_rst_ch0_c => tx_pcs_rst, - tx_pwrup_ch0_c => '1', - rx_pcs_rst_ch0_c => rx_pcs_rst, - rx_pwrup_ch0_c => '1', - rx_los_low_ch0_s => rx_los_low, - lsm_status_ch0_s => lsm_status, - rx_cdr_lol_ch0_s => rx_cdr_lol, - tx_div2_mode_ch0_c => '0', - rx_div2_mode_ch0_c => '0', - - SCI_WRDATA => sci_data_in_i, - SCI_RDDATA => sci_data_out_i, - SCI_ADDR => sci_addr_i, - SCI_SEL_QUAD => sci_ch_i(4), - SCI_SEL_CH0 => sci_ch_i(0), - SCI_RD => sci_read_i, - SCI_WRN => sci_write_i, - - fpga_txrefclk => clk_200_i, - tx_serdes_rst_c => '0', - tx_pll_lol_qd_s => tx_pll_lol, - rst_qd_c => rst_qd, - serdes_rst_qd_c => '0' +-- gen_pcs0 : if SERDES_NUM = 0 generate +-- THE_SERDES : entity work.serdes_sync_0 +-- port map( +-- hdinp_ch0 => SD_RXD_P_IN, +-- hdinn_ch0 => SD_RXD_N_IN, +-- hdoutp_ch0 => SD_TXD_P_OUT, +-- hdoutn_ch0 => SD_TXD_N_OUT, +-- rxiclk_ch0 => clk_200_i, +-- txiclk_ch0 => clk_200_i, +-- rx_full_clk_ch0 => clk_rx_full, +-- rx_half_clk_ch0 => clk_rx_half, +-- tx_full_clk_ch0 => clk_tx_full, +-- tx_half_clk_ch0 => clk_tx_half, +-- fpga_rxrefclk_ch0 => clk_200_internal, +-- txdata_ch0 => tx_data, +-- tx_k_ch0 => tx_k, +-- tx_force_disp_ch0 => '0', +-- tx_disp_sel_ch0 => '0', +-- rxdata_ch0 => rx_data, +-- rx_k_ch0 => rx_k, +-- rx_disp_err_ch0 => open, +-- rx_cv_err_ch0 => rx_error, +-- rx_serdes_rst_ch0_c => rx_serdes_rst, +-- sb_felb_ch0_c => '0', +-- sb_felb_rst_ch0_c => '0', +-- tx_pcs_rst_ch0_c => tx_pcs_rst, +-- tx_pwrup_ch0_c => '1', +-- rx_pcs_rst_ch0_c => rx_pcs_rst, +-- rx_pwrup_ch0_c => '1', +-- rx_los_low_ch0_s => rx_los_low, +-- lsm_status_ch0_s => lsm_status, +-- rx_cdr_lol_ch0_s => rx_cdr_lol, +-- tx_div2_mode_ch0_c => '0', +-- rx_div2_mode_ch0_c => '0', +-- +-- SCI_WRDATA => sci_data_in_i, +-- SCI_RDDATA => sci_data_out_i, +-- SCI_ADDR => sci_addr_i, +-- SCI_SEL_QUAD => sci_ch_i(4), +-- SCI_SEL_CH0 => sci_ch_i(0), +-- SCI_RD => sci_read_i, +-- SCI_WRN => sci_write_i, +-- +-- fpga_txrefclk => clk_200_i, +-- tx_serdes_rst_c => '0', +-- tx_pll_lol_qd_s => tx_pll_lol, +-- rst_qd_c => rst_qd, +-- serdes_rst_qd_c => '0' +-- +-- ); +-- end generate; - ); -end generate; gen_pcs3 : if SERDES_NUM = 3 generate THE_SERDES : entity work.serdes_sync_3 port map( @@ -179,8 +180,8 @@ gen_pcs3 : if SERDES_NUM = 3 generate hdinn_ch3 => SD_RXD_N_IN, hdoutp_ch3 => SD_TXD_P_OUT, hdoutn_ch3 => SD_TXD_N_OUT, - rxiclk_ch3 => clk_rx_full, --JM06 - txiclk_ch3 => clk_tx_full, --JM06 clk_tx_fullclk_200_i, +-- rxiclk_ch3 => clk_rx_full, --JM06 + txiclk_ch3 => clk_rx_full, --clk_tx_full, --JM06 clk_tx_fullclk_200_i, JM150706 rx_full_clk_ch3 => clk_rx_full, rx_half_clk_ch3 => clk_rx_half, tx_full_clk_ch3 => clk_tx_full, @@ -215,7 +216,7 @@ gen_pcs3 : if SERDES_NUM = 3 generate SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_i, + fpga_txrefclk => clk_rx_full, tx_serdes_rst_c => '0', tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -237,10 +238,10 @@ THE_MED_CONTROL : entity work.med_sync_control ) port map( CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full, + CLK_RXI => clk_rx_full, --clk_rx_full, CLK_RXHALF => clk_rx_half, - CLK_TXI => clk_tx_full, - CLK_REF => clk_200_internal, + CLK_TXI => clk_rx_full, --clk_200_internal, --clk_tx_full, JM150706 + CLK_REF => clk_200_i, RESET => RESET, CLEAR => CLEAR, @@ -301,11 +302,11 @@ THE_SCI_READER : entity work.sci_reader DEBUG_OUT => open ); -STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); -STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); -STAT_DEBUG(7) <= '0'; -STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); - +-- STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); +-- STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); +-- STAT_DEBUG(7) <= '0'; +-- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); +STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); end architecture; diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 5f7091c..e19af8b 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -35,11 +35,11 @@ entity med_ecp3_sfp_sync_4 is SD_RXD_N_IN : in std_logic_vector(3 downto 0); SD_TXD_P_OUT : out std_logic_vector(3 downto 0); SD_TXD_N_OUT : out std_logic_vector(3 downto 0); - SD_REFCLK_P_IN : in std_logic; --not used - SD_REFCLK_N_IN : in std_logic; --not used + SD_REFCLK_P_IN : in std_logic := '0'; --not used + SD_REFCLK_N_IN : in std_logic := '0'; --not used SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) - SD_TXDIS_OUT : out std_logic_vector(3 downto 0) := '0'; -- SFP disable + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; @@ -56,11 +56,11 @@ architecture med_ecp3_sfp_sync_4_arch of med_ecp3_sfp_sync_4 is -- Placer Directives attribute HGROUP : string; -- for whole architecture - attribute HGROUP of med_ecp3_sfp_sync_arch : architecture is "media_interface_group"; + attribute HGROUP of med_ecp3_sfp_sync_4_arch : architecture is "media_interface_group"; attribute syn_sharing : string; - attribute syn_sharing of med_ecp3_sfp_sync_arch : architecture is "off"; + attribute syn_sharing of med_ecp3_sfp_sync_4_arch : architecture is "off"; attribute syn_hier : string; - attribute syn_hier of med_ecp3_sfp_sync_arch : architecture is "hard"; + attribute syn_hier of med_ecp3_sfp_sync_4_arch : architecture is "hard"; signal clk_200_i : std_logic; signal clk_200_internal : std_logic; @@ -109,13 +109,13 @@ clk_200_internal <= CLK; SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i <= clk_rx_full; -end generate; - -gen_master_clock : if IS_SYNC_SLAVE = c_NO generate +-- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate +-- clk_200_i <= clk_rx_full; +-- end generate; +-- +-- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate clk_200_i <= clk_200_internal; -end generate; +-- end generate; ------------------------------------------------- @@ -127,7 +127,7 @@ end generate; hdinn_ch0 => SD_RXD_N_IN(0), hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), - rxiclk_ch0 => clk_rx_full(0), + rxiclk_ch0 => clk_200_i, txiclk_ch0 => clk_tx_full(0), rx_full_clk_ch0 => clk_rx_full(0), rx_half_clk_ch0 => clk_rx_half(0), @@ -159,7 +159,7 @@ end generate; hdinn_ch1 => SD_RXD_N_IN(1), hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), - rxiclk_ch1 => clk_rx_full(1), + rxiclk_ch1 => clk_200_i, txiclk_ch1 => clk_tx_full(1), rx_full_clk_ch1 => clk_rx_full(1), rx_half_clk_ch1 => clk_rx_half(1), @@ -191,7 +191,7 @@ end generate; hdinn_ch2 => SD_RXD_N_IN(2), hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), - rxiclk_ch2 => clk_rx_full(2), + rxiclk_ch2 => clk_200_i, txiclk_ch2 => clk_tx_full(2), rx_full_clk_ch2 => clk_rx_full(2), rx_half_clk_ch2 => clk_rx_half(2), @@ -223,7 +223,7 @@ end generate; hdinn_ch3 => SD_RXD_N_IN(3), hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), - rxiclk_ch3 => clk_rx_full(3), + rxiclk_ch3 => clk_200_i, txiclk_ch3 => clk_tx_full(3), rx_full_clk_ch3 => clk_rx_full(3), rx_half_clk_ch3 => clk_rx_half(3), @@ -264,9 +264,10 @@ end generate; fpga_txrefclk => clk_200_i, tx_serdes_rst_c => '0', - tx_pll_lol_qd_s => tx_pll_lol(0), + tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd(0), - serdes_rst_qd_c => '0' + serdes_rst_qd_c => '0', + tx_sync_qd_c => '0' ); @@ -283,7 +284,7 @@ gen_control : for i in 0 to 3 generate ) port map( CLK_SYS => SYSCLK, - CLK_RXI => clk_rx_full(i), + CLK_RXI => clk_200_i, CLK_RXHALF => clk_rx_half(i), CLK_TXI => clk_tx_full(i), CLK_REF => clk_200_internal, @@ -321,6 +322,11 @@ gen_control : for i in 0 to 3 generate STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32) ); end generate; + gen_not_used : if IS_USED(i) = c_NO generate + MEDIA_MED2INT(i).dataready <= '0'; + MEDIA_MED2INT(i).tx_read <= '1'; + MEDIA_MED2INT(i).stat_op <= x"0007"; + end generate; end generate; THE_SCI_READER : entity work.sci_reader @@ -342,17 +348,22 @@ THE_SCI_READER : entity work.sci_reader BUS_RX => BUS_RX, BUS_TX => BUS_TX, - MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, - MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, - MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, + MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i(31 downto 0), + MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i(31 downto 0), MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'), DEBUG_OUT => open ); -STAT_DEBUG(4 downto 0) <= debug_rx_control_i(4 downto 0); -STAT_DEBUG(6 downto 5) <= stat_fsm_reset_i(9 downto 8); -STAT_DEBUG(7) <= '0'; -STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); + +STAT_DEBUG(13 downto 0) <= debug_tx_control_i(13 downto 0); +STAT_DEBUG(15 downto 14) <= debug_tx_control_i(17 downto 16); + +-- STAT_DEBUG(3 downto 0) <= debug_tx_control_i(3 downto 0); +-- STAT_DEBUG(5 downto 4) <= stat_fsm_reset_i(9 downto 8); +-- STAT_DEBUG(9 downto 6) <= debug_tx_control_i(19 downto 16); +-- STAT_DEBUG(12 downto 10) <= stat_fsm_reset_i(2 downto 0); +-- STAT_DEBUG(15 downto 13) <= stat_fsm_reset_i(6 downto 4); end architecture; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index b001ac5..211f939 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -79,7 +79,8 @@ signal tx_allow : std_logic; signal got_link_ready_i : std_logic; signal make_link_reset_i : std_logic; signal send_link_reset_i : std_logic; -signal make_link_reset_real_i : std_logic; +signal make_link_reset_real_i : std_logic := '0'; +signal send_link_reset_real_i : std_logic := '0'; signal reset_i, rst_n : std_logic; signal media_med2int_i : MED2INT; @@ -164,7 +165,7 @@ end process; ------------------------------------------------- THE_TX : tx_control port map( - CLK_200 => CLK_TXI, --JM06 clk_200_i, + CLK_200 => CLK_TXI, CLK_100 => CLK_SYS, RESET_IN => reset_i, @@ -199,7 +200,7 @@ THE_TX : tx_control ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => CLK_RXI, --JM06 clk_200_i, + CLK_200 => CLK_RXI, CLK_100 => CLK_SYS, RESET_IN => reset_i, @@ -261,11 +262,21 @@ STAT_RESET(7 downto 4) <= tx_fsm_state; STAT_RESET(8) <= tx_allow; STAT_RESET(9) <= rx_allow; STAT_RESET(31 downto 10) <= (others => '0'); - -make_link_reset_real_i <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0'; + + +gen_link_reset : if IS_SYNC_SLAVE = 1 generate + link_reset_pulse : pulse_sync port map(CLK_RXI,'0',make_link_reset_i, + CLK_SYS,'0',make_link_reset_real_i); + link_reset_send : pulse_sync port map(CLK_RXI,'0',send_link_reset_i, + CLK_SYS,'0',send_link_reset_real_i); +end generate; + + + + sd_los_i <= SFP_LOS when rising_edge(CLK_SYS); -media_med2int_i.stat_op(15) <= send_link_reset_i when rising_edge(CLK_SYS); +media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS); media_med2int_i.stat_op(14) <= '0'; media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset media_med2int_i.stat_op(12) <= led_dlm or last_led_dlm; diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 1a41bc5..2ffcd57 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -48,12 +48,14 @@ architecture arch of tx_control is SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H, SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10 signal current_state : state_t; - + signal state_bits : std_logic_vector(3 downto 0); + type ram_t is array(0 to 255) of std_logic_vector(17 downto 0); signal ram : ram_t; signal ram_write : std_logic := '0'; signal ram_write_addr : unsigned(7 downto 0) := (others => '0'); + signal last_ram_write_addr : unsigned(7 downto 0) := (others => '0'); signal ram_read : std_logic := '0'; signal ram_read_addr : unsigned(7 downto 0) := (others => '0'); signal ram_dout : std_logic_vector(17 downto 0); @@ -212,7 +214,7 @@ begin if tx_allow_qtx = '0' then ram_fill_level <= (others => '0'); else - ram_fill_level <= ram_write_addr - ram_read_addr; + ram_fill_level <= last_ram_write_addr - ram_read_addr; end if; end if; end process; @@ -220,10 +222,10 @@ begin --RAM empty -- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN; - ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; + ram_empty <= '1' when (last_ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0'; ram_afull <= '1' when ram_fill_level >= 4 else '0'; - + last_ram_write_addr <= ram_write_addr when rising_edge(CLK_200); ---------------------------------------------------------------------- -- TX control state machine @@ -480,14 +482,18 @@ tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100); ---------------------------------------------------------------------- -- Debug ---------------------------------------------------------------------- - DEBUG_OUT(0) <= ram_read; + DEBUG_OUT(0) <= ct_fifo_afull; DEBUG_OUT(1) <= ct_fifo_write; DEBUG_OUT(2) <= ct_fifo_read; DEBUG_OUT(3) <= tx_allow_qtx; DEBUG_OUT(4) <= ram_empty; DEBUG_OUT(5) <= ram_afull; DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200); - DEBUG_OUT(15 downto 7) <= (others => '0'); + DEBUG_OUT(7) <= TX_WRITE_IN; + DEBUG_OUT(8) <= ram_read; + DEBUG_OUT(9) <= ram_write; + DEBUG_OUT(13 downto 10) <= state_bits; + DEBUG_OUT(15 downto 14) <= "00"; DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0); DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0); @@ -503,11 +509,32 @@ tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100); STAT_REG_OUT(20) <= make_restart_i; STAT_REG_OUT(21) <= make_request_i; STAT_REG_OUT(22) <= load_eop; - STAT_REG_OUT(31 downto 23) <= (others => '0'); + STAT_REG_OUT(23) <= send_dlm_i; + STAT_REG_OUT(24) <= make_restart_i; + STAT_REG_OUT(25) <= make_request_i; + STAT_REG_OUT(26) <= load_read_pointer_i; + STAT_REG_OUT(27) <= ct_fifo_afull; + STAT_REG_OUT(28) <= ct_fifo_read; + STAT_REG_OUT(29) <= ct_fifo_write; + STAT_REG_OUT(30) <= RESET_IN; + STAT_REG_OUT(31) <= '0'; +-- STAT_REG_OUT(31 downto 27) <= (others => '0'); end if; end process; - - +state_bits <= x"0" when current_state = SEND_IDLE_L else + x"1" when current_state = SEND_IDLE_H else + x"2" when current_state = SEND_DATA_L else + x"3" when current_state = SEND_DATA_H else + x"4" when current_state = SEND_DLM_L else + x"5" when current_state = SEND_DLM_H else + x"6" when current_state = SEND_START_L else + x"7" when current_state = SEND_START_H else + x"8" when current_state = SEND_REQUEST_L else + x"9" when current_state = SEND_REQUEST_H else + x"a" when current_state = SEND_CHKSUM_L else + x"b" when current_state = SEND_CHKSUM_H else + x"c" when current_state = SEND_RESET else + x"F"; end architecture; \ No newline at end of file diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index 1576456..5a2f234 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -139,6 +139,7 @@ entity trb_net16_endpoint_hades_full is REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; REGIO_ONEWIRE_MONITOR_OUT : out std_logic; REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency @@ -1075,5 +1076,7 @@ begin STAT_TRIGGER_OUT <= stat_counters_lvl1_handler; + MY_ADDRESS_OUT <= MY_ADDRESS; + end architecture; diff --git a/trb_net16_endpoint_hades_full_handler_record.vhd b/trb_net16_endpoint_hades_full_handler_record.vhd index ae2dd47..f760237 100644 --- a/trb_net16_endpoint_hades_full_handler_record.vhd +++ b/trb_net16_endpoint_hades_full_handler_record.vhd @@ -261,6 +261,7 @@ begin REGIO_ONEWIRE_MONITOR_IN => '0', REGIO_ONEWIRE_MONITOR_OUT => open, REGIO_VAR_ENDPOINT_ID => REGIO_VAR_ENDPOINT_ID, + MY_ADDRESS_OUT => TIMERS_OUT.network_address, GLOBAL_TIME_OUT => time_global_i, LOCAL_TIME_OUT => time_local_i, diff --git a/trb_net16_hub_streaming_port_sctrl_record.vhd b/trb_net16_hub_streaming_port_sctrl_record.vhd index c68e97f..5cca33b 100644 --- a/trb_net16_hub_streaming_port_sctrl_record.vhd +++ b/trb_net16_hub_streaming_port_sctrl_record.vhd @@ -174,7 +174,7 @@ signal reset_i : std_logic; signal HUB_MED_CTRL_OP : std_logic_vector(mii*16-1 downto 0); signal reset_i_mux_io : std_logic; -signal hub_make_network_reset : std_logic; +signal hub_make_network_reset : std_logic := '0'; signal hub_got_network_reset : std_logic; signal timer_ticks : std_logic_vector(1 downto 0); signal hub_ctrl_debug : std_logic_vector(31 downto 0); @@ -351,8 +351,7 @@ end generate; hub_ctrl_debug(2 downto 0) <= not io_error_in; hub_ctrl_debug(31 downto 3) <= (others => '0'); HUB_STAT_GEN <= buf_HUB_STAT_GEN; --- TIMER_TICKS_OUT <= timer_ticks; - + timer_ticks <= TIMER.tick_ms & TIMER.tick_us; --------------------------------------------------------------------- -- I/O Buffers diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 451668d..441f48c 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -728,7 +728,8 @@ end component; REGIO_ONEWIRE_MONITOR_IN : in std_logic := '0'; REGIO_ONEWIRE_MONITOR_OUT : out std_logic; REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); - + MY_ADDRESS_OUT : out std_logic_vector(15 downto 0); + GLOBAL_TIME_OUT : out std_logic_vector(31 downto 0); --global time, microseconds LOCAL_TIME_OUT : out std_logic_vector(7 downto 0); --local time running with chip frequency TIME_SINCE_LAST_TRG_OUT : out std_logic_vector(31 downto 0); --local time, resetted with each trigger diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 3b4fa76..de999d5 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -203,6 +203,7 @@ package trb_net_std is last_trigger : std_logic_vector (31 downto 0); --local time, resetted with each trigger tick_ms : std_logic; tick_us : std_logic; + network_address : std_logic_vector (15 downto 0); end record; type MED2INT is record -- 2.43.0