From 90034d485dc908788b6dbda994f78781dd73314f Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 18 May 2015 16:10:28 +0200 Subject: [PATCH] Try with 80 again --- ADC/config.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ADC/config.vhd b/ADC/config.vhd index 9204326..6d6bf78 100644 --- a/ADC/config.vhd +++ b/ADC/config.vhd @@ -30,7 +30,7 @@ package config is --note that not all READOUT_MODEs will lead to timing-error free designs --the READOUT_MODE_PSA mode is usually only working with 40MHz --the READOUT_MODE_CFD mode is more robust against clock domain crossing issues - constant ADC_SAMPLING_RATE : integer := 64; + constant ADC_SAMPLING_RATE : integer := 80; --These are currently used for the included features table only constant ADC_BASELINE_LOGIC : integer := c_YES; -- 2.51.0