From 9090be188f3a50c93209bd99dd5541076f04066f Mon Sep 17 00:00:00 2001 From: Michael Traxler Date: Fri, 30 Jul 2021 01:13:07 +0200 Subject: [PATCH] =?utf8?q?added=20bugreport=20about=20precision=20degradat?= =?utf8?q?ion=20if=20the=20temperature=20it=20<30=C2=B0C,=20mt?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- trb3/Trb3KnownBugs.tex | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/trb3/Trb3KnownBugs.tex b/trb3/Trb3KnownBugs.tex index f5063f6..5ee5280 100644 --- a/trb3/Trb3KnownBugs.tex +++ b/trb3/Trb3KnownBugs.tex @@ -9,5 +9,20 @@ \item Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible. \item The JTAG Connector is wrong. The line labelled TDI is TDO and vice versa. \item The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one. + \end{itemize*} +\section{TRB3/TRB3sc Temperature Effect} + +We observed that the time precision of the FPGA-TDC in the ECP3 FPGAs (on TRB3 +and TRB3sc) degrades dramatically (from the well known <20ps RMS to up to +~200ps RMS) if the FPGA temperature decreases below roughly 30°C. +This effect is completely not understood and no workaround except keeping the +FPGA temperature high enough is known. + +This effect is not seen on any board with the ECP5 FPGA (tested by cooling +down 50 FPGAs on the TRB5sc-boards). + + + + -- 2.43.0