From 91307e4900d42ebc34c13640b10c76c2763069af Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 Feb 2024 14:19:01 +0100 Subject: [PATCH] update scalers for Hades spillmon --- code/hadesspillmon.vhd | 2 +- code/scaler_xy.vhd | 156 +++++++++++++++++++++++++++ code/tb/sim/scalers_readout.mpf | 28 ++--- spillmonitor/config.vhd | 2 +- spillmonitor/trb3sc_spillmonitor.lpf | 2 + spillmonitor/trb3sc_spillmonitor.prj | 1 + spillmonitor/trb3sc_spillmonitor.vhd | 27 +++-- 7 files changed, 195 insertions(+), 23 deletions(-) create mode 100644 code/scaler_xy.vhd diff --git a/code/hadesspillmon.vhd b/code/hadesspillmon.vhd index 002512c..70d814f 100644 --- a/code/hadesspillmon.vhd +++ b/code/hadesspillmon.vhd @@ -31,7 +31,7 @@ architecture arch of hadesspillmon is signal CONF_binwidth : integer range 0 to 65000 := 2000; signal CONF_meanwidth : integer range 0 to 65000 := 2100; signal CONF_disable : std_logic_vector(INPUT_NUM-1 downto 0); - signal CONF_recordoffset : unsigned(23 downto 0); + signal CONF_recordoffset : unsigned(23 downto 0) := 10#100000#; --2 seconds signal inp_reg, inp_reg_last : std_logic_vector(INPUT_NUM-1 downto 0); diff --git a/code/scaler_xy.vhd b/code/scaler_xy.vhd new file mode 100644 index 0000000..93d36a8 --- /dev/null +++ b/code/scaler_xy.vhd @@ -0,0 +1,156 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +--use work.config.all; +use work.trb_net_std.all; + +entity scaler_xy is + port( + CLK : in std_logic; + RESET : in std_logic; + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + SIGNAL_IN : in std_logic_vector( 31 downto 0) + + ); +end entity; + +architecture arch of scaler_xy is + + type scaler_arr is array(integer range <>) of unsigned(23 downto 0); + signal scaler : scaler_arr(0 to 255) := (others => (others => '0')); + signal scaler_mult : scaler_arr(0 to 15) := (others => (others => '0')); + + signal last_scaler_update : std_logic_vector(255 downto 0); + + signal selected_scaler : unsigned(23 downto 0); + signal last_read, last2_read : std_logic; + + signal long_inp : std_logic_vector(31 downto 0) := (others => '0'); + signal reg_inp, reg2_inp, reg3_inp : std_logic_vector(31 downto 0); + signal inp_edge, last_inp_edge : std_logic_vector(31 downto 0); + signal last2_inp_edge : std_logic_vector(31 downto 0); + + signal final_sig : std_logic_vector(31 downto 0); + signal last_final_sig : std_logic_vector(31 downto 0); + signal last2_final_sig : std_logic_vector(31 downto 0); + signal long_final_sig : std_logic_vector(31 downto 0); + + signal mult_x, mult_y : unsigned(4 downto 0); + signal all_x, all_y : std_logic; + signal last_update_x,last_update_y : std_logic := '0'; + +begin + + +-------------------------------- +-- Input Handling +-------------------------------- +long_inp <= (long_inp and not reg2_inp) or SIGNAL_IN; +reg_inp <= long_inp when rising_edge(CLK); +reg2_inp <= reg_inp when rising_edge(CLK); +reg3_inp <= reg2_inp when rising_edge(CLK); + +inp_edge <= reg2_inp and not reg3_inp when rising_edge(CLK); +last_inp_edge <= inp_edge when rising_edge(CLK); +last2_inp_edge <= last_inp_edge when rising_edge(CLK); + +final_sig <= inp_edge or last_inp_edge when rising_edge(CLK); +last_final_sig <= final_sig when rising_edge(CLK); +last2_final_sig <= last_final_sig when rising_edge(CLK); +long_final_sig <= final_sig or last2_final_sig when rising_edge(CLK); + +all_x <= or last2_final_sig(15 downto 0) when rising_edge(CLK); +all_y <= or last2_final_sig(31 downto 16) when rising_edge(CLK); + + +gen_scaler_x : for x in 0 to 15 generate + gen_scaler_y : for y in 0 to 15 generate + process begin + wait until rising_edge(CLK); + last_scaler_update(x+y*16) <= '0'; + + if final_sig(x) and final_sig(16 + y) and not last_scaler_update(x+y*16) then + scaler(x+y*16) <= scaler(x+y*16) + 1; + last_scaler_update(x+y*16) <= '1'; + end if; + end process; + end generate; +end generate; + + +PROC_COUNTS_X : process + variable count : unsigned(4 downto 0) := "00000"; +begin + wait until rising_edge(CLK); + count := "00000"; + for i in 0 to 15 loop + count := count + ("0000" & long_final_sig(i)); + end loop; + mult_x <= count; +end process; + +PROC_COUNTS_Y : process + variable count : unsigned(4 downto 0) := "00000"; +begin + wait until rising_edge(CLK); + count := "00000"; + for i in 0 to 15 loop + count := count + ("0000" & long_final_sig(i+16)); + end loop; + mult_y <= count; +end process; + +PROC_SCALER_MULT : process begin + wait until rising_edge(CLK); + last_update_x <= last_update_x and all_x; + last_update_y <= last_update_y and all_y; + + if all_x = '1' and last_update_x = '0' and mult_y(4 downto 3) = "00" then + scaler_mult(to_integer(mult_y(2 downto 0))+8) <= scaler_mult(to_integer(mult_y(2 downto 0))+8) + '1'; + last_update_x <= '1'; + end if; + if all_y = '1' and last_update_y = '0' and mult_x(4 downto 3) = "00" then + scaler_mult(to_integer(mult_x(2 downto 0))) <= scaler_mult(to_integer(mult_x(2 downto 0))) + '1'; + last_update_y <= '1'; + end if; + +end process; + +-------------------------------- +-- Slowcontrol Registers +-------------------------------- +PROC_REGS : process + variable addr : integer range 0 to 255; +begin + wait until rising_edge(CLK); + addr := to_integer(unsigned(BUS_RX.addr(7 downto 0))); + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + BUS_TX.ack <= last2_read; + BUS_TX.data <= x"00" & std_logic_vector(selected_scaler); + + selected_scaler <= scaler(addr); + + last2_read <= last_read; + last_read <= '0'; + + if BUS_RX.read = '1' then + if BUS_RX.addr(8) = '0' then + last_read <= '1'; + elsif BUS_RX.addr(8 downto 4) = "10000" then + BUS_TX.data <= x"00" & std_logic_vector(scaler_mult(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); + BUS_TX.ack <= '1'; + else + BUS_TX.unknown <= '1'; BUS_TX.ack <= '0'; + end if; + end if; +end process; + + + +end architecture; diff --git a/code/tb/sim/scalers_readout.mpf b/code/tb/sim/scalers_readout.mpf index 135cf7b..6315e64 100644 --- a/code/tb/sim/scalers_readout.mpf +++ b/code/tb/sim/scalers_readout.mpf @@ -648,7 +648,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 680 us +RunLength = 1 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1739,17 +1739,19 @@ suppress = 8780 ;an explanation can be had by running: verror 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 5 -Project_File_0 = /local/trb/git/trbnet/lattice/ecp3/fifo/fifo_2x64k_oreg.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1703012791 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_1 = /local/trb/git/trbnet/trb_net_std.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1661268274 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_2 = /local/trb/git/trb3sc/code/scalers_readout.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1703253017 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008 -Project_File_3 = /local/trb/git/trbnet/lattice/ecp3/fifo/fifo_4x2k_oreg.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1702988821 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_4 = /local/trb/git/trb3sc/code/tb/tb_scalers_readout.vhd -Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1703254355 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_Files_Count = 6 +Project_File_0 = /local/trb/git/trb3sc/code/tb/tb_scalers_xy.vhd +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1705674620 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008 +Project_File_1 = /local/trb/git/trbnet/lattice/ecp3/fifo/fifo_2x64k_oreg.vhd +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1703012791 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_2 = /local/trb/git/trbnet/trb_net_std.vhd +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1661268274 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_3 = /local/trb/git/trb3sc/code/scalers_readout.vhd +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1703685171 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_4 = /local/trb/git/trb3sc/code/scaler_xy.vhd +Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1705675087 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2008 +Project_File_5 = /local/trb/git/trbnet/lattice/ecp3/fifo/fifo_4x2k_oreg.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1702988821 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 @@ -1761,7 +1763,7 @@ VERILOG_DoubleClick = Edit VERILOG_CustomDoubleClick = SYSTEMVERILOG_DoubleClick = Edit SYSTEMVERILOG_CustomDoubleClick = -VHDL_DoubleClick = Edit +VHDL_DoubleClick = Compile VHDL_CustomDoubleClick = PSL_DoubleClick = Edit PSL_CustomDoubleClick = diff --git a/spillmonitor/config.vhd b/spillmonitor/config.vhd index 54d5578..231823b 100644 --- a/spillmonitor/config.vhd +++ b/spillmonitor/config.vhd @@ -36,7 +36,7 @@ package config is constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 16; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 16; + constant MONITOR_INPUT_NUM : integer := 32; constant USE_GBE : integer := c_YES; diff --git a/spillmonitor/trb3sc_spillmonitor.lpf b/spillmonitor/trb3sc_spillmonitor.lpf index dbcff81..e3380f1 100644 --- a/spillmonitor/trb3sc_spillmonitor.lpf +++ b/spillmonitor/trb3sc_spillmonitor.lpf @@ -5,6 +5,8 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" CLKNET clk MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full_osc 2x; MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET clk_full 2x; +MULTICYCLE TO CELL "THE_SCALER_XY/selected_scale*" 1x; + FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; FREQUENCY NET "THE_ENDPOINT/THE_ENDPOINT/genbuffers.1.geniobuf.gen_ipu_apl.gen_gbe.THE_GBE/clk_125_rx_from_pcs[0]" 125 MHz; diff --git a/spillmonitor/trb3sc_spillmonitor.prj b/spillmonitor/trb3sc_spillmonitor.prj index c174410..534f3a9 100644 --- a/spillmonitor/trb3sc_spillmonitor.prj +++ b/spillmonitor/trb3sc_spillmonitor.prj @@ -244,6 +244,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vh add_file -vhdl -lib work "../../trb3sc/code/hadesspillmon.vhd" +add_file -vhdl -lib work "../../trb3sc/code/scaler_xy.vhd" add_file -vhdl -lib work "./trb3sc_spillmonitor.vhd" diff --git a/spillmonitor/trb3sc_spillmonitor.vhd b/spillmonitor/trb3sc_spillmonitor.vhd index fcba960..e421f10 100644 --- a/spillmonitor/trb3sc_spillmonitor.vhd +++ b/spillmonitor/trb3sc_spillmonitor.vhd @@ -135,8 +135,8 @@ architecture trb3sc_arch of trb3sc_spillmonitor is signal reboot_from_gbe : std_logic; signal reset_via_gbe : std_logic; signal do_reboot_i : std_logic; - signal ctrlbus_rx, bussci_rx, bustools_rx, busrdo_rx, bustc_rx, busgbeip_rx, busgbereg_rx, busspillmon_rx, bus_master_out : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, bustools_tx, busrdo_tx, bustc_tx, busgbeip_tx, busgbereg_tx, busspillmon_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, busrdo_rx, bustc_rx, busgbeip_rx, busgbereg_rx, busspillmon_rx, busscalerxy_rx, bus_master_out : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, busrdo_tx, bustc_tx, busgbeip_tx, busgbereg_tx, busspillmon_tx, busscalerxy_tx, bus_master_in : CTRLBUS_TX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -205,7 +205,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ); - --------------------------------------------------------------------------- +--------------------------------------------------------------------------- -- GbE --------------------------------------------------------------------------- GBE : entity work.gbe_wrapper @@ -362,9 +362,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"8100", 4 => x"8300", 5 => x"b800", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 8, 5 => 8, others => 0), + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"8100", 4 => x"8300", 5 => x"b800", 6 => x"ba00", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 8, 5 => 8, 6 => 9, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -380,13 +380,14 @@ THE_CLOCK_RESET : entity work.clock_reset_handler BUS_RX(3) => busgbeip_rx, BUS_RX(4) => busgbereg_rx, BUS_RX(5) => busspillmon_rx, + BUS_RX(6) => busscalerxy_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busgbeip_tx, BUS_TX(4) => busgbereg_tx, BUS_TX(5) => busspillmon_tx, - + BUS_TX(6) => busscalerxy_tx, STAT_DEBUG => open ); @@ -419,7 +420,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => INP(15 downto 0), --KEL(32 downto 1),--(others => '0'), + MONITOR_INPUTS => INP(31 downto 0), --KEL(32 downto 1),--(others => '0'), TRIG_GEN_INPUTS => open, --KEL(32 downto 1),--(others => '0'), TRIG_GEN_OUTPUTS => open, --X(8 downto 5),--open, --SED @@ -451,6 +452,16 @@ THE_CLOCK_RESET : entity work.clock_reset_handler BUS_RX => busspillmon_rx, BUS_TX => busspillmon_tx ); + + + THE_SCALER_XY : entity work.scaler_xy + port map( + CLK => clk_sys, + RESET => reset_i, + SIGNAL_IN => INP(31 downto 0), + BUS_RX => busscalerxy_rx, + BUS_TX => busscalerxy_tx + ); --------------------------------------------------------------------------- -- Switches -- 2.43.0