From 913151b38a980612b60040c20e7cfacdd5abc6e8 Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Tue, 8 Jul 2014 15:43:22 +0200 Subject: [PATCH] Back to simple clocking of soda_hub. Using tx_full_clks did not provide a working system although this should be the way (according to docs). Situatiuon: trb is running on oscillator clocks (!!) soda is running on rx_full_clk. This gives a working trbnet (with errors) but I'm amazed that it works at all. --- code/med_ecp3_sfp_4_sync_down.vhd | 88 ++++++++++---------- code/med_ecp3_sfp_sync_down.vhd | 67 +++++++-------- code/med_ecp3_sfp_sync_up.vhd | 66 +++++++-------- code/soda_components.vhd | 29 +++---- code/soda_hub.vhd | 40 ++++----- code/trb3_periph_sodaclient.vhd | 63 +++++++------- code/trb3_periph_sodahub.vhd | 124 +++++++++++++--------------- code/trb3_periph_sodasource.vhd | 31 +++---- soda_client_probe.rvl | 132 ++---------------------------- soda_hub_probe.rvl | 9 +- trb3_soda_client.xcf | 8 +- trb3_soda_hub.xcf | 13 ++- trb3_soda_source.xcf | 5 +- 13 files changed, 274 insertions(+), 401 deletions(-) diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index b378b81..d85ecba 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -33,10 +33,10 @@ entity med_ecp3_sfp_4_sync_down is MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); MED_READ_IN : in std_logic_vector(3 downto 0); - CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz - CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); @@ -88,10 +88,10 @@ signal clk_200_osc : std_logic; signal clk_200_txdata : std_logic; signal clk_200_rxdn : std_logic_vector(3 downto 0); signal clk_200_i : std_logic_vector(3 downto 0); -signal clk_rx_full : std_logic_vector(3 downto 0); -signal clk_rx_half : std_logic_vector(3 downto 0); -signal clk_tx_full : std_logic_vector(3 downto 0); -signal clk_tx_half : std_logic_vector(3 downto 0); +signal rx_full_clk : std_logic_vector(3 downto 0); +signal rx_half_clk : std_logic_vector(3 downto 0); +signal tx_full_clk : std_logic_vector(3 downto 0); +signal tx_half_clk : std_logic_vector(3 downto 0); signal tx_data : t_HUB_BYTE; --std_logic_vector(4*8-1 downto 0); signal tx_k : std_logic_vector(3 downto 0); @@ -175,18 +175,18 @@ gen_clocks : for i in 0 to 3 generate rst(i) <= (CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); rst_n(i) <= not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i)); - CLK_RX_HALF_OUT(i) <= clk_rx_half(i); - CLK_RX_FULL_OUT(i) <= clk_rx_full(i); - CLK_TX_HALF_OUT(i) <= clk_tx_half(i); - CLK_TX_FULL_OUT(i) <= clk_tx_full(i); + RX_HALF_CLK_OUT(i) <= rx_half_clk(i); + RX_FULL_CLK_OUT(i) <= rx_full_clk(i); + TX_HALF_CLK_OUT(i) <= tx_half_clk(i); + TX_FULL_CLK_OUT(i) <= tx_full_clk(i); -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- NO WAY IN HELL !! this downlink is a master --- clk_200_i(i) <= clk_rx_full(i); +-- clk_200_i(i) <= rx_full_clk(i); -- end generate; -- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_200_i(i) <= clk_200_txdata; - clk_200_rxdn(i) <= clk_rx_full(i); -- These clocks are the rx_full of the DOWNLINKs !!! +-- clk_200_i(i) <= clk_200_txdata; +-- clk_200_rxdn(i) <= rx_full_clk(i); -- These clocks are the rx_full of the DOWNLINKs !!! -- end generate; end generate; @@ -200,13 +200,13 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch0 => SD_RXD_N_IN(0), hdoutp_ch0 => SD_TXD_P_OUT(0), hdoutn_ch0 => SD_TXD_N_OUT(0), - rxiclk_ch0 => clk_200_i(0), --clk_200_txdata, + rxiclk_ch0 => clk_200_txdata, --clk_200_i(0), sci_sel_ch0 => sci_ch_i(0), txiclk_ch0 => clk_200_txdata, - rx_full_clk_ch0 => clk_rx_full(0), - rx_half_clk_ch0 => clk_rx_half(0), - tx_full_clk_ch0 => clk_tx_full(0), - tx_half_clk_ch0 => clk_tx_half(0), + rx_full_clk_ch0 => rx_full_clk(0), + rx_half_clk_ch0 => rx_half_clk(0), + tx_full_clk_ch0 => tx_full_clk(0), + tx_half_clk_ch0 => tx_half_clk(0), fpga_rxrefclk_ch0 => clk_200_osc, txdata_ch0 => tx_data(0), tx_k_ch0 => tx_k(0), @@ -233,13 +233,13 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch1 => SD_RXD_N_IN(1), hdoutp_ch1 => SD_TXD_P_OUT(1), hdoutn_ch1 => SD_TXD_N_OUT(1), - rxiclk_ch1 => clk_200_i(1), --clk_200_txdata, + rxiclk_ch1 => clk_200_txdata, --clk_200_i(1), sci_sel_ch1 => sci_ch_i(1), txiclk_ch1 => clk_200_txdata, - rx_full_clk_ch1 => clk_rx_full(1), - rx_half_clk_ch1 => clk_rx_half(1), - tx_full_clk_ch1 => clk_tx_full(1), - tx_half_clk_ch1 => clk_tx_half(1), + rx_full_clk_ch1 => rx_full_clk(1), + rx_half_clk_ch1 => rx_half_clk(1), + tx_full_clk_ch1 => tx_full_clk(1), + tx_half_clk_ch1 => tx_half_clk(1), fpga_rxrefclk_ch1 => clk_200_osc, txdata_ch1 => tx_data(1), tx_k_ch1 => tx_k(1), @@ -266,13 +266,13 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch2 => SD_RXD_N_IN(2), hdoutp_ch2 => SD_TXD_P_OUT(2), hdoutn_ch2 => SD_TXD_N_OUT(2), - rxiclk_ch2 => clk_200_i(2), --clk_200_txdata, + rxiclk_ch2 => clk_200_txdata, --clk_200_i(2), sci_sel_ch2 => sci_ch_i(2), txiclk_ch2 => clk_200_txdata, - rx_full_clk_ch2 => clk_rx_full(2), - rx_half_clk_ch2 => clk_rx_half(2), - tx_full_clk_ch2 => clk_tx_full(2), - tx_half_clk_ch2 => clk_tx_half(2), + rx_full_clk_ch2 => rx_full_clk(2), + rx_half_clk_ch2 => rx_half_clk(2), + tx_full_clk_ch2 => tx_full_clk(2), + tx_half_clk_ch2 => tx_half_clk(2), fpga_rxrefclk_ch2 => clk_200_osc, txdata_ch2 => tx_data(2), tx_k_ch2 => tx_k(2), @@ -299,13 +299,13 @@ THE_SERDES : entity work.serdes_4_sync_downstream hdinn_ch3 => SD_RXD_N_IN(3), hdoutp_ch3 => SD_TXD_P_OUT(3), hdoutn_ch3 => SD_TXD_N_OUT(3), - rxiclk_ch3 => clk_200_i(3), --clk_200_txdata, + rxiclk_ch3 => clk_200_txdata, --clk_200_i(3), sci_sel_ch3 => sci_ch_i(3), txiclk_ch3 => clk_200_txdata, - rx_full_clk_ch3 => clk_rx_full(3), - rx_half_clk_ch3 => clk_rx_half(3), - tx_full_clk_ch3 => clk_tx_full(3), - tx_half_clk_ch3 => clk_tx_half(3), + rx_full_clk_ch3 => rx_full_clk(3), + rx_half_clk_ch3 => rx_half_clk(3), + tx_full_clk_ch3 => tx_full_clk(3), + tx_half_clk_ch3 => tx_half_clk(3), fpga_rxrefclk_ch3 => clk_200_osc, txdata_ch3 => tx_data(3), tx_k_ch3 => tx_k(3), @@ -335,7 +335,7 @@ THE_SERDES : entity work.serdes_4_sync_downstream sci_rd => sci_read_i, sci_wrn => sci_write_i, - fpga_txrefclk => clk_200_osc, --clk_200_i(0), + fpga_txrefclk => clk_200_txdata, --clk_200_osc, --clk_200_i(0), tx_serdes_rst_c => '0', --tx_serdes_rst(0), -- resets tx_pll PL 1906 tx_pll_lol_qd_s => tx_pll_lol_quad, tx_sync_qd_c => '0', -- unused; signal to synchronise channels/serdesses for multi-channel protocols @@ -363,7 +363,7 @@ generated_logic : for i in 0 to 3 generate THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n(i), - RX_REFCLK => clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn + RX_REFCLK => rx_full_clk(i), --clk_200_osc, -- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn TX_PLL_LOL_QD_S => tx_pll_lol(i), RX_SERDES_RST_CH_C => rx_serdes_rst(i), RX_CDR_LOL_CH_S => rx_cdr_lol(i), @@ -376,7 +376,7 @@ generated_logic : for i in 0 to 3 generate THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n(i), - TX_REFCLK => clk_200_osc, + TX_REFCLK => clk_200_txdata, --clk_200_osc, TX_PLL_LOL_QD_S => tx_pll_lol(i), RST_QD_C => rst_qd(i), TX_PCS_RST_CH_C => tx_pcs_rst(i), @@ -388,9 +388,9 @@ generated_logic : for i in 0 to 3 generate wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0"; - PROC_ALLOW : process(clk_200_i(i)) + PROC_ALLOW : process(clk_200_txdata) --clk_200_i(i)) begin - if rising_edge(clk_200_i(i)) then -- clk_200_txdata ?? + if rising_edge(clk_200_txdata) then -- clk_200_txdata ?? if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then rx_allow(i) <= '1'; tx_allow(i) <= '1'; @@ -405,9 +405,9 @@ generated_logic : for i in 0 to 3 generate tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK); - PROC_START_TIMER : process(clk_200_i(i)) --clk_200_txdata?? + PROC_START_TIMER : process(clk_200_txdata) --clk_200_i(i)) begin - if rising_edge(clk_200_i(i)) then + if rising_edge(clk_200_txdata) then if got_link_ready_i(i) = '1' then watchdog_timer(i) <= (others => '0'); if start_timer(i)(start_timer'left) = '0' then @@ -434,7 +434,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => clk_200_i(i), --clk_200_txdata?? + CLK_200 => tx_full_clk(i), --clk_200_i(i), CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! @@ -471,7 +471,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => clk_200_i(i), --PL! + CLK_200 => rx_full_clk(i), --clk_200_i(i), --PL! CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd index 6688014..2842779 100644 --- a/code/med_ecp3_sfp_sync_down.vhd +++ b/code/med_ecp3_sfp_sync_down.vhd @@ -14,7 +14,7 @@ entity med_ecp3_sfp_sync_down is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock + OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset @@ -28,10 +28,10 @@ entity med_ecp3_sfp_sync_down is MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic := '0'; MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz + RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz --Sync operation RX_DLM : out std_logic := '0'; @@ -93,12 +93,13 @@ port ( end component; -signal clk_200_i : std_logic; -signal clk_200_internal : std_logic; -signal clk_rx_full : std_logic; -signal clk_rx_half : std_logic; -signal clk_tx_full : std_logic; -signal clk_tx_half : std_logic; +--signal clk_200_i : std_logic; +--signal clk_200_internal : std_logic; +signal clk_200_osc : std_logic; +signal rx_full_clk_ch0 : std_logic; +signal rx_half_clk_ch0 : std_logic; +signal tx_full_clk_ch0 : std_logic; +signal tx_half_clk_ch0 : std_logic; signal tx_data : std_logic_vector(7 downto 0); signal tx_k : std_logic; @@ -194,12 +195,12 @@ signal start_timer : unsigned(18 downto 0) := (others => '0'); begin -clk_200_internal <= CLK; +clk_200_osc <= OSCCLK; -CLK_RX_HALF_OUT <= clk_rx_half; -CLK_RX_FULL_OUT <= clk_rx_full; -CLK_TX_HALF_OUT <= clk_tx_half; -CLK_TX_FULL_OUT <= clk_tx_full; +RX_HALF_CLK_OUT <= rx_half_clk_ch0; +RX_FULL_CLK_OUT <= rx_full_clk_ch0; +TX_HALF_CLK_OUT <= tx_half_clk_ch0; +TX_FULL_CLK_OUT <= tx_full_clk_ch0; SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -211,11 +212,11 @@ rst_n <= not(CLEAR or internal_make_link_reset_out); rst <= (CLEAR or internal_make_link_reset_out); --gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate --- clk_200_i <= clk_rx_full; +-- clk_200_i <= rx_full_clk_ch0; --end generate; --gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_200_i <= clk_200_internal; +-- clk_200_i <= clk_200_internal; --end generate; @@ -228,13 +229,13 @@ THE_SERDES : entity work.serdes_sync_source_downstream hdinn_ch0 => SD_RXD_N_IN, hdoutp_ch0 => SD_TXD_P_OUT, hdoutn_ch0 => SD_TXD_N_OUT, - rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL! - txiclk_ch0 => clk_200_i, - rx_full_clk_ch0 => clk_rx_full, - rx_half_clk_ch0 => clk_rx_half, - tx_full_clk_ch0 => clk_tx_full, - tx_half_clk_ch0 => clk_tx_half, - fpga_rxrefclk_ch0 => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT + rxiclk_ch0 => tx_full_clk_ch0, --clk_200_i, -- read fifo is no longer present! PL! + txiclk_ch0 => tx_full_clk_ch0, --clk_200_i, + rx_full_clk_ch0 => rx_full_clk_ch0, + rx_half_clk_ch0 => rx_half_clk_ch0, + tx_full_clk_ch0 => tx_full_clk_ch0, + tx_half_clk_ch0 => tx_half_clk_ch0, + fpga_rxrefclk_ch0 => clk_200_osc, --clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT txdata_ch0 => tx_data, tx_k_ch0 => tx_k, tx_force_disp_ch0 => '0', @@ -265,7 +266,7 @@ THE_SERDES : entity work.serdes_sync_source_downstream SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT + fpga_txrefclk => clk_200_osc, --clk_200_internal, -- REF CLK MUST ALWAYS BE PRESENT tx_serdes_rst_c => tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -279,7 +280,7 @@ THE_SERDES : entity work.serdes_sync_source_downstream THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n, - RX_REFCLK => clk_200_i, + RX_REFCLK => rx_full_clk_ch0, --clk_200_i, TX_PLL_LOL_QD_S => tx_pll_lol, RX_SERDES_RST_CH_C => rx_serdes_rst, RX_CDR_LOL_CH_S => rx_cdr_lol, @@ -292,7 +293,7 @@ THE_RX_FSM : rx_reset_fsm THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n, - TX_REFCLK => clk_200_internal, + TX_REFCLK => clk_200_osc, --clk_200_internal, TX_PLL_LOL_QD_S => tx_pll_lol, RST_QD_C => rst_qd, TX_PCS_RST_CH_C => tx_pcs_rst, @@ -305,7 +306,7 @@ wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000"; --Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable PROC_ALLOW : process begin - wait until rising_edge(clk_200_i); + wait until rising_edge(clk_200_osc); --clk_200_i); if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then rx_allow <= '1'; else @@ -337,9 +338,9 @@ tx_allow_q <= tx_allow when rising_edge(SYSCLK); -- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high. -- This gives a slave on the other side time to start-up -- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset -PROC_START_TIMER : process(clk_200_i) +PROC_START_TIMER : process(clk_200_osc) --clk_200_i) begin - if rising_edge(clk_200_i) then + if rising_edge(clk_200_osc) then if got_link_ready_i = '1' then -- watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then @@ -365,7 +366,7 @@ end process; ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => clk_200_i, + CLK_200 => clk_200_osc, --clk_200_i, CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! @@ -402,7 +403,7 @@ LINK_PHASE_OUT <= link_phase_S; --PL! ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => clk_rx_full, --clk_200_i, PL! + CLK_200 => rx_full_clk_ch0, --clk_200_i, PL! CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 7a0bd97..8644227 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -14,7 +14,7 @@ entity med_ecp3_sfp_sync_up is generic( SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_YES); --select slave mode port( - CLK : in std_logic; -- 200 MHz reference clock + OSCCLK : in std_logic; -- 200 MHz reference clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset @@ -28,10 +28,10 @@ entity med_ecp3_sfp_sync_up is MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic := '0'; MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz + RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz --Sync operation RX_DLM : out std_logic := '0'; @@ -94,12 +94,13 @@ DCSOUT :out std_logic) ; end component; -signal clk_200_i : std_logic; -signal clk_200_internal : std_logic; -signal clk_rx_full : std_logic; -signal clk_rx_half : std_logic; -signal clk_tx_full : std_logic; -signal clk_tx_half : std_logic; +--signal clk_200_i : std_logic; +--signal clk_200_internal : std_logic; +signal clk_200_osc : std_logic; +signal rx_full_clk_ch3 : std_logic; +signal rx_half_clk_ch3 : std_logic; +signal tx_full_clk_ch3 : std_logic; +signal tx_half_clk_ch3 : std_logic; signal tx_data : std_logic_vector(7 downto 0); signal tx_k : std_logic; @@ -195,17 +196,17 @@ signal watchdog_trigger : std_logic :='0'; begin -clk_200_internal <= CLK; +clk_200_osc <= OSCCLK; -CLK_RX_HALF_OUT <= clk_rx_half; -CLK_RX_FULL_OUT <= clk_rx_full; -CLK_TX_HALF_OUT <= clk_tx_half; -CLK_TX_FULL_OUT <= clk_tx_full; +RX_HALF_CLK_OUT <= rx_half_clk_ch3; +RX_FULL_CLK_OUT <= rx_full_clk_ch3; +TX_HALF_CLK_OUT <= tx_half_clk_ch3; +TX_FULL_CLK_OUT <= tx_full_clk_ch3; SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready LINK_READY_OUT <= got_link_ready_i; - + --rst_n <= not CLEAR; PL! rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger); @@ -213,7 +214,7 @@ rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigg --gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_200_i <= clk_rx_full; +-- clk_200_i <= rx_full_clk_ch3; --end generate; --gen_master_clock : if IS_SYNC_SLAVE = c_NO generate @@ -230,13 +231,12 @@ THE_SERDES : entity work.serdes_sync_upstream hdinn_ch3 => SD_RXD_N_IN, hdoutp_ch3 => SD_TXD_P_OUT, hdoutn_ch3 => SD_TXD_N_OUT, --- rxiclk_ch3 => clk_200_i, -- no more RX-fifo - txiclk_ch3 => clk_200_i, - rx_full_clk_ch3 => clk_rx_full, - rx_half_clk_ch3 => clk_rx_half, - tx_full_clk_ch3 => clk_tx_full, - tx_half_clk_ch3 => clk_tx_half, - fpga_rxrefclk_ch3 => clk_200_internal, + txiclk_ch3 => rx_full_clk_ch3, --clk_200_i, + rx_full_clk_ch3 => rx_full_clk_ch3, + rx_half_clk_ch3 => rx_half_clk_ch3, + tx_full_clk_ch3 => tx_full_clk_ch3, + tx_half_clk_ch3 => tx_half_clk_ch3, + fpga_rxrefclk_ch3 => clk_200_osc, --clk_200_internal, txdata_ch3 => tx_data, tx_k_ch3 => tx_k, tx_force_disp_ch3 => '0', @@ -266,7 +266,7 @@ THE_SERDES : entity work.serdes_sync_upstream SCI_RD => sci_read_i, SCI_WRN => sci_write_i, - fpga_txrefclk => clk_200_i, + fpga_txrefclk => rx_full_clk_ch3, --clk_200_osc, --clk_200_i, tx_serdes_rst_c => tx_serdes_rst, tx_pll_lol_qd_s => tx_pll_lol, rst_qd_c => rst_qd, @@ -280,7 +280,7 @@ THE_SERDES : entity work.serdes_sync_upstream THE_RX_FSM : rx_reset_fsm port map( RST_N => rst_n, - RX_REFCLK => clk_200_internal, -- allways running PL! + RX_REFCLK => clk_200_osc, --clk_200_internal, -- allways running PL! TX_PLL_LOL_QD_S => tx_pll_lol, RX_SERDES_RST_CH_C => rx_serdes_rst, RX_CDR_LOL_CH_S => rx_cdr_lol, @@ -293,7 +293,7 @@ THE_RX_FSM : rx_reset_fsm THE_TX_FSM : tx_reset_fsm port map( RST_N => rst_n, - TX_REFCLK => clk_200_internal, -- allways running PL! 18-06 was clk_200_i + TX_REFCLK => rx_full_clk_ch3, --clk_200_osc, --clk_200_internal, -- allways running PL! 18-06 was clk_200_i TX_PLL_LOL_QD_S => tx_pll_lol, RST_QD_C => rst_qd, TX_PCS_RST_CH_C => tx_pcs_rst, @@ -306,7 +306,7 @@ wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000"; --Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable PROC_ALLOW : process begin - wait until rising_edge(clk_200_i); + wait until rising_edge(rx_full_clk_ch3); --clk_200_osc); --clk_200_i); if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then rx_allow <= '1'; else @@ -323,9 +323,9 @@ rx_allow_q <= rx_allow when rising_edge(SYSCLK); tx_allow_q <= tx_allow when rising_edge(SYSCLK); -PROC_START_TIMER : process(clk_200_i) +PROC_START_TIMER : process(rx_full_clk_ch3) --clk_200_osc) --clk_200_i) begin - if rising_edge(clk_200_i) then + if rising_edge(clk_200_osc) then if got_link_ready_i = '1' then watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then @@ -351,7 +351,7 @@ end process; ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => clk_200_i, + CLK_200 => rx_full_clk_ch3, --clk_200_osc, --clk_200_i, CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! @@ -388,7 +388,7 @@ LINK_PHASE_OUT <= link_phase_S; --PL! ------------------------------------------------- THE_RX_CONTROL : rx_control port map( - CLK_200 => clk_rx_full, --clk_200_i, PL! + CLK_200 => rx_full_clk_ch3, --clk_200_i, PL! CLK_100 => SYSCLK, RESET_IN => rst, --CLEAR, PL! diff --git a/code/soda_components.vhd b/code/soda_components.vhd index 74a70fd..b3dd5d8 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -150,7 +150,7 @@ package soda_components is port( SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- recovered clock - TX_SODACLK : in t_HUB_BIT; -- transmit clock +-- SODA_OUT_CLK : in t_HUB_BIT; -- transmit clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -309,7 +309,7 @@ component med_ecp3_sfp_sync_down is SERDES_NUM : integer range 0 to 3 := 0; IS_SYNC_SLAVE : integer := c_NO); --select slave mode port( - CLK : in std_logic; -- _internal_ 200 MHz reference clock + OSCCLK : in std_logic; -- _internal_ 200 MHz reference clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset @@ -325,10 +325,10 @@ component med_ecp3_sfp_sync_down is MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic := '0'; MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - CLK_TX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_TX_FULL_OUT : out std_logic := '0'; --received 200 MHz + RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz --Sync operation RX_DLM : out std_logic := '0'; @@ -387,10 +387,10 @@ component med_ecp3_sfp_4_sync_down is MED_PACKET_NUM_OUT : out t_HUB_NUM; -- std_logic_vector(4*c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic_vector(3 downto 0) := (others => '0'); MED_READ_IN : in std_logic_vector(3 downto 0); - CLK_RX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - CLK_RX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz - CLK_TX_HALF_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz - CLK_TX_FULL_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + RX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + RX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz + TX_HALF_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --100 MHz + TX_FULL_CLK_OUT : out std_logic_vector(3 downto 0) := (others => '0'); --200 MHz --Sync operation RX_DLM : out t_HUB_BIT; --std_logic_vector(3 downto 0) := (others => '0'); @@ -433,7 +433,7 @@ component med_ecp3_sfp_sync_up is IS_SYNC_SLAVE : integer := c_YES --select slave mode ); port( - CLK : in std_logic; -- 200 MHz reference clock + OSCCLK : in std_logic; -- 200 MHz reference clock SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset @@ -447,9 +447,10 @@ component med_ecp3_sfp_sync_up is MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0'); MED_DATAREADY_OUT : out std_logic := '0'; MED_READ_IN : in std_logic; - CLK_RX_HALF_OUT : out std_logic := '0'; --received 100 MHz - CLK_RX_FULL_OUT : out std_logic := '0'; --received 200 MHz - + RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz + RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz --Sync operation RX_DLM : out std_logic := '0'; RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index 698e8da..f260850 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -13,7 +13,7 @@ entity soda_hub is port( SYSCLK : in std_logic; -- fabric clock SODACLK : in std_logic; -- recovered clock - TX_SODACLK : in t_HUB_BIT; -- tx-full clock +-- TX_SODACLK : in t_HUB_BIT; -- tx-full clock RESET : in std_logic; -- synchronous reset CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; @@ -151,22 +151,22 @@ begin channel :for i in c_HUB_CHILDREN-1 downto 0 generate - X_clk_domain : process(TX_SODACLK(i)) - begin - if rising_edge(TX_SODACLK(i)) then - if RESET='1' then - TXsoda_cmd_valid_S(i) <= '0'; - TXstart_of_superburst_S(i) <= '0'; - TXsoda_cmd_word_S(i) <= (others => '0'); - TXsuper_burst_nr_S(i) <= (others => '0'); - else - TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; - TXstart_of_superburst_S(i) <= start_of_superburst_S; - TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; - TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; - end if; - end if; - end process; + --X_clk_domain : process(TX_SODACLK(i)) + --begin + --if rising_edge(TX_SODACLK(i)) then + --if RESET='1' then + --TXsoda_cmd_valid_S(i) <= '0'; + --TXstart_of_superburst_S(i) <= '0'; + --TXsoda_cmd_word_S(i) <= (others => '0'); + --TXsuper_burst_nr_S(i) <= (others => '0'); + --else + --TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; + --TXstart_of_superburst_S(i) <= start_of_superburst_S; + --TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; + --TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; + --end if; + --end if; + --end process; @@ -174,7 +174,7 @@ begin packet_builder : soda_packet_builder port map( - SODACLK => TX_SODACLK(i), + SODACLK => SODACLK, RESET => RESET, --Internal Connection SODA_CMD_STROBE_IN => TXsoda_cmd_valid_S(i), @@ -190,7 +190,7 @@ begin hub_reply_handler : soda_reply_handler port map( - SODACLK => TX_SODACLK(i), + SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => '1', @@ -205,7 +205,7 @@ begin hub_calibration_timer : soda_calibration_timer port map( - SODACLK => TX_SODACLK(i), + SODACLK => SODACLK, RESET => RESET, CLEAR => '0', CLK_EN => '1', diff --git a/code/trb3_periph_sodaclient.vhd b/code/trb3_periph_sodaclient.vhd index 73784bd..743ea40 100644 --- a/code/trb3_periph_sodaclient.vhd +++ b/code/trb3_periph_sodaclient.vhd @@ -115,7 +115,7 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is --Clock / Reset -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL +-- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; @@ -124,8 +124,13 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; signal clk_sys_internal : std_logic; - signal clk_raw_internal : std_logic; - signal clk_tdc : std_logic; +-- signal clk_raw_internal : std_logic; + signal clk_200_osc : std_logic; + signal rx_full_clk : std_logic; + signal rx_half_clk : std_logic; + signal tx_full_clk : std_logic; + signal tx_half_clk : std_logic; +-- signal clk_tdc : std_logic; signal time_counter, time_counter2 : unsigned(31 downto 0); --Media Interface signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0); @@ -193,8 +198,8 @@ architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is --SODA -signal soda_rx_clock_half : std_logic; -signal soda_rx_clock_full : std_logic; +--signal soda_rx_clock_half : std_logic; +--signal soda_rx_clock_full : std_logic; signal tx_dlm_i : std_logic; signal rx_dlm_i : std_logic; signal tx_dlm_word : std_logic_vector(7 downto 0); @@ -219,16 +224,16 @@ signal link_phase_S : std_logic; --PL! signal soda_counter_i : unsigned(3 downto 0); attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining - attribute syn_preserve of clk_soda_i : signal is true; - attribute syn_keep of clk_soda_i : signal is true; +-- attribute syn_preserve of clk_soda_i : signal is true; +-- attribute syn_keep of clk_soda_i : signal is true; -- attribute syn_preserve of soda_rx_clock_full : signal is true; -- attribute syn_keep of soda_rx_clock_full : signal is true; -- attribute syn_preserve of soda_rx_clock_half : signal is true; -- attribute syn_keep of soda_rx_clock_half : signal is true; attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; - attribute syn_preserve of clk_raw_internal : signal is true; - attribute syn_keep of clk_raw_internal : signal is true; + attribute syn_preserve of clk_200_osc : signal is true; + attribute syn_keep of clk_200_osc : signal is true; attribute syn_preserve of tx_dlm_i : signal is true; attribute syn_keep of tx_dlm_i : signal is true; attribute syn_preserve of rx_dlm_i : signal is true; @@ -254,7 +259,7 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! + CLK_IN => clk_200_osc, --clk_raw_internal, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel @@ -279,27 +284,27 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate port map( CLK => CLK_GPLL_RIGHT, CLKOP => clk_sys_internal, - CLKOK => clk_raw_internal, + CLKOK => clk_200_osc, --clk_raw_internal, LOCK => pll_lock ); end generate; -gen_125 : if USE_125_MHZ = c_YES generate - clk_sys_internal <= CLK_GPLL_LEFT; - clk_raw_internal <= CLK_GPLL_LEFT; -end generate; +--gen_125 : if USE_125_MHZ = c_YES generate +-- clk_sys_internal <= CLK_GPLL_LEFT; +-- clk_raw_internal <= CLK_GPLL_LEFT; +--end generate; -gen_sync_clocks : if SYNC_MODE = c_YES generate +--gen_sync_clocks : if SYNC_MODE = c_YES generate -- clk_sys_i <= clk_sys_internal; - clk_soda_i <= soda_rx_clock_full; +-- clk_soda_i <= soda_rx_clock_full; -- clk_200_i <= soda_rx_clock_full; -end generate; +--end generate; -gen_local_clocks : if SYNC_MODE = c_NO generate +--gen_local_clocks : if SYNC_MODE = c_NO generate -- clk_sys_i <= clk_sys_internal; - clk_soda_i <= clk_raw_internal; +-- clk_soda_i <= clk_raw_internal; -- clk_200_i <= clk_raw_internal; -end generate; +--end generate; --------------------------------------------------------------------------- @@ -526,7 +531,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_YES ) port map( - CLK => clk_raw_internal, --clk_200_i, + OSCCLK => clk_200_osc, --clk_raw_internal, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, @@ -539,8 +544,10 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), MED_DATAREADY_OUT => med_dataready_in(0), MED_READ_IN => med_read_out(0), - CLK_RX_HALF_OUT => soda_rx_clock_half, - CLK_RX_FULL_OUT => soda_rx_clock_full, + RX_HALF_CLK_OUT => rx_half_clk, --soda_rx_clock_half, + RX_FULL_CLK_OUT => rx_full_clk, --soda_rx_clock_full, + TX_HALF_CLK_OUT => tx_half_clk, + TX_FULL_CLK_OUT => tx_full_clk, RX_DLM => rx_dlm_i, RX_DLM_WORD => rx_dlm_word, @@ -584,7 +591,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up A_SODA_CLIENT : soda_client port map( SYSCLK => clk_sys_internal, --clk_sys_i, - SODACLK => clk_soda_i, + SODACLK => rx_full_clk, --soda_rx_clock_full, --clk_soda_i, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -637,9 +644,9 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up end if; end process; - process(clk_soda_i) + process(rx_full_clk) --soda_rx_clock_full) --clk_soda_i) begin - if rising_edge(clk_soda_i) then + if rising_edge(rx_full_clk) then soda_counter_i <= soda_counter_i+1; end if; end process; @@ -650,7 +657,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_up TEST_LINE(3) <= soda_counter_i(2); TEST_LINE(4) <= '0'; TEST_LINE(5) <= '0'; - TEST_LINE(6) <= soda_rx_clock_half; + TEST_LINE(6) <= rx_half_clk; TEST_LINE(7) <= '0'; TEST_LINE(8) <= '0'; diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index 1a5ee3f..dff97ba 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -83,7 +83,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is --Clock / Reset -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL - signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL +-- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. signal clear_i : std_logic; @@ -94,8 +94,20 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; signal clk_sys_internal : std_logic; - signal clk_raw_internal : std_logic; - signal clk_tdc : std_logic; +-- signal clk_raw_internal : std_logic; + signal clk_200_osc : std_logic; + + signal rxup_half_clk : std_logic; + signal rxup_full_clk : std_logic; + signal txup_half_clk : std_logic; + signal txup_full_clk : std_logic; + + signal rxdn_half_clk : t_HUB_BIT; + signal rxdn_full_clk : t_HUB_BIT; + signal txdn_half_clk : t_HUB_BIT; + signal txdn_full_clk : t_HUB_BIT; + +-- signal clk_tdc : std_logic; signal time_counter, time_counter2 : unsigned(31 downto 0); --Media Interface signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0'); @@ -174,11 +186,6 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is --SODA --- signal soda_rxup_clock_half : std_logic; - signal soda_rxup_clock_full : std_logic; --- signal soda_rxdn_clock_half : t_HUB_BIT; - signal soda_rxdn_clock_full : t_HUB_BIT; - signal soda_txdn_clock_full : t_HUB_BIT; signal make_reset : std_logic; --SODA uplink @@ -214,38 +221,15 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal soda_counter_i : unsigned(3 downto 0); --- attribute syn_useioff : boolean; --- --no IO-FF for LEDs relaxes timing constraints --- attribute syn_useioff of LED_GREEN : signal is false; --- attribute syn_useioff of LED_ORANGE : signal is false; --- attribute syn_useioff of LED_RED : signal is false; --- attribute syn_useioff of LED_YELLOW : signal is false; --- attribute syn_useioff of TEMPSENS : signal is false; --- attribute syn_useioff of PROGRAMN : signal is false; --- attribute syn_useioff of CODE_LINE : signal is false; --- attribute syn_useioff of LED_LINKOK : signal is false; --- attribute syn_useioff of LED_TX : signal is false; --- attribute syn_useioff of LED_RX : signal is false; --- attribute syn_useioff of SFP_MOD0 : signal is false; --- attribute syn_useioff of SFP_TXDIS : signal is false; --- attribute syn_useioff of SFP_LOS : signal is false; --- attribute syn_useioff of TEST_LINE : signal is false; --H! - --- --important signals _with_ IO-FF --- attribute syn_useioff of FLASH_CLK : signal is true; --- attribute syn_useioff of FLASH_CS : signal is true; --- attribute syn_useioff of FLASH_DIN : signal is true; --- attribute syn_useioff of FLASH_DOUT : signal is true; --- attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining attribute syn_preserve of clk_sys_internal : signal is true; attribute syn_keep of clk_sys_internal : signal is true; - attribute syn_preserve of clk_raw_internal : signal is true; - attribute syn_keep of clk_raw_internal : signal is true; - attribute syn_preserve of clk_soda_i : signal is true; - attribute syn_keep of clk_soda_i : signal is true; +-- attribute syn_preserve of clk_raw_internal : signal is true; +-- attribute syn_keep of clk_raw_internal : signal is true; +-- attribute syn_preserve of clk_soda_i : signal is true; +-- attribute syn_keep of clk_soda_i : signal is true; attribute syn_preserve of txup_dlm_i : signal is true; attribute syn_keep of txup_dlm_i : signal is true; attribute syn_preserve of rxup_dlm_i : signal is true; @@ -276,7 +260,7 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_raw_internal, -- raw master clock, NOT from PLL/DLL! + CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel @@ -286,12 +270,12 @@ begin DEBUG_OUT => open ); - process(clk_sys_internal) - begin - if rising_edge(clk_sys_internal) then - general_reset_i <= not SFP_LOS(1); - end if; - end process; +-- process(clk_sys_internal) +-- begin +-- if rising_edge(clk_sys_internal) then +-- general_reset_i <= not SFP_LOS(1); +-- end if; +-- end process; --------------------------------------------------------------------------- -- Clock Handling @@ -301,7 +285,7 @@ begin port map( CLK => CLK_GPLL_RIGHT, CLKOP => clk_sys_internal, - CLKOK => clk_raw_internal, + CLKOK => clk_200_osc, LOCK => pll_lock ); --end generate; @@ -312,7 +296,7 @@ begin --end generate; --gen_sync_clocks : if SYNC_MODE = c_YES generate - clk_soda_i <= soda_rxup_clock_full; +-- clk_soda_i <= rxup_full_clk; --end generate; --gen_local_clocks : if SYNC_MODE = c_NO generate @@ -445,7 +429,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_YES ) port map( - CLK => clk_raw_internal, --clk_200_i, + OSCCLK => clk_200_osc, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, @@ -458,8 +442,10 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), MED_DATAREADY_OUT => med_dataready_in(0), MED_READ_IN => med_read_out(0), - CLK_RX_HALF_OUT => open, --soda_rxup_clock_half, - CLK_RX_FULL_OUT => soda_rxup_clock_full, + RX_HALF_CLK_OUT => rxup_half_clk, + RX_FULL_CLK_OUT => rxup_full_clk, + TX_HALF_CLK_OUT => txup_half_clk, + TX_FULL_CLK_OUT => txup_full_clk, RX_DLM => rxup_dlm_i, RX_DLM_WORD => rxup_dlm_word, @@ -502,8 +488,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up A_SODA_HUB : soda_hub port map( SYSCLK => clk_sys_internal, --clk_sys_i, - SODACLK => clk_soda_i, - TX_SODACLK => soda_txdn_clock_full, -- This is 4 clocks !! + SODACLK => rxup_full_clk, --clk_soda_i, +-- SODA_OUT_CLK => txdn_full_clk, -- This is 4 clocks !! RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -544,8 +530,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up IS_SYNC_SLAVE => c_NO ) port map( - OSC_CLK => clk_raw_internal, - TX_DATACLK => clk_soda_i, --clk_raw_internal, --clk_200_i, + OSC_CLK => clk_200_osc, + TX_DATACLK => rxup_full_clk, --clk_soda_i, --clk_raw_internal, --clk_200_i, SYSCLK => clk_sys_internal, --clk_sys_i, RESET => downlink_reset, CLEAR => downlink_clear, @@ -596,25 +582,25 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up MED_READ_IN(2) => med_read_out(2), MED_READ_IN(3) => med_read_out(4), - CLK_RX_HALF_OUT(0) => open, - CLK_RX_HALF_OUT(1) => open, - CLK_RX_HALF_OUT(2) => open, - CLK_RX_HALF_OUT(3) => open, + RX_HALF_CLK_OUT(0) => rxdn_half_clk(0), + RX_HALF_CLK_OUT(1) => rxdn_half_clk(1), + RX_HALF_CLK_OUT(2) => rxdn_half_clk(2), + RX_HALF_CLK_OUT(3) => rxdn_half_clk(3), - CLK_RX_FULL_OUT(0) => soda_rxdn_clock_full(0), -- needed for sync replies i.e. calibration - CLK_RX_FULL_OUT(1) => soda_rxdn_clock_full(1), -- needed for sync replies i.e. calibration - CLK_RX_FULL_OUT(2) => soda_rxdn_clock_full(2), -- needed for sync replies i.e. calibration - CLK_RX_FULL_OUT(3) => soda_rxdn_clock_full(3), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration + RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration - CLK_TX_HALF_OUT(0) => open, - CLK_TX_HALF_OUT(1) => open, - CLK_TX_HALF_OUT(2) => open, - CLK_TX_HALF_OUT(3) => open, + TX_HALF_CLK_OUT(0) => txdn_half_clk(0), + TX_HALF_CLK_OUT(1) => txdn_half_clk(1), + TX_HALF_CLK_OUT(2) => txdn_half_clk(2), + TX_HALF_CLK_OUT(3) => txdn_half_clk(3), - CLK_TX_FULL_OUT(0) => soda_txdn_clock_full(0), - CLK_TX_FULL_OUT(1) => soda_txdn_clock_full(1), - CLK_TX_FULL_OUT(2) => soda_txdn_clock_full(2), - CLK_TX_FULL_OUT(3) => soda_txdn_clock_full(3), + TX_FULL_CLK_OUT(0) => txdn_full_clk(0), + TX_FULL_CLK_OUT(1) => txdn_full_clk(1), + TX_FULL_CLK_OUT(2) => txdn_full_clk(2), + TX_FULL_CLK_OUT(3) => txdn_full_clk(3), RX_DLM(0) => rxdn_dlm_i(0), RX_DLM(1) => rxdn_dlm_i(1), @@ -793,9 +779,9 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up end if; end process; - process(clk_soda_i) + process(rxup_full_clk) --clk_soda_i) begin - if rising_edge(clk_soda_i) then + if rising_edge(rxup_full_clk) then soda_counter_i <= soda_counter_i+1; end if; end process; diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index 1706a74..b86f668 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -225,15 +225,6 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal SOB_S : std_logic := '0'; -- fix signal names for constraining - attribute syn_preserve of CLK_GPLL_LEFT : signal is true; - attribute syn_keep of CLK_GPLL_LEFT : signal is true; - attribute syn_preserve of CLK_GPLL_RIGHT : signal is true; - attribute syn_keep of CLK_GPLL_RIGHT : signal is true; - attribute syn_preserve of CLK_PCLK_LEFT : signal is true; - attribute syn_keep of CLK_PCLK_LEFT : signal is true; - attribute syn_preserve of CLK_PCLK_RIGHT : signal is true; - attribute syn_keep of CLK_PCLK_RIGHT : signal is true; - attribute syn_preserve of soda_rx_clock_full : signal is true; attribute syn_keep of soda_rx_clock_full : signal is true; attribute syn_preserve of soda_rx_clock_half : signal is true; @@ -554,7 +545,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down IS_SYNC_SLAVE => c_NO ) port map( - CLK => clk_raw_internal, + OSCCLK => clk_raw_internal, SYSCLK => clk_sys_internal, RESET => reset_i, CLEAR => clear_i, @@ -567,10 +558,10 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), MED_DATAREADY_OUT => med_dataready_in(1), MED_READ_IN => med_read_out(1), - CLK_RX_HALF_OUT => soda_rx_clock_half, - CLK_RX_FULL_OUT => soda_rx_clock_full, - CLK_TX_HALF_OUT => soda_tx_clock_half, - CLK_TX_FULL_OUT => soda_tx_clock_full, + RX_HALF_CLK_OUT => soda_rx_clock_half, + RX_FULL_CLK_OUT => soda_rx_clock_full, + TX_HALF_CLK_OUT => soda_tx_clock_half, + TX_FULL_CLK_OUT => soda_tx_clock_full, RX_DLM => rx_dlm_i, RX_DLM_WORD => rx_dlm_word, @@ -609,8 +600,8 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down -- The Soda Central --------------------------------------------------------------------------- -THE_SOB_SOURCE : soda_start_of_burst_faker - generic map( +THE_SOB_SOURCE : soda_start_of_burst_faker + generic map( CLOCK_PERIOD => cSYS_CLOCK_PERIOD, -- clock-period in ns BURST_PERIOD => cBURST_PERIOD -- burst-period in ns ) @@ -644,8 +635,8 @@ THE_SODA_SOURCE : soda_source SODA_ACK_OUT => soda_ack, LEDS_OUT => soda_leds ); - - + + raw : soda_clockscaler port map( CLK => clk_raw_internal, @@ -653,13 +644,13 @@ raw : soda_clockscaler CLOCK_ENABLE_OUT => open, CLOCK_OUT => open ); - + tx : soda_clockscaler port map( CLK => soda_tx_clock_full, RESET => reset_i, CLOCK_ENABLE_OUT => open, - CLOCK_OUT => open + CLOCK_OUT => open ); diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl index b2226d8..0a27f45 100644 --- a/soda_client_probe.rvl +++ b/soda_client_probe.rvl @@ -1,9 +1,9 @@ - + - + - + @@ -11,7 +11,6 @@ - @@ -22,6 +21,7 @@ + @@ -33,37 +33,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -86,102 +60,14 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - + + + - - - - diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 453ea35..1051fb4 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,10 +1,10 @@ - + - + - - + + @@ -326,6 +326,7 @@ + diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf index f87f918..e38f152 100644 --- a/trb3_soda_client.xcf +++ b/trb3_soda_client.xcf @@ -47,8 +47,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140623.bit - 06/23/14 18:00:44 + /local/lemmens/lattice/soda/trb3_periph_sodaclient_20140707.bit + 07/07/14 13:26:49 Fast Program