From 91568db91f488d274d99a28dac13b19c0f1314c0 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Mon, 4 Jun 2018 11:56:12 +0200 Subject: [PATCH] decoding of pixel hit addresses. --- mupix/Mupix8/sources/PixelAddressDecode.vhd | 79 +++++++++++++++ mupix/Mupix8/tb/PixelAddressDecodeTest.vhd | 101 ++++++++++++++++++++ 2 files changed, 180 insertions(+) create mode 100644 mupix/Mupix8/sources/PixelAddressDecode.vhd create mode 100644 mupix/Mupix8/tb/PixelAddressDecodeTest.vhd diff --git a/mupix/Mupix8/sources/PixelAddressDecode.vhd b/mupix/Mupix8/sources/PixelAddressDecode.vhd new file mode 100644 index 0000000..16fa267 --- /dev/null +++ b/mupix/Mupix8/sources/PixelAddressDecode.vhd @@ -0,0 +1,79 @@ +------------------------------------------------------------ +-- Decoding of pixel address of Mupix 8 to physical address +-- T.Weber +-- Ruhr University Bochum +----------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity PixelAddressDecode is + + generic ( + column_width : integer := 8; -- column bits + row_width : integer := 8); -- row bits + port ( + clk : in std_logic; -- clock in + reset : in std_logic; -- reset in + bypass : in std_logic; -- bypass logic + ena : in std_logic; -- enable in + col_in : in std_logic_vector(column_width - 1 downto 0); -- mupix col addr. + row_in : in std_logic_vector(row_width - 1 downto 0); -- mupix row addr. + valid_o : out std_logic; -- valid output + col_out : out std_logic_vector(column_width - 1 downto 0); -- phys. col addr. + row_out : out std_logic_vector(row_width - 1 downto 0)); -- phys row addr. +end entity PixelAddressDecode; + +architecture rtl of PixelAddressDecode is + + signal row_i : std_logic_vector(row_width - 1 downto 0); + signal col_i : std_logic_vector(column_width - 1 downto 0); + signal valid_i : std_logic; + +begin -- architecture rtl + + decode_proc : process(ena, col_in, row_in) is + variable col_tmp : integer range 0 to 255 := 0; + variable row_tmp : integer range 0 to 255 := 0; + begin + row_i <= (others => '0'); + col_i <= (others => '0'); + valid_i <= '0'; + if ena = '1' then + col_tmp := to_integer(unsigned(col_in)) - 128; + row_tmp := to_integer(unsigned(row_in)); + if row_tmp >= 240 then + row_tmp := 99 - (255 - row_tmp); + elsif row_tmp < 240 and row_tmp >= 140 then + row_tmp := row_tmp - 40; + elsif row_tmp < 140 and row_tmp >= 56 then + row_tmp := row_tmp - 56; + else + row_tmp := row_tmp + 199; + end if; + row_i <= std_logic_vector(to_unsigned(row_tmp, row_width)); + col_i <= std_logic_vector(to_unsigned(col_tmp, column_width)); + valid_i <= '1'; + end if; + end process decode_proc; + + seq_proc : process (clk) is + begin -- process decode_proc + if rising_edge(clk) then + if reset = '1' then + col_out <= (others => '1'); + row_out <= (others => '1'); + else + if bypass = '1' then + col_out <= col_in; + row_out <= row_in; + else + col_out <= col_i; + row_out <= row_i; + valid_o <= valid_i; + end if; + end if; + end if; + end process seq_proc; + +end architecture rtl; diff --git a/mupix/Mupix8/tb/PixelAddressDecodeTest.vhd b/mupix/Mupix8/tb/PixelAddressDecodeTest.vhd new file mode 100644 index 0000000..4aab783 --- /dev/null +++ b/mupix/Mupix8/tb/PixelAddressDecodeTest.vhd @@ -0,0 +1,101 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity PixelAddressDecodeTest is +end entity PixelAddressDecodeTest; + +architecture sim of PixelAddressDecodeTest is + + component PixelAddressDecode is + generic ( + column_width : integer; + row_width : integer); + port ( + clk : in std_logic; + reset : in std_logic; + bypass : in std_logic; + ena : in std_logic; + col_in : in std_logic_vector(column_width - 1 downto 0); + row_in : in std_logic_vector(row_width - 1 downto 0); + valid_o : out std_logic; + col_out : out std_logic_vector(column_width - 1 downto 0); + row_out : out std_logic_vector(row_width - 1 downto 0)); + end component PixelAddressDecode; + + constant column_width : integer := 8; + constant row_width : integer := 8; + constant clk_period : time := 10 ns; + + signal clk : std_logic; + signal reset : std_logic := '0'; + signal bypass : std_logic := '0'; + signal ena : std_logic := '0'; + signal col_in : std_logic_vector(column_width - 1 downto 0) := (others => '1'); + signal row_in : std_logic_vector(row_width - 1 downto 0) := (others => '1'); + signal valid_o : std_logic; + signal col_out : std_logic_vector(column_width - 1 downto 0); + signal row_out : std_logic_vector(row_width - 1 downto 0); + +begin + + PixelAddressDecode_1 : entity work.PixelAddressDecode + generic map ( + column_width => column_width, + row_width => row_width) + port map ( + clk => clk, + reset => reset, + bypass => bypass, + ena => ena, + col_in => col_in, + row_in => row_in, + valid_o => valid_o, + col_out => col_out, + row_out => row_out); + + clk_gen : process is + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process clk_gen; + + stimulus : process is + begin + wait for 100 ns; + -- test bypass + bypass <= '1'; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(245, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(180, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(88, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(30, row_width)); + wait for clk_period; + -- test decoding + bypass <= '0'; + ena <= '1'; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(245, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(180, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(88, row_width)); + wait for clk_period; + col_in <= std_logic_vector(to_unsigned(140, column_width)); + row_in <= std_logic_vector(to_unsigned(30, row_width)); + wait for clk_period; + ena <= '0'; + + end process stimulus; + +end architecture; -- 2.43.0