From 922b787b984ec6f08dba9492d7818b212b0212f5 Mon Sep 17 00:00:00 2001 From: local account Date: Tue, 8 Sep 2015 21:46:44 +0200 Subject: [PATCH] trigger,IPU and slow controll are working, apvs not synced yet --- adcmv3.lpf | 8 ++-- adcmv3_constraints.lpf | 4 +- design/adcmv3.vhd | 4 +- design/rich_trb.vhd | 2 +- setenv.sh | 10 +++++ stdout.log | 83 ------------------------------------------ 6 files changed, 19 insertions(+), 92 deletions(-) create mode 100644 setenv.sh delete mode 100644 stdout.log diff --git a/adcmv3.lpf b/adcmv3.lpf index 3798a01..f0f5fea 100755 --- a/adcmv3.lpf +++ b/adcmv3.lpf @@ -151,8 +151,8 @@ LOCATE COMP "ENA_LVDS_0" SITE "AG15" ; # IOBUF PORT "FPGA_SECTOR_4" IO_TYPE=LVTTL33 ; # Backplane sense wires: sector number # small assembly bug: switch is 180degree rotated, so number are mirrored -#LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15" -#IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_SECTOR_3" SITE "AF11" ; # was "AF15" +IOBUF PORT "BP_SECTOR_3" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_2" SITE "AF12" ; # was "AF13" IOBUF PORT "BP_SECTOR_2" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_SECTOR_1" SITE "AF13" ; # was "AF12" @@ -416,8 +416,8 @@ LOCATE COMP "ENB_LVDS_0" SITE "D12" ; # LOCATE COMP "FPGA_BP_12" SITE "C14" ; # IOBUF PORT "FPGA_BP_12" IO_TYPE=LVTTL33 ; # Backplane sense wires: backplane number -#LOCATE COMP "BP_MODULE_3" SITE "A14" ; -#IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ; +LOCATE COMP "BP_MODULE_3" SITE "A14" ; +IOBUF PORT "BP_MODULE_3" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_MODULE_2" SITE "F13" ; IOBUF PORT "BP_MODULE_2" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "BP_MODULE_1" SITE "E12" ; diff --git a/adcmv3_constraints.lpf b/adcmv3_constraints.lpf index c3130a5..f5a9359 100755 --- a/adcmv3_constraints.lpf +++ b/adcmv3_constraints.lpf @@ -1,6 +1,6 @@ # Clock # Extern CLK100M -# -> DLL_100M -> sysclk_c +# -> DLL_100M -> sysclk # -> PLL_40M -> clk_apv -> APVxy_CLK (0A,0B,1A.1B) # -> clk_adc -> ADCx_CLK (0,1) # Extern ADC0_LCLK (bitclock ADC0) @@ -14,7 +14,7 @@ BLOCK PATH FROM CLKNET "clk_apv*" TO CLKNET "sysclk*"; # PLL 100MHz -> 40MHz ###################################################################### FREQUENCY NET "CLK100M_c" 100.000000 MHz ; -FREQUENCY NET "sysclk_c" 100.000000 MHz ; +FREQUENCY NET "sysclk" 100.000000 MHz ; LOCATE COMP "THE_40M_PLL/PLLDInst_0" SITE "PLL_R103C3" ; FREQUENCY NET "clk_adc" 40.000000 MHz ; diff --git a/design/adcmv3.vhd b/design/adcmv3.vhd index 6d52b73..e9eeb99 100755 --- a/design/adcmv3.vhd +++ b/design/adcmv3.vhd @@ -1373,9 +1373,9 @@ THE_SYNC_PROC: process( sysclk ) begin if( rising_edge(sysclk) ) then bp_module_qq <= bp_module_q; - bp_module_q <= not bp_module; + bp_module_q <= not BP_MODULE; bp_sector_qq <= bp_sector_q; - bp_sector_q <= not bp_sector; + bp_sector_q <= not BP_SECTOR; not_configured <= next_not_configured; -- status bit fe_error <= next_fe_error; -- status bit end if; diff --git a/design/rich_trb.vhd b/design/rich_trb.vhd index c71d950..b89b723 100755 --- a/design/rich_trb.vhd +++ b/design/rich_trb.vhd @@ -214,7 +214,7 @@ THE_UNIFIED_ENDPOINT: trb_net16_endpoint_hades_full MED_CTRL_OP_OUT => med_ctrl_op, -- LVL1 trigger APL - TRG_TIMING_TRG_RECEIVED_IN => open, + TRG_TIMING_TRG_RECEIVED_IN => TIMING_TRG_FOUND_IN, LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_RECEIVED_OUT, LVL1_TRG_VALID_TIMING_OUT => open, --valid timing trigger has been received LVL1_TRG_VALID_NOTIMING_OUT => open, --valid trigger without timing trigger has been received diff --git a/setenv.sh b/setenv.sh new file mode 100644 index 0000000..23d22ae --- /dev/null +++ b/setenv.sh @@ -0,0 +1,10 @@ +#!/bin/sh +export SNPSLMD_LICENSE_FILE="27000@lxcad01.gsi.de" +export LM_LICENSE_FILE="1702@hadeb05" + +export LATTICE_PATH=/opt/lattice/diamond/3.4_x64 +export LATTICE_BIN_PATH=${LATTICE_PATH}/bin/lin64 +export SYNPLIFY="/opt/synplicity/I-2013.09-SP1" +export SYN_DISABLE_RAINBOW_DONGLE=1 + +bindir=$LATTICE_BIN_PATH . ${LATTICE_BIN_PATH}/diamond_env diff --git a/stdout.log b/stdout.log deleted file mode 100644 index 392deb2..0000000 --- a/stdout.log +++ /dev/null @@ -1,83 +0,0 @@ - -Starting: /opt/synplicity/I-2013.09-SP1/linux_a_64/mbin/synbatch_orig -Install: /opt/synplicity/I-2013.09-SP1 -Date: Tue Sep 8 16:09:24 2015 -Version: I-2013.09-SP1 - -Arguments: -product synplify_premier_dp -batch adcmv3.prj -ProductType: synplify_premier_dp - -License checkout: synplifypremierdp -License: synplifypremierdp from server lxcad01.gsi.de -Licensed Vendor: All FPGA -License Option: ident - - - - -Generating DM database... - -compile_dm Completed -Return Code: 0 -Run Time:00h:00m:01s - - -log file: "/home/hadaq/lmaier/ADCM/adcm/workdir/adcmv3.srr" - - - - - -Running adcmv3|workdir - - -Running: Compile on adcmv3|workdir - - -Running: Compile HDL/EDIF on adcmv3|workdir - - -Running: Compile Input on adcmv3|workdir - -Copied /home/hadaq/lmaier/ADCM/adcm/workdir/synwork/adcmv3_comp.srs to /home/hadaq/lmaier/ADCM/adcm/workdir/adcmv3.srs - -compiler Completed -Return Code: 0 -Run Time:00h:00m:16s - - -Complete: Compile HDL/EDIF on adcmv3|workdir - - -Running: Premap on adcmv3|workdir - -premap Completed with warnings -Return Code: 1 -Run Time:00h:00m:04s - - -Complete: Compile on adcmv3|workdir - - -Running: Map on adcmv3|workdir - - -Running: Map & Optimize on adcmv3|workdir - -fpga_mapper Completed with warnings -Return Code: 1 -Run Time:00h:03m:27s - - -Complete: Map on adcmv3|workdir - -Complete: Logic Synthesis on adcmv3|workdir - -exit status=0 - - -exit status=0 - - -License checkin: synplifypremierdp - -- 2.43.0