From 92515e19d3401ff0a4a9c2969ca59969965a0dd9 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 29 Jul 2022 11:01:19 +0200 Subject: [PATCH] relaxed timing --- gbe_trb/base/tx_fifo.vhd | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd index e2cf503..9bd55d9 100644 --- a/gbe_trb/base/tx_fifo.vhd +++ b/gbe_trb/base/tx_fifo.vhd @@ -58,13 +58,14 @@ architecture tx_fifo_arch of tx_fifo is -- state machine signals -- Signals - signal frames_avail : unsigned(7 downto 0); - signal frame_written : std_logic; - signal frame_read : std_logic; - signal mac_fifoeof : std_logic; - signal mac_tx_read : std_logic; - signal frame_active : std_logic; - signal fifo_wr : std_logic; + signal frames_avail : unsigned(7 downto 0); + signal frame_written_x : std_logic; + signal frame_written : std_logic; + signal frame_read : std_logic; + signal mac_fifoeof : std_logic; + signal mac_tx_read : std_logic; + signal frame_active : std_logic; + signal fifo_wr : std_logic; begin @@ -104,8 +105,10 @@ begin mac_tx_read <= MAC_TX_READ_IN when rising_edge(CLK); -- one frame written to FIFO - frame_written <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; + frame_written_x <= '1' when (FIFO_D_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0'; -- HERE + frame_written <= frame_written_x when rising_edge(CLK); + -- one frame read from FIFO frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0'; -- 2.43.0