From 92f7bda5272b008c0890e2b35d918535776a8271 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 5 Nov 2008 17:12:02 +0000 Subject: [PATCH] first working ecp2m media interface, Jan --- basics/signal_sync.vhd | 56 ++ lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc | 44 + lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd | 853 +++++++++++++++++++ lattice/ecp2m/trb_net16_fifo_arch.vhd | 164 ++++ trb_net16_hub_base.vhd | 54 +- trb_net16_ibuf.vhd | 31 +- trb_net16_iobuf.vhd | 13 +- trb_net16_med_ecp_sfp.vhd | 937 +++++++++++++-------- trb_net16_med_tlk.vhd | 3 +- trb_net16_obuf.vhd | 23 +- trb_net16_regIO.vhd | 21 +- trb_net_med_8bit_slow.vhd | 4 +- trb_net_onewire.vhd | 4 +- 13 files changed, 1826 insertions(+), 381 deletions(-) create mode 100644 basics/signal_sync.vhd create mode 100644 lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc create mode 100644 lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd create mode 100644 lattice/ecp2m/trb_net16_fifo_arch.vhd diff --git a/basics/signal_sync.vhd b/basics/signal_sync.vhd new file mode 100644 index 0000000..8a800c2 --- /dev/null +++ b/basics/signal_sync.vhd @@ -0,0 +1,56 @@ +--synchronizes a signal do a different clock domain + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +entity signal_sync is + generic( + WIDTH : integer := 1; -- + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + ); +end entity; + +architecture behavioral of signal_sync is + + signal sync_q : std_logic_vector((DEPTH+1)*WIDTH-1 downto 0); + +begin + sync_q(WIDTH-1 downto 0) <= D_IN; + D_OUT <= sync_q((DEPTH+1)*WIDTH-1 downto DEPTH*WIDTH); + + process(CLK0) + begin + if rising_edge(CLK0) then + if RESET = '1' then + sync_q(2*WIDTH-1 downto WIDTH) <= (others => '0'); + else + sync_q(2*WIDTH-1 downto WIDTH) <= sync_q(WIDTH-1 downto 0); + end if; + end if; + end process; + + gen_others : if DEPTH > 1 generate + gen_flipflops : for i in 2 to DEPTH generate + process(CLK1) + begin + if rising_edge(CLK1) then + if RESET = '1' then + sync_q((i+1)*WIDTH-1 downto i*WIDTH) <= (others => '0'); + else + sync_q((i+1)*WIDTH-1 downto i*WIDTH) <= sync_q(i*WIDTH-1 downto (i-1)*WIDTH); + end if; + end if; + end process; + end generate; + end generate; + +end architecture; diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc b/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc new file mode 100644 index 0000000..a75bc1c --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M35E +PartName=LFE2M35E-5F672C +SpeedGrade=-5 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=4.3 +ModuleName=lattice_ecp2m_fifo_18x1k +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=11/04/2008 +Time=15:19:14 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=1024 +Width=18 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Single Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Single Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +EnECC=0 diff --git a/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd b/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd new file mode 100644 index 0000000..9c2bf8e --- /dev/null +++ b/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd @@ -0,0 +1,853 @@ +-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 4.3 +--/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 18 -depth 1024 -no_enable -pe -1 -pf -1 -e + +-- Tue Nov 4 15:19:14 2008 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity lattice_ecp2m_fifo_18x1k is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end lattice_ecp2m_fifo_18x1k; + +architecture Structure of lattice_ecp2m_fifo_18x1k is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal rden_i_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal ifcount_5: std_logic; + signal co1: std_logic; + signal ifcount_6: std_logic; + signal ifcount_7: std_logic; + signal co2: std_logic; + signal ifcount_8: std_logic; + signal ifcount_9: std_logic; + signal co3: std_logic; + signal ifcount_10: std_logic; + signal co5: std_logic; + signal cnt_con: std_logic; + signal co4: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal co2_1: std_logic; + signal co3_1: std_logic; + signal co4_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; + signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; + signal co3_2: std_logic; + signal wren_i: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; + signal co4_2: std_logic; + signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co1_3: std_logic; + signal iwcount_6: std_logic; + signal iwcount_7: std_logic; + signal wcount_6: std_logic; + signal wcount_7: std_logic; + signal co2_3: std_logic; + signal iwcount_8: std_logic; + signal iwcount_9: std_logic; + signal wcount_8: std_logic; + signal wcount_9: std_logic; + signal co3_3: std_logic; + signal iwcount_10: std_logic; + signal co5_1: std_logic; + signal wcount_10: std_logic; + signal co4_3: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co1_4: std_logic; + signal ircount_6: std_logic; + signal ircount_7: std_logic; + signal rcount_6: std_logic; + signal rcount_7: std_logic; + signal co2_4: std_logic; + signal ircount_8: std_logic; + signal ircount_9: std_logic; + signal rcount_8: std_logic; + signal rcount_9: std_logic; + signal co3_4: std_logic; + signal ircount_10: std_logic; + signal co5_2: std_logic; + signal rcount_10: std_logic; + signal scuba_vlo: std_logic; + signal co4_4: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_1 : label is "0x3232"; + attribute initval of LUT4_0 : label is "0x3232"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "lattice_ecp2m_fifo_18x1k.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_0 : label is "ENABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t3: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_3: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_2: INV + port map (A=>empty_i, Z=>invout_0); + + AND2_t1: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t0: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_1: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_0: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x3232") + -- synopsys translate_on + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + pdp_ram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0, + ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3, + ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6, + ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9, + CEA=>wren_i, CLKA=>Clock, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1, + ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4, + ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7, + ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>Q(8), DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), + DOB12=>Q(12), DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), + DOB16=>Q(16), DOB17=>Q(17)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_29: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_5); + + FF_28: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_6); + + FF_27: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_7); + + FF_26: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_8); + + FF_25: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_9); + + FF_24: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_10); + + FF_23: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_21: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_20: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_19: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_18: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_17: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_16: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_5); + + FF_15: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_6); + + FF_14: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_7); + + FF_13: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_8); + + FF_12: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_9); + + FF_11: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_10); + + FF_10: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_9: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_8: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_7: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_6: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_5: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_5); + + FF_4: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_6); + + FF_3: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_7); + + FF_2: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_8); + + FF_1: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_9); + + FF_0: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_10); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5); + + bdcnt_bctr_3: CB2 + port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con, + CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7); + + bdcnt_bctr_4: CB2 + port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con, + CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); + + bdcnt_bctr_5: CB2 + port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>co2_1); + + e_cmp_3: ALEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co2_1, LE=>co3_1); + + e_cmp_4: ALEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); + + e_cmp_5: ALEB2 + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i, + CI=>co1_2, GE=>co2_2); + + g_cmp_3: AGEB2 + port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i, + CI=>co2_2, GE=>co3_2); + + g_cmp_4: AGEB2 + port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i, + CI=>co3_2, GE=>co4_2); + + g_cmp_5: AGEB2 + port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_ctr_3: CU2 + port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3, + NC0=>iwcount_6, NC1=>iwcount_7); + + w_ctr_4: CU2 + port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_3, + NC0=>iwcount_8, NC1=>iwcount_9); + + w_ctr_5: CU2 + port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1, + NC0=>iwcount_10, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4, + NC0=>ircount_4, NC1=>ircount_5); + + r_ctr_3: CU2 + port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4, + NC0=>ircount_6, NC1=>ircount_7); + + r_ctr_4: CU2 + port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_4, + NC0=>ircount_8, NC1=>ircount_9); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + r_ctr_5: CU2 + port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2, + NC0=>ircount_10, NC1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of lattice_ecp2m_fifo_18x1k is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:ALEB2 use entity ecp2m.ALEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:CB2 use entity ecp2m.CB2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/trb_net16_fifo_arch.vhd b/lattice/ecp2m/trb_net16_fifo_arch.vhd new file mode 100644 index 0000000..3d7763b --- /dev/null +++ b/lattice/ecp2m/trb_net16_fifo_arch.vhd @@ -0,0 +1,164 @@ +library ieee; + +use ieee.std_logic_1164.all; +USE ieee.std_logic_signed.ALL; +USE IEEE.numeric_std.ALL; +use work.trb_net_std.all; + +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture arch_trb_net16_fifo of trb_net16_fifo is +component lattice_ecp2m_fifo_18x1k is + port ( + Data: in std_logic_vector(17 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end component; + + +-- component lattice_ecp2m_fifo_18x16 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x32 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; +-- +-- component lattice_ecp2m_fifo_18x64 is +-- port ( +-- Data: in std_logic_vector(17 downto 0); +-- WrClock: in std_logic; +-- RdClock: in std_logic; +-- WrEn: in std_logic; +-- RdEn: in std_logic; +-- Reset: in std_logic; +-- RPReset: in std_logic; +-- Q: out std_logic_vector(17 downto 0); +-- Empty: out std_logic; +-- Full: out std_logic); +-- end component; + + + signal din, dout : std_logic_vector(c_DATA_WIDTH +1 downto 0); + signal depth16 : std_logic_vector(7 downto 0); + +begin + din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN; + din(c_DATA_WIDTH + 1 downto c_DATA_WIDTH) <= PACKET_NUM_IN; + DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0); + PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 1 downto c_DATA_WIDTH); + DEPTH_OUT <= std_logic_vector(to_unsigned(DEPTH,8)); + + gen_FIFO6 : if DEPTH = 6 generate + fifo:lattice_ecp2m_fifo_18x1k + port map ( + Data => din, + Clock => CLK, + WrEn => WRITE_ENABLE_IN, + RdEn => READ_ENABLE_IN, + Reset => RESET, + Q => dout, + Empty => EMPTY_OUT, + Full => FULL_OUT + ); + end generate; + + +-- gen_FIFO1 : if DEPTH = 1 generate +-- fifo:lattice_ecp2m_fifo_18x16 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- gen_FIFO2 : if DEPTH = 2 generate +-- fifo:lattice_ecp2m_fifo_18x32 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; +-- +-- +-- gen_FIFO3 : if DEPTH = 3 generate +-- fifo:lattice_ecp2m_fifo_18x64 +-- port map ( +-- Data => din, +-- WrClock => CLK, +-- RdClock => CLK, +-- WrEn => WRITE_ENABLE_IN, +-- RdEn => READ_ENABLE_IN, +-- Reset => RESET, +-- RPReset => RESET, +-- Q => dout, +-- Empty => EMPTY_OUT, +-- Full => FULL_OUT +-- ); +-- end generate; + + +end architecture; + + + diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 13708ef..078311a 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -159,7 +159,9 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); signal buf_CTRL_DEBUG : std_logic_vector (31 downto 0); - + signal buf_MED_DATAREADY_OUT : std_logic_vector (MII_NUMBER-1 downto 0); + signal buf_MED_PACKET_NUM_OUT : std_logic_vector(MII_NUMBER*c_NUM_WIDTH-1 downto 0); + signal buf_MED_DATA_OUT : std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0); signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0); @@ -194,6 +196,9 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal IOBUF_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); signal IOBUF_CTRL_GEN : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); signal IOBUF_CTRL_IBUF_BUFFER : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_INIT_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal IOBUF_STAT_REPLY_OBUF_DEBUG : std_logic_vector ((MII_NUMBER*2**(c_MUX_WIDTH-1) + API_NUMBER + TRG_NUMBER)*32-1 downto 0); + signal resync : std_logic_vector(MII_NUMBER-1 downto 0); signal combined_resync : std_logic; signal reg_resync : std_logic; @@ -319,7 +324,9 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is STAT_GEN : out std_logic_vector (31 downto 0); STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) ); end component; @@ -585,9 +592,9 @@ begin MED_DATA_IN => MED_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), MED_PACKET_NUM_IN => MED_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_OUT => MED_READ_OUT(i), - MED_DATAREADY_OUT => MED_DATAREADY_OUT(i), - MED_DATA_OUT => MED_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + MED_DATAREADY_OUT => buf_MED_DATAREADY_OUT(i), + MED_DATA_OUT => buf_MED_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + MED_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), MED_READ_IN => MED_READ_IN(i), INT_DATAREADY_OUT => m_DATAREADY_IN((i+1)*2**(c_MUX_WIDTH-1)-1 downto i*2**(c_MUX_WIDTH-1)), INT_DATA_OUT => m_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), @@ -601,7 +608,9 @@ begin STAT => MPLEX_STAT((i+1)*32-1 downto i*32) ); end generate; - +MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; +MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; +MED_DATA_OUT <= buf_MED_DATA_OUT; --generate IOBufs for MII gen_bufs : for j in 0 to MII_NUMBER-1 generate gen_iobufs: for k in 0 to 2**(c_MUX_WIDTH-1)-1 generate @@ -661,7 +670,9 @@ begin STAT_GEN => IOBUF_STAT_GEN((i+1)*32-1 downto i*32), STAT_IBUF_BUFFER => IOBUF_IBUF_BUFFER((i+1)*32-1 downto i*32), CTRL_GEN => IOBUF_CTRL_GEN((i+1)*32-1 downto i*32), - STAT_CTRL_IBUF_BUFFER => IOBUF_CTRL_IBUF_BUFFER((i+1)*32-1 downto i*32) + STAT_CTRL_IBUF_BUFFER => IOBUF_CTRL_IBUF_BUFFER((i+1)*32-1 downto i*32), + STAT_INIT_OBUF_DEBUG => IOBUF_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32), + STAT_REPLY_OBUF_DEBUG => IOBUF_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) ); end generate; @@ -1236,13 +1247,28 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --debug Status and Control ports - buf_STAT_DEBUG(3 downto 0) <= MED_PACKET_NUM_IN(3 downto 0); - buf_STAT_DEBUG(5 downto 4) <= MED_DATAREADY_IN(1 downto 0); - buf_STAT_DEBUG(7 downto 6) <= HUB_MED_CONNECTED(1 downto 0); - buf_STAT_DEBUG(15 downto 8) <= buf_STAT_POINTS_locked(7 downto 0); - buf_STAT_DEBUG(19 downto 16) <= (others => '0'); - buf_STAT_DEBUG(31 downto 20) <= TEMP_OUT; - + buf_STAT_DEBUG(2 downto 0) <= buf_MED_PACKET_NUM_OUT(2 downto 0); + buf_STAT_DEBUG(3) <= buf_MED_DATAREADY_OUT(0); + buf_STAT_DEBUG(7 downto 4) <= buf_MED_DATA_OUT(3 downto 0); + buf_STAT_DEBUG(10 downto 8) <= MED_PACKET_NUM_IN(5 downto 3); + buf_STAT_DEBUG(11) <= MED_DATAREADY_IN(1); + buf_STAT_DEBUG(12) <= m_DATAREADY_OUT(0); + buf_STAT_DEBUG(15 downto 13) <= m_PACKET_NUM_OUT(2 downto 0); + + buf_STAT_DEBUG(17 downto 16) <= hub_to_buf_INIT_DATAREADY(1 downto 0); + buf_STAT_DEBUG(20 downto 18) <= hub_to_buf_INIT_PACKET_NUM(2 downto 0); + buf_STAT_DEBUG(30 downto 21) <= IOBUF_STAT_INIT_OBUF_DEBUG(9 downto 0); + +-- STAT_DEBUG(0) <= comb_dataready; +-- STAT_DEBUG(3 downto 1) <= transfer_counter; +-- STAT_DEBUG(4) <= MED_DATAREADY_OUT; +-- STAT_DEBUG(7 downto 5) <= MED_PACKET_NUM_OUT; +-- STAT_DEBUG(8) <= sbuf_free; +-- STAT_DEBUG(9) <= comb_next_read; + +-- buf_STAT_DEBUG(31 downto 20) <= TEMP_OUT; + +-- buf_STAT_DEBUG(3) <= MED_DATAREADY_IN(0); buf_HUB_STAT_GEN <= (others => '0'); diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 2f24bb4..30390fe 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -21,8 +21,8 @@ entity trb_net16_ibuf is ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; + CLK : in std_logic; + RESET : in std_logic; CLK_EN : in std_logic; -- Media direction port MED_DATAREADY_IN : in std_logic; @@ -102,7 +102,7 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is end component; - + signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_packet_num_in : std_logic_vector(1 downto 0); @@ -114,11 +114,11 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal saved_packet_type : std_logic_vector(3 downto 0); signal current_fifo_packet_type : std_logic_vector(3 downto 0); signal saved_fifo_packet_type : std_logic_vector(3 downto 0); - + signal next_read_out, reg_read_out : std_logic; - signal got_ack_init_internal, reg_ack_init_internal : std_logic; - signal got_ack_reply_internal, reg_ack_reply_internal : std_logic; + signal got_ack_init_internal, reg_ack_init_internal : std_logic; + signal got_ack_reply_internal, reg_ack_reply_internal : std_logic; signal got_eob_init_out, reg_eob_init_out: std_logic; signal got_eob_reply_out, reg_eob_reply_out: std_logic; signal sbuf_init_free, comb_next_init_read: std_logic; @@ -178,7 +178,7 @@ begin elsif last_fifo_read = '1' then saved_fifo_long_packet_num_out <= fifo_long_packet_num_out; end if; - end if; + end if; end process; ------------------------ @@ -206,7 +206,7 @@ begin end if; end process; --create comb. real packet type - current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0) + current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0) else saved_packet_type; current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_long_packet_num_out = c_H0) else saved_fifo_packet_type; @@ -269,7 +269,7 @@ begin end if; end process; - MED_READ_OUT <= reg_read_out; + MED_READ_OUT <= reg_read_out; reg_buffer: process(CLK) begin @@ -369,10 +369,9 @@ begin CRC_RESET <= '1'; end if; end if; - fifo_read <= not fifo_empty and not (fifo_read_before and not - ((sbuf_init_free and not current_fifo_packet_type(3)) - or (sbuf_reply_free and current_fifo_packet_type(3)) - or throw_away)); + fifo_read <= not fifo_empty and not (fifo_read_before and ((not sbuf_init_free and not current_fifo_packet_type(3)) + or (not sbuf_reply_free and current_fifo_packet_type(3)) + or not throw_away)); if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then if SECURE_MODE = 1 then @@ -389,7 +388,7 @@ begin throw_away <= '1'; end if; if USE_ACKNOWLEDGE = 1 then - if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB + if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F3 then got_eob_init_out <= not current_fifo_packet_type(3); got_eob_reply_out <= current_fifo_packet_type(3); @@ -417,7 +416,7 @@ begin else if fifo_read = '1' then fifo_read_before <= '1'; - elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3)) + elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3)) or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then fifo_read_before <= '0'; end if; @@ -443,7 +442,7 @@ begin - + -- make STAT_BUFFER STAT_BUFFER(3 downto 0) <= std_logic_vector(to_unsigned(DEPTH,4)); STAT_BUFFER(7 downto 4) <= current_rec_buffer_size_out; diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 9c553c3..f0d4532 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -67,7 +67,9 @@ entity trb_net16_iobuf is STAT_GEN : out std_logic_vector (31 downto 0); STAT_IBUF_BUFFER : out std_logic_vector (31 downto 0); CTRL_GEN : in std_logic_vector (31 downto 0); - STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0) + STAT_CTRL_IBUF_BUFFER : in std_logic_vector (31 downto 0); + STAT_INIT_OBUF_DEBUG : out std_logic_vector (31 downto 0); + STAT_REPLY_OBUF_DEBUG : out std_logic_vector (31 downto 0) ); end entity; @@ -97,7 +99,8 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is INT_READ_OUT: out std_logic; -- Status and control port STAT_BUFFER: out std_logic_vector (31 downto 0); - CTRL_BUFFER: in std_logic_vector (31 downto 0) + CTRL_BUFFER: in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) ); end component; @@ -275,7 +278,8 @@ begin INT_PACKET_NUM_IN => INT_INIT_PACKET_NUM_IN, INT_READ_OUT => INT_INIT_READ_OUT, STAT_BUFFER(31 downto 0) => INITOBUF_stat_buffer, - CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer + CTRL_BUFFER(31 downto 0) => INITOBUF_ctrl_buffer, + STAT_DEBUG => STAT_INIT_OBUF_DEBUG ); end generate; genINITOBUF2 : if INIT_CAN_SEND_DATA = 0 generate @@ -323,7 +327,8 @@ begin INT_PACKET_NUM_IN => INT_REPLY_PACKET_NUM_IN, INT_READ_OUT => INT_REPLY_READ_OUT, STAT_BUFFER(31 downto 0) => REPLYOBUF_stat_buffer, - CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer + CTRL_BUFFER(31 downto 0) => REPLYOBUF_ctrl_buffer, + STAT_DEBUG => STAT_REPLY_OBUF_DEBUG ); end generate; genREPLYOBUF2 : if REPLY_CAN_SEND_DATA = 0 generate diff --git a/trb_net16_med_ecp_sfp.vhd b/trb_net16_med_ecp_sfp.vhd index ae44009..26866df 100644 --- a/trb_net16_med_ecp_sfp.vhd +++ b/trb_net16_med_ecp_sfp.vhd @@ -1,7 +1,6 @@ --Media interface for Lattice ECP2M using PCS at 2GHz ---Still missing: link reset features, clock switching after lock - +--Still missing: link reset features, fifo full error handling, signals on stat_op LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; @@ -12,45 +11,43 @@ library work; use work.trb_net_std.all; entity trb_net16_med_ecp_sfp is - port( - CLK : in std_logic; - RESET : in std_logic; --must be applied for at least 2 clock cycles - CLK_EN : in std_logic; +port( CLK : in std_logic; + RESET : in std_logic; -- synchronous reset + CLK_EN : in std_logic; --Internal Connection - MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic; - MED_READ_OUT : out std_logic; - MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic; - MED_READ_IN : in std_logic; - MED_ERROR_OUT : out std_logic_vector(2 downto 0); - - REFCLK2CORE : out std_logic; + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + MED_ERROR_OUT : out std_logic_vector(2 downto 0); + REFCLK2CORE_OUT : out std_logic; --SFP Connection - SD_RXD_P : in std_logic; - SD_RXD_N : in std_logic; - SD_TXD_P : out std_logic; - SD_TXD_N : out std_logic; - SD_REFCLK_P : in std_logic; - SD_REFCLK_N : in std_logic; + SD_RXD_P_IN : in std_logic; + SD_RXD_N_IN : in std_logic; + SD_TXD_P_OUT : out std_logic; + SD_TXD_N_OUT : out std_logic; + SD_REFCLK_P_IN : in std_logic; + SD_REFCLK_N_IN : in std_logic; + SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) -- Status and control port - STAT_OP: out std_logic_vector (15 downto 0); - CTRL_OP: in std_logic_vector (15 downto 0); - - STAT_DEBUG: out std_logic_vector (63 downto 0); - CTRL_DEBUG: in std_logic_vector (63 downto 0) - - ); + STAT_OP : out std_logic_vector (15 downto 0); + CTRL_OP : in std_logic_vector (15 downto 0); + STAT_DEBUG : out std_logic_vector (63 downto 0); + CTRL_DEBUG : in std_logic_vector (63 downto 0) + ); end entity; architecture med_ecp_sfp of trb_net16_med_ecp_sfp is component serdes port( - core_txrefclk, core_rxrefclk : IN std_logic; --CLK --- refclkp, refclkn : in std_logic; + core_txrefclk : IN std_logic; --CLK + core_rxrefclk : IN std_logic; --CLK hdinp2 : IN std_logic; --RX Data input hdinn2 : IN std_logic; --RX Data input ff_rxiclk_ch2 : IN std_logic; --CLK ff_txhalfclk @@ -95,336 +92,620 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp is end component; component trb_net_fifo_16bit_bram_dualport is + generic( + USE_STATUS_FLAGS : integer := c_YES + ); + port( read_clock_in : in std_logic; + write_clock_in : in std_logic; + read_enable_in : in std_logic; + write_enable_in : in std_logic; + fifo_gsr_in : in std_logic; + write_data_in : in std_logic_vector(17 downto 0); + read_data_out : out std_logic_vector(17 downto 0); + full_out : out std_logic; + empty_out : out std_logic; + fifostatus_out : out std_logic_vector(3 downto 0); + valid_read_out : out std_logic; + almost_empty_out : out std_logic; + almost_full_out : out std_logic + ); + end component; + + component dcs is +-- synthesis translate_off + generic ( DCSMODE : string := "POS" ); +-- synthesis translate_on + port( CLK0 : in std_logic; + CLK1 : in std_logic; + SEL : in std_logic; + DCSOUT : out std_logic + ); + end component; + + -- taken from HB1003.pdf, DCS section page 10-34 + attribute DCSMODE : string; + attribute DCSMODE of THE_DCS : label is "POS"; + + component signal_sync is generic( - USE_STATUS_FLAGS : integer := c_YES + WIDTH : integer := 1; -- + DEPTH : integer := 3 ); - port ( - read_clock_in: in std_logic; - write_clock_in: in std_logic; - read_enable_in: in std_logic; - write_enable_in: in std_logic; - fifo_gsr_in: in std_logic; - write_data_in: in std_logic_vector(17 downto 0); - read_data_out: out std_logic_vector(17 downto 0); - full_out: out std_logic; - empty_out: out std_logic; - fifostatus_out: out std_logic_vector(3 downto 0); - valid_read_out: out std_logic; - almost_empty_out:out std_logic; - almost_full_out :out std_logic + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output ); end component; + signal dcs_clk : std_logic; -- DCS output + signal dcs_clk_0 : std_logic; + signal dcs_clk_1 : std_logic; + signal dcs_select : std_logic; + signal flip_flop : std_logic; - signal REFCLK : std_logic; - signal refck2core : std_logic; + signal refck2core : std_logic; --reset signals - signal ffc_quad_rst : std_logic; - signal ffc_lane_tx_rst_ch2 : std_logic; - signal ffc_lane_rx_rst_ch2 : std_logic; + signal ffc_quad_rst : std_logic; + signal ffc_lane_tx_rst_ch2 : std_logic; + signal ffc_lane_rx_rst_ch2 : std_logic; --serdes connections - signal tx_data : std_logic_vector(15 downto 0); - signal tx_k : std_logic_vector(1 downto 0); - signal rx_data : std_logic_vector(15 downto 0); - signal rx_k : std_logic_vector(1 downto 0); - signal link_ok : std_logic_vector(0 downto 0); - signal link_error : std_logic_vector(9 downto 0); - signal ff_rxhalfclk : std_logic; - signal ff_txhalfclk : std_logic; + signal tx_data : std_logic_vector(15 downto 0); + signal tx_k : std_logic_vector(1 downto 0); + signal rx_data : std_logic_vector(15 downto 0); + signal rx_k : std_logic_vector(1 downto 0); + signal link_ok : std_logic_vector(0 downto 0); + signal link_error : std_logic_vector(9 downto 0); + signal ff_rxhalfclk : std_logic; + signal ff_txhalfclk : std_logic; --rx fifo signals - signal fifo_rx_rd_en : std_logic; - signal fifo_rx_wr_en : std_logic; - signal fifo_rx_reset : std_logic; - signal fifo_rx_din : std_logic_vector(17 downto 0); - signal fifo_rx_dout : std_logic_vector(17 downto 0); - signal fifo_rx_full : std_logic; - signal fifo_rx_empty : std_logic; + signal fifo_rx_rd_en : std_logic; + signal fifo_rx_wr_en : std_logic; + signal fifo_rx_reset : std_logic; + signal fifo_rx_din : std_logic_vector(17 downto 0); + signal fifo_rx_dout : std_logic_vector(17 downto 0); + signal fifo_rx_full : std_logic; + signal fifo_rx_empty : std_logic; --tx fifo signals - signal fifo_tx_rd_en : std_logic; - signal fifo_tx_wr_en : std_logic; - signal fifo_tx_reset : std_logic; - signal fifo_tx_din : std_logic_vector(17 downto 0); - signal fifo_tx_dout : std_logic_vector(17 downto 0); - signal fifo_tx_full : std_logic; - signal fifo_tx_empty : std_logic; + signal fifo_tx_rd_en : std_logic; + signal fifo_tx_wr_en : std_logic; + signal fifo_tx_reset : std_logic; + signal fifo_tx_din : std_logic_vector(17 downto 0); + signal fifo_tx_dout : std_logic_vector(17 downto 0); + signal fifo_tx_full : std_logic; + signal fifo_tx_empty : std_logic; --rx path - signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal reset_interface : std_logic; - signal buf_MED_DATAREADY_OUT : std_logic; - signal buf_MED_DATA_OUT : std_logic_vector(c_DATA_WIDTH-1 downto 0); - signal buf_MED_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0); - signal swap_bytes : std_logic; - signal last_rx : std_logic_vector(8 downto 0); + signal rx_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal buf_med_dataready_out : std_logic; + signal buf_med_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); + signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0); + signal last_rx : std_logic_vector(8 downto 0); signal last_fifo_rx_empty : std_logic; --tx path - signal last_fifo_tx_empty : std_logic; + signal last_fifo_tx_empty : std_logic; --link status - type med_state_t is (start, waitplolandrlol, waitrxallow, waittxallow, working); - signal state : med_state_t; - signal state_bits : std_logic_vector(2 downto 0); - signal counter : std_logic_vector(28 downto 0); - signal tx_allow : std_logic; - signal rx_allow : std_logic; - signal serdes_reset : std_logic; - signal serdes_reset_counter : std_logic_vector(6 downto 0); - + signal link_led : std_logic; + + + -- state machine signals + type STATES is ( SLEEP, QRST, WPAR, WLOS, ALIGN, WRXA, WTXA, LINK ); + signal CURRENT_STATE, NEXT_STATE: STATES; + signal state_bits : std_logic_vector(3 downto 0); + signal clock : std_logic; + + signal med_error_x : std_logic_vector(2 downto 0); + signal med_error : std_logic_vector(2 downto 0); + + signal timing_ctr : std_logic_vector(28 downto 0); + signal ce_ctr_x : std_logic; + signal ce_ctr : std_logic; + signal rst_ctr_x : std_logic; + signal rst_ctr : std_logic; + signal quad_rst_x : std_logic; + signal quad_rst : std_logic; + signal lane_rst_x : std_logic; + signal lane_rst : std_logic; + signal rx_allow_x : std_logic; + signal rx_allow : std_logic; + signal tx_allow_x : std_logic; + signal tx_allow : std_logic; + signal align_me_x : std_logic; + signal align_me : std_logic; + signal resync_x : std_logic; + signal resync : std_logic; + signal reset_me_x : std_logic; + signal reset_me : std_logic; + + signal rx_k_q : std_logic_vector(1 downto 0); + + signal info_led : std_logic; + + signal rx_allow_q : std_logic; -- clock domain changed signal + signal tx_allow_q : std_logic; + signal swap_bytes : std_logic; + + -- status inputs from SFP + signal sfp_prsnt_n : std_logic; -- synchronized input signals + signal sfp_los : std_logic; -- synchronized input signals begin - REFCLK2CORE <= refck2core; ---Instantiation of serdes module ---------------------- +-------------------------------------------------------------------------- +-- Main control state machine, startup control for SFP +-------------------------------------------------------------------------- +clock <= CLK; + +-- Input synchronizer + +THE_SFP_STATUS_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN(1) => SD_PRSNT_N_IN, + D_IN(0) => SD_LOS_IN, + CLK0 => clock, + CLK1 => clock, + D_OUT(0) => sfp_prsnt_n, + D_OUT(1) => sfp_los + ); + +-- Transfering the komma delimiter in the *training* phase +THE_RX_K_SYNC: signal_sync + generic map( + DEPTH => 3, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN => rx_k, + CLK0 => clock, + CLK1 => clock, + D_OUT => rx_k_q + ); + + +-- "Swap Bytes" indicator +THE_SWAP_BYTES_PROC: process( clock ) +begin + if( rising_edge(clock) ) then + if ( (align_me = '1') and (rx_k_q = "10") ) then + swap_bytes <= '1'; + elsif( (align_me = '1') and (rx_k_q = "01") ) then + swap_bytes <= '0'; + end if; + end if; +end process THE_SWAP_BYTES_PROC; + +-- Timing counter for reset sequencing +THE_TIMING_COUNTER_PROC: process( clock ) +begin + if( rising_edge(clock) ) then + if ( rst_ctr = '1' ) then + timing_ctr <= (others => '0'); + elsif( ce_ctr = '1' ) then + timing_ctr <= timing_ctr + 1; + end if; + end if; +end process THE_TIMING_COUNTER_PROC; + +-- State machine +-- state registers +STATE_MEM: process( clock, RESET ) +begin + if( RESET = '1' ) then + CURRENT_STATE <= SLEEP; + ce_ctr <= '0'; + rst_ctr <= '0'; + quad_rst <= '1'; + lane_rst <= '1'; + rx_allow <= '0'; + tx_allow <= '0'; + align_me <= '0'; + reset_me <= '1'; + resync <= '1'; + med_error <= ERROR_NC; + elsif( rising_edge(clock) ) then + CURRENT_STATE <= NEXT_STATE; + ce_ctr <= ce_ctr_x; + rst_ctr <= rst_ctr_x; + quad_rst <= quad_rst_x; + lane_rst <= lane_rst_x; + rx_allow <= rx_allow_x; + tx_allow <= tx_allow_x; + align_me <= align_me_x; + reset_me <= reset_me_x; + resync <= resync_x; + med_error <= med_error_x; + end if; +end process STATE_MEM; + +-- state transitions +STATE_TRANSFORM: process( CURRENT_STATE, sfp_prsnt_n, sfp_los, timing_ctr, link_error, rst_ctr, link_ok, rx_k_q ) +begin + NEXT_STATE <= SLEEP; -- avoid latches + ce_ctr_x <= '0'; + rst_ctr_x <= '0'; + quad_rst_x <= '0'; + lane_rst_x <= '0'; + rx_allow_x <= '0'; + tx_allow_x <= '0'; + align_me_x <= '0'; + reset_me_x <= '1'; + resync_x <= '1'; + med_error_x <= ERROR_NC; + case CURRENT_STATE is + when SLEEP => if( sfp_prsnt_n = '0' ) then + NEXT_STATE <= QRST; -- do a correctly timed QUAD reset (about 150ns) + rst_ctr_x <= '1'; + quad_rst_x <= '1'; + lane_rst_x <= '1'; + else + NEXT_STATE <= SLEEP; -- wait for SFP present signal + ce_ctr_x <= '1'; + quad_rst_x <= '1'; + lane_rst_x <= '1'; + end if; + when QRST => if( (timing_ctr(4) = '1') and (rst_ctr = '0') ) then + NEXT_STATE <= WPAR; -- release QUAD_RST, wait for RLOL and PLOL deassertation + lane_rst_x <= '1'; + else + NEXT_STATE <= QRST; -- count delay + ce_ctr_x <= '1'; + quad_rst_x <= '1'; + lane_rst_x <= '1'; + end if; + when WPAR => if ( sfp_prsnt_n = '1' ) then + NEXT_STATE <= SLEEP; -- taking out SFP during operation must be taken into account + quad_rst_x <= '1'; + lane_rst_x <= '1'; + ce_ctr_x <= '1'; + elsif( (link_error(4) = '0') and (link_error(5) = '0') and (sfp_los = '0') ) then + NEXT_STATE <= WLOS; + rst_ctr_x <= '1'; + else + NEXT_STATE <= WPAR; -- wait for RLOL and PLOL and incoming signal from SFP + lane_rst_x <= '1'; + ce_ctr_x <= '1'; + end if; + when WLOS => if ( (timing_ctr(27) = '0') and (timing_ctr(26) = '0') and (rst_ctr = '0') ) then + NEXT_STATE <= WLOS; + resync_x <= '0'; + ce_ctr_x <= '1'; + elsif( (timing_ctr(27) = '1') and (rst_ctr = '0') ) then + NEXT_STATE <= ALIGN; -- debounce before aligning + align_me_x <= '1'; + reset_me_x <= '0'; + ce_ctr_x <= '1'; + else + NEXT_STATE <= WLOS; -- no fibre, no alignment + ce_ctr_x <= '1'; + end if; + when ALIGN => if( (rx_k_q = "10") or (rx_k_q = "01") ) then + NEXT_STATE <= WRXA; -- one komma character has been received + --rst_ctr_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_WAIT; + else + NEXT_STATE <= ALIGN; -- wait for komma character + ce_ctr_x <= '1'; + align_me_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_WAIT; + end if; + when WRXA => if( (timing_ctr(28) = '1') and (rst_ctr = '0') ) then + NEXT_STATE <= WTXA; -- wait cycle done, allow reception of data + rst_ctr_x <= '1'; + rx_allow_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_WAIT; + else + NEXT_STATE <= WRXA; -- wait one complete cycle (2^27 x 10ns = 1.3s) + ce_ctr_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_WAIT; + end if; + when WTXA => if( (timing_ctr(28) = '1') and (rst_ctr = '0') ) then + NEXT_STATE <= LINK; -- wait cycle done, allow transmission of data + rst_ctr_x <= '1'; + rx_allow_x <= '1'; + tx_allow_x <= '1'; + ce_ctr_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_OK; + else + NEXT_STATE <= WTXA; -- wait one complete cycle (2^27 x 10ns = 1.3s) + ce_ctr_x <= '1'; + rx_allow_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_WAIT; + end if; + when LINK => if( (sfp_prsnt_n = '1') or (sfp_los = '1') ) then + NEXT_STATE <= SLEEP; + quad_rst_x <= '1'; + lane_rst_x <= '1'; + rst_ctr_x <= '1'; + else + NEXT_STATE <= LINK; + rx_allow_x <= '1'; + tx_allow_x <= '1'; + ce_ctr_x <= '1'; + reset_me_x <= '0'; + med_error_x <= ERROR_OK; + end if; + when others => NEXT_STATE <= SLEEP; + end case; +end process STATE_TRANSFORM; - s : serdes - PORT map( - core_txrefclk => CLK, --CLK - core_rxrefclk => CLK, - hdinp2 => SD_RXD_P, --RX Data input - hdinn2 => SD_RXD_N, --RX Data input - ff_rxiclk_ch2 => ff_rxhalfclk, --CLK ff_txhalfclk - ff_txiclk_ch2 => ff_txhalfclk, --CLK ff_txhalfclk - ff_ebrd_clk_2 => ff_rxhalfclk, --CLK ff_txfullclk - ff_txdata_ch2 => tx_data, --internal tx data - ff_tx_k_cntrl_ch2 => tx_k, --control character flag 00 - ff_force_disp_ch2 => "00", --activate disparity value 00 - ff_disp_sel_ch2 => "00", --disparity value in 00 - ff_correct_disp_ch2 => "00", --disparity check 00 - ffc_rrst_ch2 => '0', --RESET - ffc_signal_detect_ch2 => '1', --enable signal detect - ffc_enable_cgalign_ch2 => '1', --enable comma aligner 0 +THE_DECODE_PROC: process( CURRENT_STATE, timing_ctr ) +begin + case CURRENT_STATE is + when SLEEP => state_bits <= "0000"; + info_led <= '0'; + when QRST => state_bits <= "0001"; + info_led <= timing_ctr(21); -- too high + when WPAR => state_bits <= "0010"; + info_led <= timing_ctr(21) and timing_ctr(24); -- nice frequence for human eye + when WLOS => state_bits <= "0011"; + info_led <= timing_ctr(22); + when ALIGN => state_bits <= "0100"; + info_led <= timing_ctr(23); + when WRXA => state_bits <= "0101"; + info_led <= timing_ctr(24); + when WTXA => state_bits <= "0110"; + info_led <= timing_ctr(25); + when LINK => state_bits <= "0111"; + info_led <= '1'; + when others => state_bits <= "1111"; + info_led <= '0'; + end case; +end process THE_DECODE_PROC; + +THE_RX_ALLOW_SYNC: signal_sync + generic map( + DEPTH => 2, + WIDTH => 2 + ) + port map( + RESET => RESET, + D_IN(0) => rx_allow, + D_IN(1) => tx_allow, + CLK0 => clock, --ff_rxhalfclk, + CLK1 => clock, --ff_rxhalfclk, + D_OUT(0) => rx_allow_q, + D_OUT(1) => tx_allow_q + ); + +-------------------------------------------------------------------------- +-------------------------------------------------------------------------- + +ffc_quad_rst <= quad_rst; +ffc_lane_tx_rst_ch2 <= lane_rst; +ffc_lane_rx_rst_ch2 <= lane_rst; + + + +-- SerDes clock output to FPGA fabric +refclk2core_out <= refck2core; + +-- Instantiation of serdes module +THE_SERDES: serdes +port map( core_txrefclk => clock, + core_rxrefclk => dcs_clk, --clk_in, + hdinp2 => sd_rxd_p_in, + hdinn2 => sd_rxd_n_in, + ff_rxiclk_ch2 => ff_rxhalfclk, + ff_txiclk_ch2 => ff_txhalfclk, + ff_ebrd_clk_2 => ff_rxhalfclk, -- not used, just for completeness + ff_txdata_ch2 => tx_data, + ff_tx_k_cntrl_ch2 => tx_k, + ff_force_disp_ch2 => "00", + ff_disp_sel_ch2 => "00", + ff_correct_disp_ch2 => "00", + ffc_rrst_ch2 => '0', + ffc_signal_detect_ch2 => '1', + ffc_enable_cgalign_ch2 => resync, --'1', ffc_lane_tx_rst_ch2 => ffc_lane_tx_rst_ch2, ffc_lane_rx_rst_ch2 => ffc_lane_rx_rst_ch2, - ffc_txpwdnb_ch2 => '1', --power down active low - ffc_rxpwdnb_ch2 => '1', --power down active low - ffc_macro_rst => '0', --RESET - ffc_quad_rst => ffc_quad_rst, --RESET - ffc_trst => '0', --RESET - hdoutp2 => SD_TXD_P, --TX Data output - hdoutn2 => SD_TXD_N, --TX Data output - ff_rxdata_ch2 => rx_data, --internal rx data - ff_rx_k_cntrl_ch2 => rx_k, --control character flag - ff_rxfullclk_ch2 => open, --RX recovered CLK - ff_rxhalfclk_ch2 => ff_rxhalfclk, --RX half recovered CLK - ff_disp_err_ch2 => open, --disparity error flag - ff_cv_ch2 => link_error(7 downto 6), --code violation flag - ffs_rlos_lo_ch2 => link_error(8), --signal loss - ffs_ls_sync_status_ch2 => link_ok(0), --link state machine status - ffs_cc_underrun_ch2 => link_error(0), --Clock compensator FIFO error - ffs_cc_overrun_ch2 => link_error(1), --Clock compensator FIFO error - ffs_txfbfifo_error_ch2 => link_error(2), --TX FIFO error - ffs_rxfbfifo_error_ch2 => link_error(3), --RX FIFO error - ffs_rlol_ch2 => link_error(4), --Clock Recovery error - oob_out_ch2 => open, --internal output same as real serdes output - ff_txfullclk => open, --TX CLK - ff_txhalfclk => ff_txhalfclk, --TX CLK/2 <- interface CLK from MED to Serdes - refck2core => refck2core, --Reference CLK - ffs_plol => link_error(5) --TX PLL error (not locked) - ); - - ---RX Fifo & Data output ---------------------- - FIFO_SFP_TO_INT: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => CLK, + ffc_txpwdnb_ch2 => '1', + ffc_rxpwdnb_ch2 => '1', + ffc_macro_rst => '0', + ffc_quad_rst => ffc_quad_rst, + ffc_trst => '0', + hdoutp2 => sd_txd_p_out, + hdoutn2 => sd_txd_n_out, + ff_rxdata_ch2 => rx_data, + ff_rx_k_cntrl_ch2 => rx_k, + ff_rxfullclk_ch2 => open, + ff_rxhalfclk_ch2 => ff_rxhalfclk, + ff_disp_err_ch2 => open, + ff_cv_ch2 => link_error(7 downto 6), + ffs_rlos_lo_ch2 => link_error(8), + ffs_ls_sync_status_ch2 => link_ok(0), + ffs_cc_underrun_ch2 => link_error(0), + ffs_cc_overrun_ch2 => link_error(1), + ffs_txfbfifo_error_ch2 => link_error(2), + ffs_rxfbfifo_error_ch2 => link_error(3), + ffs_rlol_ch2 => link_error(4), + oob_out_ch2 => open, + ff_txfullclk => open, + ff_txhalfclk => ff_txhalfclk, + refck2core => refck2core, + ffs_plol => link_error(5) + ); + +link_error(9) <= '0'; -- unused + +---- Implement the TN1171 bugfix +dcs_select <= link_error(4); +dcs_clk_0 <= flip_flop xor ff_rxhalfclk; +dcs_clk_1 <= clock; + +-- Flipflop for phase shifting in case of repeated loss of lock +THE_FLIP_FLOP_PROC: process( dcs_select, ffc_quad_rst ) +begin + if ( ffc_quad_rst = '1' ) then + flip_flop <= '0'; + elsif( rising_edge(dcs_select) ) then + flip_flop <= not flip_flop; + end if; +end process THE_FLIP_FLOP_PROC; + +THE_DCS: dcs +-- synthesis translate_off +generic map ( DCSMODE => "POS" ) +-- synthesis translate_on +port map( SEL => dcs_select, + CLK0 => dcs_clk_0, + CLK1 => dcs_clk_1, + DCSOUT => dcs_clk + ); + +------------------------------------------------------------------------- +-- RX Fifo & Data output +------------------------------------------------------------------------- +THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => clock, write_clock_in => ff_rxhalfclk, read_enable_in => fifo_rx_rd_en, - write_enable_in => fifo_rx_wr_en, - fifo_gsr_in => fifo_rx_reset, - write_data_in => fifo_rx_din, - read_data_out => fifo_rx_dout, - full_out => fifo_rx_full, - empty_out => fifo_rx_empty - ); - - fifo_rx_reset <= reset or not rx_allow; - fifo_rx_rd_en <= '1'; - - process(ff_rxhalfclk) - begin - if rising_edge(ff_rxhalfclk) then - last_rx <= rx_k(1) & rx_data(15 downto 8); - if swap_bytes = '0' then - fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); - fifo_rx_wr_en <= not rx_k(0) and rx_allow; - else - fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); - fifo_rx_wr_en <= not last_rx(8) and rx_allow; - end if; - end if; - end process; - - buf_MED_DATA_OUT <= fifo_rx_dout(15 downto 0); - buf_MED_DATAREADY_OUT <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty; - buf_MED_PACKET_NUM_OUT <= rx_counter; - MED_READ_OUT <= tx_allow; - - process(CLK) - begin - if rising_edge(CLK) then - MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; - MED_DATA_OUT <= buf_MED_DATA_OUT; - MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; - end if; - end process; + write_enable_in => fifo_rx_wr_en, + fifo_gsr_in => fifo_rx_reset, + write_data_in => fifo_rx_din, + read_data_out => fifo_rx_dout, + full_out => fifo_rx_full, + empty_out => fifo_rx_empty + ); + +fifo_rx_reset <= RESET; +fifo_rx_rd_en <= '1'; + +-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path +THE_BYTE_SWAP_PROC: process( ff_rxhalfclk ) +begin + if( rising_edge(ff_rxhalfclk) ) then + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; + end if; +end process THE_BYTE_SWAP_PROC; + +buf_med_data_out <= fifo_rx_dout(15 downto 0); +buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; +buf_med_packet_num_out <= rx_counter; +med_read_out <= tx_allow_q; + +THE_SYNC_PROC: process( clock ) +begin + if( rising_edge(clock) ) then + if RESET = '1' then + med_dataready_out <= '0'; + else + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + end if; + end if; +end process THE_SYNC_PROC; --rx packet counter --------------------- - rx_packets : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' or reset_interface = '1' then - rx_counter <= c_H0; +THE_RX_PACKETS_PROC: process( clock ) +begin + if( rising_edge(clock) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if RESET = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); else - last_fifo_rx_empty <= fifo_rx_empty; - if buf_MED_DATAREADY_OUT = '1' then - if rx_counter = c_max_word_number then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; - end if; - end if; + rx_counter <= rx_counter + 1; end if; end if; - end process; - + end if; + end if; +end process; --TX Fifo & Data output to Serdes --------------------- - FIFO_INT_TO_SFP: trb_net_fifo_16bit_bram_dualport - generic map( - USE_STATUS_FLAGS => c_NO - ) - port map( - read_clock_in => ff_txhalfclk, - write_clock_in => CLK, +THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport +generic map( + USE_STATUS_FLAGS => c_NO + ) +port map( read_clock_in => ff_txhalfclk, + write_clock_in => clock, read_enable_in => fifo_tx_rd_en, - write_enable_in => fifo_tx_wr_en, - fifo_gsr_in => fifo_tx_reset, - write_data_in => fifo_tx_din, - read_data_out => fifo_tx_dout, - full_out => fifo_tx_full, - empty_out => fifo_tx_empty - ); - fifo_tx_reset <= reset or not tx_allow; - fifo_tx_din <= MED_PACKET_NUM_IN(2) & MED_PACKET_NUM_IN(0) & MED_DATA_IN; - fifo_tx_wr_en <= MED_DATAREADY_IN and tx_allow; - fifo_tx_rd_en <= tx_allow; - - make_serdes_input : process(ff_txhalfclk) - begin - if rising_edge(ff_txhalfclk) then - last_fifo_tx_empty <= fifo_tx_empty; - if last_fifo_tx_empty = '1' then - tx_data <= x"c5bc"; - tx_k <= "01"; - else - tx_data <= fifo_tx_dout(15 downto 0); - tx_k <= "00"; - end if; - end if; - end process; + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty + ); +fifo_tx_reset <= RESET; +fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; +fifo_tx_wr_en <= med_dataready_in and tx_allow_q; +fifo_tx_rd_en <= tx_allow; ---link start-up state machine ----------------------- ---generate quad reset with primary clock - gen_serdes_reset : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - serdes_reset_counter <= (others => '0'); - serdes_reset <= '1'; - else - if serdes_reset_counter(6) = '1' then - serdes_reset <= '0'; - else - serdes_reset_counter <= serdes_reset_counter + 1; - end if; - end if; - end if; - end process; - ---start-up with derived clock - medium_states : process(ff_rxhalfclk, RESET) - begin - if RESET = '1' or serdes_reset = '1' then - swap_bytes <= '0'; - tx_allow <= '0'; - rx_allow <= '0'; - state <= waitplolandrlol; - MED_ERROR_OUT <= ERROR_NC; - counter <= (others => '0'); - elsif rising_edge(ff_rxhalfclk) then - counter <= counter + 1; - case state is - when waitplolandrlol => - if (link_error(5) = '0' and link_error(4) = '0') THEN - state <= waitrxallow; - counter <= (others => '0'); - end if; - MED_ERROR_OUT <= ERROR_NC; - when waitrxallow => - if counter(28) = '1' then - counter <= (others => '0'); - rx_allow <= '1'; - state <= waittxallow; - end if; - if counter(27) = '1' then - if rx_k = "10" then - swap_bytes <= '1'; - elsif rx_k = "01" then - swap_bytes <= '0'; - end if; - end if; - MED_ERROR_OUT <= ERROR_WAIT; - when waittxallow => - if counter(28) = '1' then - tx_allow <= '1'; - state <= working; - end if; - MED_ERROR_OUT <= ERROR_WAIT; - when working => - MED_ERROR_OUT <= ERROR_OK; - end case; - if (link_error(6) = '1' or link_error(7) = '1') and ffc_lane_rx_rst_ch2 = '0' then - counter <= (others => '0'); - rx_allow <= '0'; - tx_allow <= '0'; - state <= waitrxallow; - MED_ERROR_OUT <= ERROR_WAIT; - end if; - end if; - end process; - - ffc_quad_rst <= '1' when serdes_reset = '1' else RESET; - ffc_lane_tx_rst_ch2 <= '1' when serdes_reset = '1' or state = waitplolandrlol else '0'; - ffc_lane_rx_rst_ch2 <= '1' when serdes_reset = '1' or state = waitplolandrlol else '0'; - - - process(state) - begin - case state is - when start => state_bits <= "000"; - when waitplolandrlol => state_bits <= "001"; - when waitrxallow => state_bits <= "010"; - when waittxallow => state_bits <= "011"; - when working => state_bits <= "100"; - when others => state_bits <= "111"; - end case; - end process; - - STAT_DEBUG(2 downto 0) <= state_bits; - STAT_DEBUG(9 downto 3) <= (others => '0'); - STAT_DEBUG(19 downto 10) <= link_error; - STAT_DEBUG(20) <= link_ok(0); - STAT_DEBUG(38 downto 21) <= fifo_rx_din; - STAT_DEBUG(39) <= swap_bytes; - STAT_DEBUG(40) <= fifo_rx_wr_en; - STAT_DEBUG(63 downto 41) <= (others => '0'); +THE_SERDES_INPUT_PROC: process( ff_txhalfclk ) +begin + if( rising_edge(ff_txhalfclk) ) then + last_fifo_tx_empty <= fifo_tx_empty; + if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then + tx_data <= x"c5bc"; + tx_k <= "01"; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + end if; + end if; +end process THE_SERDES_INPUT_PROC; + +-- +med_error_out <= med_error; +link_led <= (timing_ctr(24) or tx_allow_q) and not sfp_los; + + +stat_op(8 downto 0) <= (others => '0'); -- unused +stat_op(9) <= link_led; +stat_op(10) <= buf_med_dataready_out; --rx led +stat_op(11) <= not tx_k(0); --tx led +stat_op(13 downto 12)<= (others => '0'); -- unused +stat_op(14) <= reset_me; -- reset out +stat_op(15) <= '0'; -- protocol error + +-- Debug output +stat_debug(3 downto 0) <= state_bits; +stat_debug(4) <= align_me; +stat_debug(5) <= sfp_prsnt_n; +stat_debug(6) <= rx_k(0); +stat_debug(7) <= rx_k(1); +stat_debug(8) <= rx_k_q(0); +stat_debug(9) <= rx_k_q(1); +--stat_debug(9 downto 7) <= (others => '0'); +stat_debug(19 downto 10) <= link_error; +stat_debug(20) <= link_ok(0); +stat_debug(38 downto 21) <= fifo_rx_din; +stat_debug(39) <= swap_bytes; +stat_debug(40) <= fifo_rx_wr_en; +stat_debug(41) <= info_led; +stat_debug(42) <= resync; +stat_debug(59 downto 43) <= (others => '0'); +stat_debug(63 downto 60) <= link_error(3 downto 0); end architecture; \ No newline at end of file diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 19c5d3b..e2fb644 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -77,9 +77,8 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal fifo_wr_en_m : std_logic; signal fifo_empty_m : std_logic; signal fifo_full_m : std_logic; - signal fifo_almost_empty_m, fifo_almost_empty_a : std_logic; signal fifo_valid_read_m, fifo_valid_read_a : std_logic; - signal fifo_underflow_a, fifo_underflow_m : std_logic; + signal fifo_reset : std_logic; signal fifo_status_a : std_logic_vector(3 downto 0); diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 97aad46..821e2d1 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -34,7 +34,8 @@ entity trb_net16_obuf is INT_READ_OUT : out std_logic; -- Status and control port STAT_BUFFER : out std_logic_vector (31 downto 0); - CTRL_BUFFER : in std_logic_vector (31 downto 0) + CTRL_BUFFER : in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) ); end entity; @@ -110,6 +111,9 @@ architecture trb_net16_obuf_arch of trb_net16_obuf is signal CRC_RESET, CRC_enable : std_logic; signal CRC : std_logic_vector(15 downto 0); + signal buf_MED_DATAREADY_OUT : std_logic; + signal buf_MED_PACKET_NUM_OUT : std_logic_vector(c_NUM_WIDTH-1 downto 0); + begin -- gen_sbuf : if SECURE_MODE = 1 generate SBUF:trb_net16_sbuf @@ -125,12 +129,14 @@ begin COMB_READ_IN => comb_read, COMB_DATA_IN => current_output_data_buffer, COMB_PACKET_NUM_IN => current_output_num_buffer, - SYN_DATAREADY_OUT => MED_DATAREADY_OUT, + SYN_DATAREADY_OUT => buf_MED_DATAREADY_OUT, SYN_DATA_OUT => MED_DATA_OUT, - SYN_PACKET_NUM_OUT => MED_PACKET_NUM_OUT, + SYN_PACKET_NUM_OUT => buf_MED_PACKET_NUM_OUT, SYN_READ_IN => MED_READ_IN ); + MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; comb_read <= '1'; process(CLK) @@ -210,7 +216,7 @@ begin begin if rising_edge(CLK) then if RESET = '1' then - transfer_counter <= c_max_word_number; + transfer_counter <= c_H0; elsif comb_dataready = '1' then if transfer_counter = c_max_word_number then transfer_counter <= (others => '0'); @@ -412,8 +418,13 @@ begin end if; end if; end process; - - end generate; +STAT_DEBUG(0) <= comb_dataready; +STAT_DEBUG(3 downto 1) <= transfer_counter; +STAT_DEBUG(4) <= buf_MED_DATAREADY_OUT; +STAT_DEBUG(7 downto 5) <= buf_MED_PACKET_NUM_OUT; +STAT_DEBUG(8) <= sbuf_free; +STAT_DEBUG(9) <= comb_next_read; + end architecture; \ No newline at end of file diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index a28f9eb..473ae7d 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -22,9 +22,10 @@ entity trb_net16_regIO is USED_CTRL_BITMASK : std_logic_vector(2**(3)*32-1 downto 0) := (others => '1'); USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0'); + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678" @@ -101,8 +102,10 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is component trb_net16_addresses is generic( - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := x"1000_2000_3654_4876_5bcd_6ef1" + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001" ); port( CLK : in std_logic; @@ -205,7 +208,9 @@ begin addresses : trb_net16_addresses generic map( INIT_ADDRESS => INIT_ADDRESS, - INIT_UNIQUE_ID => INIT_UNIQUE_ID + INIT_UNIQUE_ID => INIT_UNIQUE_ID, + INIT_BOARD_INFO=> INIT_BOARD_INFO, + INIT_ENDPOINT_ID => INIT_ENDPOINT_ID ) port map( CLK => CLK, @@ -233,11 +238,11 @@ begin buf_DAT_DATA_OUT <= saved_Reg_high & saved_Reg_low; fsm : process(current_state, - API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN, API_RUN_IN, + API_DATA_IN, API_PACKET_NUM_IN, API_TYP_IN, API_DATAREADY_IN, API_READ_IN, HDR_F1, HDR_F2, HDR_F3, address, saved_Reg_high, saved_Reg_low, saved_operation, buf_API_SEND_OUT, next_packet_counter, buf_API_DATA_OUT, buf_API_SHORT_TRANSFER_OUT, REGISTERS_IN, buf_REGISTERS_OUT, reg_enable_pattern, DAT_NO_MORE_DATA_IN, - buf_DAT_DATA_OUT, buf_DAT_ADDR_OUT, DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED, + DAT_DATAREADY_IN, buf_DAT_DATA_IN, ADR_REJECTED, ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT, length, dont_understand, buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT ) diff --git a/trb_net_med_8bit_slow.vhd b/trb_net_med_8bit_slow.vhd index fb34b38..8f63838 100644 --- a/trb_net_med_8bit_slow.vhd +++ b/trb_net_med_8bit_slow.vhd @@ -83,7 +83,9 @@ begin buf_STAT(1 downto 0) <= (others => '0'); buf_STAT(5 downto 2) <= MED_DATA_IN(11 downto 8); - buf_STAT(31 downto 6)<= (others => '0'); + buf_STAT(18 downto 6)<= (others => '0'); + buf_STAT(31 downto 19) <= reg_MED_PARITY_IN & reg_MED_CARRIER_IN & reg_MED_TRANSMISSION_CLK_IN & reg_MED_FIRST_PACKET_IN & MED_DATA_IN(11) & reg_MED_DATA_IN; + MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT; diff --git a/trb_net_onewire.vhd b/trb_net_onewire.vhd index 7bba8c7..212e726 100644 --- a/trb_net_onewire.vhd +++ b/trb_net_onewire.vhd @@ -322,8 +322,8 @@ begin ram_wr <= '0'; if recv_bit_ready = '1' and (send_rom = '1' or reading_temp = '1') then buf_STAT <= not buf_STAT; - ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4)); - ram_addr(2) <= not or_all(bitcounter_vector(5 downto 4)); + ram_addr(1 downto 0) <= (bitcounter_vector(5 downto 4))-1; + ram_addr(2) <= '0'; word(14 downto 0) <= word(15 downto 1); word(15) <= recv_bit; if bitcounter_vector(3 downto 0) = "0000" and send_rom = '1' then -- 2.43.0